Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/sparc/vm/c1_Defs_sparc.hpp@ac637b7220d1 (annotated)
src/cpu/sparc/vm/c1_Defs_sparc.hpp
Tue, 30 Nov 2010 23:23:40 -0800
- author
- iveresov
- date
- Tue, 30 Nov 2010 23:23:40 -0800
- changeset 2344
- ac637b7220d1
- parent 2314
- f95d63e2154a
- child 6876
- 710a3c8b516e
- permissions
- -rw-r--r--
6985015: C1 needs to support compressed oops
Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered.
Reviewed-by: twisti, kvn, never, phh
| duke@435 | 1 | /* |
| stefank@2314 | 2 | * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| duke@435 | 4 | * |
| duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
| duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
| duke@435 | 7 | * published by the Free Software Foundation. |
| duke@435 | 8 | * |
| duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
| duke@435 | 13 | * accompanied this code). |
| duke@435 | 14 | * |
| duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
| duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
| duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| duke@435 | 18 | * |
| trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
| trims@1907 | 21 | * questions. |
| duke@435 | 22 | * |
| duke@435 | 23 | */ |
| duke@435 | 24 | |
| stefank@2314 | 25 | #ifndef CPU_SPARC_VM_C1_DEFS_SPARC_HPP |
| stefank@2314 | 26 | #define CPU_SPARC_VM_C1_DEFS_SPARC_HPP |
| stefank@2314 | 27 | |
| duke@435 | 28 | // native word offsets from memory address (big endian) |
| duke@435 | 29 | enum { |
| duke@435 | 30 | pd_lo_word_offset_in_bytes = BytesPerInt, |
| duke@435 | 31 | pd_hi_word_offset_in_bytes = 0 |
| duke@435 | 32 | }; |
| duke@435 | 33 | |
| duke@435 | 34 | |
| duke@435 | 35 | // explicit rounding operations are not required to implement the strictFP mode |
| duke@435 | 36 | enum { |
| duke@435 | 37 | pd_strict_fp_requires_explicit_rounding = false |
| duke@435 | 38 | }; |
| duke@435 | 39 | |
| duke@435 | 40 | |
| duke@435 | 41 | // registers |
| duke@435 | 42 | enum { |
| duke@435 | 43 | pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission |
| never@1363 | 44 | pd_nof_caller_save_cpu_regs_frame_map = 10, // number of cpu registers killed by calls |
| duke@435 | 45 | pd_nof_cpu_regs_reg_alloc = 20, // number of registers that are visible to register allocator |
| duke@435 | 46 | pd_nof_cpu_regs_linearscan = 32,// number of registers visible linear scan |
| duke@435 | 47 | pd_first_cpu_reg = 0, |
| duke@435 | 48 | pd_last_cpu_reg = 31, |
| duke@435 | 49 | pd_last_allocatable_cpu_reg = 19, |
| duke@435 | 50 | pd_first_callee_saved_reg = 0, |
| duke@435 | 51 | pd_last_callee_saved_reg = 13, |
| duke@435 | 52 | |
| duke@435 | 53 | pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission |
| duke@435 | 54 | pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls |
| duke@435 | 55 | pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator |
| duke@435 | 56 | pd_nof_fpu_regs_linearscan = 32, // number of registers visible to linear scan |
| duke@435 | 57 | pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
| duke@435 | 58 | pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1, |
| duke@435 | 59 | |
| duke@435 | 60 | pd_nof_xmm_regs_linearscan = 0, |
| duke@435 | 61 | pd_nof_caller_save_xmm_regs = 0, |
| duke@435 | 62 | pd_first_xmm_reg = -1, |
| duke@435 | 63 | pd_last_xmm_reg = -1 |
| duke@435 | 64 | }; |
| duke@435 | 65 | |
| duke@435 | 66 | |
| duke@435 | 67 | // for debug info: a float value in a register is saved in single precision by runtime stubs |
| duke@435 | 68 | enum { |
| duke@435 | 69 | pd_float_saved_as_double = false |
| duke@435 | 70 | }; |
| stefank@2314 | 71 | |
| stefank@2314 | 72 | #endif // CPU_SPARC_VM_C1_DEFS_SPARC_HPP |
