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src/cpu/ppc/vm/assembler_ppc.hpp@ac27a9c85bea (annotated)

src/cpu/ppc/vm/assembler_ppc.hpp

Thu, 24 May 2018 18:41:44 +0800

author

aoqi

date

Thu, 24 May 2018 18:41:44 +0800

changeset 8856

ac27a9c85bea

parent 8608

0d78aecb0948

parent 7535

7ae4e26cb1e0

child 9041

95a08233f46c

permissions

-rw-r--r--

Merge

aoqi@0	1	/*
aoqi@0	2	* Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0	3	* Copyright 2012, 2013 SAP AG. All rights reserved.
aoqi@0	4	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0	5	*
aoqi@0	6	* This code is free software; you can redistribute it and/or modify it
aoqi@0	7	* under the terms of the GNU General Public License version 2 only, as
aoqi@0	8	* published by the Free Software Foundation.
aoqi@0	9	*
aoqi@0	10	* This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0	13	* version 2 for more details (a copy is included in the LICENSE file that
aoqi@0	14	* accompanied this code).
aoqi@0	15	*
aoqi@0	16	* You should have received a copy of the GNU General Public License version
aoqi@0	17	* 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0	18	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0	19	*
aoqi@0	20	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0	21	* or visit www.oracle.com if you need additional information or have any
aoqi@0	22	* questions.
aoqi@0	23	*
aoqi@0	24	*/
aoqi@0	25
aoqi@0	26	#ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
aoqi@0	27	#define CPU_PPC_VM_ASSEMBLER_PPC_HPP
aoqi@0	28
aoqi@0	29	#include "asm/register.hpp"
aoqi@0	30
aoqi@0	31	// Address is an abstraction used to represent a memory location
aoqi@0	32	// as used in assembler instructions.
aoqi@0	33	// PPC instructions grok either baseReg + indexReg or baseReg + disp.
aoqi@0	34	// So far we do not use this as simplification by this class is low
aoqi@0	35	// on PPC with its simple addressing mode. Use RegisterOrConstant to
aoqi@0	36	// represent an offset.
aoqi@0	37	class Address VALUE_OBJ_CLASS_SPEC {
aoqi@0	38	};
aoqi@0	39
aoqi@0	40	class AddressLiteral VALUE_OBJ_CLASS_SPEC {
aoqi@0	41	private:
aoqi@0	42	address _address;
aoqi@0	43	RelocationHolder _rspec;
aoqi@0	44
aoqi@0	45	RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
aoqi@0	46	switch (rtype) {
aoqi@0	47	case relocInfo::external_word_type:
aoqi@0	48	return external_word_Relocation::spec(addr);
aoqi@0	49	case relocInfo::internal_word_type:
aoqi@0	50	return internal_word_Relocation::spec(addr);
aoqi@0	51	case relocInfo::opt_virtual_call_type:
aoqi@0	52	return opt_virtual_call_Relocation::spec();
aoqi@0	53	case relocInfo::static_call_type:
aoqi@0	54	return static_call_Relocation::spec();
aoqi@0	55	case relocInfo::runtime_call_type:
aoqi@0	56	return runtime_call_Relocation::spec();
aoqi@0	57	case relocInfo::none:
aoqi@0	58	return RelocationHolder();
aoqi@0	59	default:
aoqi@0	60	ShouldNotReachHere();
aoqi@0	61	return RelocationHolder();
aoqi@0	62	}
aoqi@0	63	}
aoqi@0	64
aoqi@0	65	protected:
aoqi@0	66	// creation
aoqi@0	67	AddressLiteral() : _address(NULL), _rspec(NULL) {}
aoqi@0	68
aoqi@0	69	public:
aoqi@0	70	AddressLiteral(address addr, RelocationHolder const& rspec)
aoqi@0	71	: _address(addr),
aoqi@0	72	_rspec(rspec) {}
aoqi@0	73
aoqi@0	74	AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
aoqi@0	75	: _address((address) addr),
aoqi@0	76	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
aoqi@0	77
aoqi@0	78	AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
aoqi@0	79	: _address((address) addr),
aoqi@0	80	_rspec(rspec_from_rtype(rtype, (address) addr)) {}
aoqi@0	81
aoqi@0	82	intptr_t value() const { return (intptr_t) _address; }
aoqi@0	83
aoqi@0	84	const RelocationHolder& rspec() const { return _rspec; }
aoqi@0	85	};
aoqi@0	86
aoqi@0	87	// Argument is an abstraction used to represent an outgoing
aoqi@0	88	// actual argument or an incoming formal parameter, whether
aoqi@0	89	// it resides in memory or in a register, in a manner consistent
aoqi@0	90	// with the PPC Application Binary Interface, or ABI. This is
aoqi@0	91	// often referred to as the native or C calling convention.
aoqi@0	92
aoqi@0	93	class Argument VALUE_OBJ_CLASS_SPEC {
aoqi@0	94	private:
aoqi@0	95	int _number; // The number of the argument.
aoqi@0	96	public:
aoqi@0	97	enum {
aoqi@0	98	// Only 8 registers may contain integer parameters.
aoqi@0	99	n_register_parameters = 8,
aoqi@0	100	// Can have up to 8 floating registers.
aoqi@0	101	n_float_register_parameters = 8,
aoqi@0	102
aoqi@0	103	// PPC C calling conventions.
aoqi@0	104	// The first eight arguments are passed in int regs if they are int.
aoqi@0	105	n_int_register_parameters_c = 8,
aoqi@0	106	// The first thirteen float arguments are passed in float regs.
aoqi@0	107	n_float_register_parameters_c = 13,
aoqi@0	108	// Only the first 8 parameters are not placed on the stack. Aix disassembly
aoqi@0	109	// shows that xlC places all float args after argument 8 on the stack AND
aoqi@0	110	// in a register. This is not documented, but we follow this convention, too.
aoqi@0	111	n_regs_not_on_stack_c = 8,
aoqi@0	112	};
aoqi@0	113	// creation
aoqi@0	114	Argument(int number) : _number(number) {}
aoqi@0	115
aoqi@0	116	int number() const { return _number; }
aoqi@0	117
aoqi@0	118	// Locating register-based arguments:
aoqi@0	119	bool is_register() const { return _number < n_register_parameters; }
aoqi@0	120
aoqi@0	121	Register as_register() const {
aoqi@0	122	assert(is_register(), "must be a register argument");
aoqi@0	123	return as_Register(number() + R3_ARG1->encoding());
aoqi@0	124	}
aoqi@0	125	};
aoqi@0	126
aoqi@0	127	#if !defined(ABI_ELFv2)
aoqi@0	128	// A ppc64 function descriptor.
aoqi@0	129	struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
aoqi@0	130	private:
aoqi@0	131	address _entry;
aoqi@0	132	address _toc;
aoqi@0	133	address _env;
aoqi@0	134
aoqi@0	135	public:
aoqi@0	136	inline address entry() const { return _entry; }
aoqi@0	137	inline address toc() const { return _toc; }
aoqi@0	138	inline address env() const { return _env; }
aoqi@0	139
aoqi@0	140	inline void set_entry(address entry) { _entry = entry; }
aoqi@0	141	inline void set_toc( address toc) { _toc = toc; }
aoqi@0	142	inline void set_env( address env) { _env = env; }
aoqi@0	143
aoqi@0	144	inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
aoqi@0	145	inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
aoqi@0	146	inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
aoqi@0	147
aoqi@0	148	// Friend functions can be called without loading toc and env.
aoqi@0	149	enum {
aoqi@0	150	friend_toc = 0xcafe,
aoqi@0	151	friend_env = 0xc0de
aoqi@0	152	};
aoqi@0	153
aoqi@0	154	inline bool is_friend_function() const {
aoqi@0	155	return (toc() == (address) friend_toc) && (env() == (address) friend_env);
aoqi@0	156	}
aoqi@0	157
aoqi@0	158	// Constructor for stack-allocated instances.
aoqi@0	159	FunctionDescriptor() {
aoqi@0	160	_entry = (address) 0xbad;
aoqi@0	161	_toc = (address) 0xbad;
aoqi@0	162	_env = (address) 0xbad;
aoqi@0	163	}
aoqi@0	164	};
aoqi@0	165	#endif
aoqi@0	166
aoqi@0	167	class Assembler : public AbstractAssembler {
aoqi@0	168	protected:
aoqi@0	169	// Displacement routines
aoqi@0	170	static void print_instruction(int inst);
aoqi@0	171	static int patched_branch(int dest_pos, int inst, int inst_pos);
aoqi@0	172	static int branch_destination(int inst, int pos);
aoqi@0	173
aoqi@0	174	friend class AbstractAssembler;
aoqi@0	175
aoqi@0	176	// Code patchers need various routines like inv_wdisp()
aoqi@0	177	friend class NativeInstruction;
aoqi@0	178	friend class NativeGeneralJump;
aoqi@0	179	friend class Relocation;
aoqi@0	180
aoqi@0	181	public:
aoqi@0	182
aoqi@0	183	enum shifts {
aoqi@0	184	XO_21_29_SHIFT = 2,
aoqi@0	185	XO_21_30_SHIFT = 1,
aoqi@0	186	XO_27_29_SHIFT = 2,
aoqi@0	187	XO_30_31_SHIFT = 0,
aoqi@0	188	SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
aoqi@0	189	SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
aoqi@0	190	RS_SHIFT = 21u, // RS field in bits 21 -- 25
aoqi@0	191	OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
aoqi@0	192	};
aoqi@0	193
aoqi@0	194	enum opcdxos_masks {
aoqi@0	195	XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
aoqi@0	196	ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	197	ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	198	BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	199	BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	200	// trap instructions
aoqi@0	201	TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	202	TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	203	TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
aoqi@0	204	TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
aoqi@0	205	LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	206	STD_OPCODE_MASK = LD_OPCODE_MASK,
aoqi@0	207	STDU_OPCODE_MASK = STD_OPCODE_MASK,
aoqi@0	208	STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
aoqi@0	209	STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
aoqi@0	210	STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	211	STWU_OPCODE_MASK = STW_OPCODE_MASK,
aoqi@0	212	STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
aoqi@0	213	STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
aoqi@0	214	MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
aoqi@0	215	ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	216	ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
aoqi@0	217	RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
aoqi@0	218	};
aoqi@0	219
aoqi@0	220	enum opcdxos {
aoqi@0	221	ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
aoqi@0	222	ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
aoqi@0	223	ADDI_OPCODE = (14u << OPCODE_SHIFT),
aoqi@0	224	ADDIS_OPCODE = (15u << OPCODE_SHIFT),
aoqi@0	225	ADDIC__OPCODE = (13u << OPCODE_SHIFT),
aoqi@0	226	ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
aoqi@0	227	SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
aoqi@0	228	SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
aoqi@0	229	SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
aoqi@0	230	SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
aoqi@0	231	SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
aoqi@0	232	DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
aoqi@0	233	MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
aoqi@0	234	MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
aoqi@0	235	MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
aoqi@0	236	MULLI_OPCODE = (7u << OPCODE_SHIFT),
aoqi@0	237	AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
aoqi@0	238	ANDI_OPCODE = (28u << OPCODE_SHIFT),
aoqi@0	239	ANDIS_OPCODE = (29u << OPCODE_SHIFT),
aoqi@0	240	ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
aoqi@0	241	ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
aoqi@0	242	OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
aoqi@0	243	ORI_OPCODE = (24u << OPCODE_SHIFT),
aoqi@0	244	ORIS_OPCODE = (25u << OPCODE_SHIFT),
aoqi@0	245	XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
aoqi@0	246	XORI_OPCODE = (26u << OPCODE_SHIFT),
aoqi@0	247	XORIS_OPCODE = (27u << OPCODE_SHIFT),
aoqi@0	248
aoqi@0	249	NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
aoqi@0	250
aoqi@0	251	RLWINM_OPCODE = (21u << OPCODE_SHIFT),
aoqi@0	252	CLRRWI_OPCODE = RLWINM_OPCODE,
aoqi@0	253	CLRLWI_OPCODE = RLWINM_OPCODE,
aoqi@0	254
aoqi@0	255	RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
aoqi@0	256
aoqi@0	257	SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
aoqi@0	258	SLWI_OPCODE = RLWINM_OPCODE,
aoqi@0	259	SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
aoqi@0	260	SRWI_OPCODE = RLWINM_OPCODE,
aoqi@0	261	SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
aoqi@0	262	SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
aoqi@0	263
aoqi@0	264	CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
aoqi@0	265	CMPI_OPCODE = (11u << OPCODE_SHIFT),
aoqi@0	266	CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
aoqi@0	267	CMPLI_OPCODE = (10u << OPCODE_SHIFT),
aoqi@0	268
aoqi@0	269	ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
aoqi@0	270
goetz@7222	271	// Special purpose registers
goetz@7222	272	MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
goetz@7222	273	MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
goetz@7222	274
goetz@7222	275	MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
goetz@7222	276	MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
goetz@7222	277
goetz@7222	278	MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
goetz@7222	279	MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
goetz@7222	280
goetz@7222	281	MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
goetz@7222	282	MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
goetz@7222	283
goetz@7222	284	MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
goetz@7222	285	MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
goetz@7222	286
goetz@7222	287	MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT),
goetz@7222	288	MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT),
goetz@7222	289	MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT),
goetz@7222	290	MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT),
goetz@7222	291	MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT),
goetz@7222	292	MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT),
goetz@7222	293	MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT),
goetz@7222	294	MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT),
goetz@7222	295
goetz@7222	296	MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT),
goetz@7222	297	MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT),
goetz@7222	298
goetz@7222	299	MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT),
aoqi@0	300
aoqi@0	301	MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
aoqi@0	302	MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
aoqi@0	303	MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
aoqi@0	304
aoqi@0	305	// condition register logic instructions
aoqi@0	306	CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
aoqi@0	307	CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
aoqi@0	308	CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
aoqi@0	309	CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
aoqi@0	310	CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
aoqi@0	311	CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
aoqi@0	312	CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
aoqi@0	313	CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
aoqi@0	314
aoqi@0	315	BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
aoqi@0	316	BXX_OPCODE = (18u << OPCODE_SHIFT),
aoqi@0	317	BCXX_OPCODE = (16u << OPCODE_SHIFT),
aoqi@0	318
aoqi@0	319	// CTR-related opcodes
aoqi@0	320	BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
aoqi@0	321
aoqi@0	322	LWZ_OPCODE = (32u << OPCODE_SHIFT),
aoqi@0	323	LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
aoqi@0	324	LWZU_OPCODE = (33u << OPCODE_SHIFT),
kvn@7132	325	LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
aoqi@0	326
aoqi@0	327	LHA_OPCODE = (42u << OPCODE_SHIFT),
aoqi@0	328	LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
aoqi@0	329	LHAU_OPCODE = (43u << OPCODE_SHIFT),
aoqi@0	330
aoqi@0	331	LHZ_OPCODE = (40u << OPCODE_SHIFT),
aoqi@0	332	LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
aoqi@0	333	LHZU_OPCODE = (41u << OPCODE_SHIFT),
kvn@7132	334	LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
aoqi@0	335
aoqi@0	336	LBZ_OPCODE = (34u << OPCODE_SHIFT),
aoqi@0	337	LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
aoqi@0	338	LBZU_OPCODE = (35u << OPCODE_SHIFT),
aoqi@0	339
aoqi@0	340	STW_OPCODE = (36u << OPCODE_SHIFT),
aoqi@0	341	STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
aoqi@0	342	STWU_OPCODE = (37u << OPCODE_SHIFT),
aoqi@0	343	STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
aoqi@0	344
aoqi@0	345	STH_OPCODE = (44u << OPCODE_SHIFT),
aoqi@0	346	STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
aoqi@0	347	STHU_OPCODE = (45u << OPCODE_SHIFT),
aoqi@0	348
aoqi@0	349	STB_OPCODE = (38u << OPCODE_SHIFT),
aoqi@0	350	STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
aoqi@0	351	STBU_OPCODE = (39u << OPCODE_SHIFT),
aoqi@0	352
aoqi@0	353	EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
aoqi@0	354	EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
aoqi@0	355	EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
aoqi@0	356
aoqi@0	357	// 32 bit opcode encodings
aoqi@0	358
aoqi@0	359	LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	360	LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
aoqi@0	361
aoqi@0	362	CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
aoqi@0	363
aoqi@0	364	// 64 bit opcode encodings
aoqi@0	365
aoqi@0	366	LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	367	LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	368	LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
aoqi@0	369
aoqi@0	370	STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	371	STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
aoqi@0	372	STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
aoqi@0	373	STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
aoqi@0	374
aoqi@0	375	RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
aoqi@0	376	RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
aoqi@0	377	RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
aoqi@0	378	RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
aoqi@0	379
aoqi@0	380	SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
aoqi@0	381
aoqi@0	382	SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
aoqi@0	383	SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
aoqi@0	384	SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
aoqi@0	385
aoqi@0	386	MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
aoqi@0	387	MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
aoqi@0	388	MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
aoqi@0	389	DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
aoqi@0	390
aoqi@0	391	CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
aoqi@0	392	NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
aoqi@0	393	NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
aoqi@0	394
aoqi@0	395
aoqi@0	396	// opcodes only used for floating arithmetic
aoqi@0	397	FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
aoqi@0	398	FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
aoqi@0	399	FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
aoqi@0	400	FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
aoqi@0	401	FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
aoqi@0	402	FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
aoqi@0	403	// These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
aoqi@0	404	// on Power7. Do not use.
aoqi@0	405	// MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
aoqi@0	406	// MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
aoqi@0	407	CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
aoqi@0	408	POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
aoqi@0	409	POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
aoqi@0	410	POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
aoqi@0	411	FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
aoqi@0	412	FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
aoqi@0	413	FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
aoqi@0	414	FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
aoqi@0	415	FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
aoqi@0	416	FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
aoqi@0	417	FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
aoqi@0	418
aoqi@0	419	// PPC64-internal FPU conversion opcodes
aoqi@0	420	FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
aoqi@0	421	FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
aoqi@0	422	FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
aoqi@0	423	FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
aoqi@0	424	FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
aoqi@0	425	FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
aoqi@0	426	FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
aoqi@0	427
aoqi@0	428	// WARNING: using fmadd results in a non-compliant vm. Some floating
aoqi@0	429	// point tck tests will fail.
aoqi@0	430	FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
aoqi@0	431	DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
aoqi@0	432	FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
aoqi@0	433	DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
aoqi@0	434	FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
aoqi@0	435	DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
aoqi@0	436	FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
aoqi@0	437	DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
aoqi@0	438
aoqi@0	439	LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
aoqi@0	440	LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
aoqi@0	441	LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
aoqi@0	442	LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
aoqi@0	443	LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
aoqi@0	444	LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
aoqi@0	445
aoqi@0	446	STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
aoqi@0	447	STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
aoqi@0	448	STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
aoqi@0	449	STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
aoqi@0	450	STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
aoqi@0	451	STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
aoqi@0	452
aoqi@0	453	FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
aoqi@0	454	FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
aoqi@0	455
aoqi@0	456	// Vector instruction support for >= Power6
aoqi@0	457	// Vector Storage Access
aoqi@0	458	LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
aoqi@0	459	LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
aoqi@0	460	LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
aoqi@0	461	LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
aoqi@0	462	LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
aoqi@0	463	STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
aoqi@0	464	STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
aoqi@0	465	STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
aoqi@0	466	STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
aoqi@0	467	STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
aoqi@0	468	LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
aoqi@0	469	LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
aoqi@0	470
aoqi@0	471	// Vector Permute and Formatting
aoqi@0	472	VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
aoqi@0	473	VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
aoqi@0	474	VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
aoqi@0	475	VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
aoqi@0	476	VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
aoqi@0	477	VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
aoqi@0	478	VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
aoqi@0	479	VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
aoqi@0	480	VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
aoqi@0	481	VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
aoqi@0	482	VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
aoqi@0	483	VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
aoqi@0	484	VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
aoqi@0	485	VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
aoqi@0	486	VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
aoqi@0	487
aoqi@0	488	VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
aoqi@0	489	VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
aoqi@0	490	VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
aoqi@0	491	VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
aoqi@0	492	VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
aoqi@0	493	VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
aoqi@0	494
aoqi@0	495	VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
aoqi@0	496	VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
aoqi@0	497	VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
aoqi@0	498	VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
aoqi@0	499	VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
aoqi@0	500	VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
aoqi@0	501
aoqi@0	502	VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
aoqi@0	503	VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
aoqi@0	504
aoqi@0	505	VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
aoqi@0	506	VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
aoqi@0	507	VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
aoqi@0	508	VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
aoqi@0	509	VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
aoqi@0	510
aoqi@0	511	// Vector Integer
aoqi@0	512	VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
aoqi@0	513	VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
aoqi@0	514	VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
aoqi@0	515	VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
aoqi@0	516	VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
aoqi@0	517	VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
aoqi@0	518	VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
aoqi@0	519	VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
aoqi@0	520	VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
aoqi@0	521	VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
aoqi@0	522	VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
aoqi@0	523	VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
aoqi@0	524	VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
aoqi@0	525	VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
aoqi@0	526	VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
aoqi@0	527	VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
aoqi@0	528	VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
aoqi@0	529	VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
aoqi@0	530	VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
aoqi@0	531	VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
aoqi@0	532
aoqi@0	533	VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
aoqi@0	534	VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
aoqi@0	535	VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
aoqi@0	536	VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
aoqi@0	537	VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
aoqi@0	538	VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
aoqi@0	539	VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
aoqi@0	540	VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
aoqi@0	541	VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
aoqi@0	542	VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
aoqi@0	543	VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
aoqi@0	544	VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
aoqi@0	545	VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
aoqi@0	546	VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
aoqi@0	547	VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
aoqi@0	548	VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
aoqi@0	549	VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
aoqi@0	550
aoqi@0	551	VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
aoqi@0	552	VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
aoqi@0	553	VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
aoqi@0	554	VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
aoqi@0	555	VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
aoqi@0	556
aoqi@0	557	VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
aoqi@0	558	VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
aoqi@0	559	VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
aoqi@0	560	VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
aoqi@0	561	VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
aoqi@0	562	VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
aoqi@0	563
aoqi@0	564	VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
aoqi@0	565	VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
aoqi@0	566	VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
aoqi@0	567	VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
aoqi@0	568	VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
aoqi@0	569	VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
aoqi@0	570	VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
aoqi@0	571	VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
aoqi@0	572	VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
aoqi@0	573	VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
aoqi@0	574	VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
aoqi@0	575	VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
aoqi@0	576
aoqi@0	577	VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
aoqi@0	578	VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
aoqi@0	579	VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
aoqi@0	580	VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
aoqi@0	581	VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
aoqi@0	582	VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
aoqi@0	583	VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
aoqi@0	584	VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
aoqi@0	585	VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
aoqi@0	586
aoqi@0	587	VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
aoqi@0	588	VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
aoqi@0	589	VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
aoqi@0	590	VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
aoqi@0	591	VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
simonis@8608	592	VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ),
aoqi@0	593	VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
aoqi@0	594	VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
aoqi@0	595	VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
aoqi@0	596	VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
aoqi@0	597	VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
aoqi@0	598	VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
aoqi@0	599	VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
aoqi@0	600	VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
aoqi@0	601	VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
aoqi@0	602	VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
aoqi@0	603	VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
aoqi@0	604	VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
aoqi@0	605
aoqi@0	606	// Vector Floating-Point
aoqi@0	607	// not implemented yet
aoqi@0	608
aoqi@0	609	// Vector Status and Control
aoqi@0	610	MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
aoqi@0	611	MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
aoqi@0	612
goetz@7222	613	// AES (introduced with Power 8)
goetz@7222	614	VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
goetz@7222	615	VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
goetz@7222	616	VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
goetz@7222	617	VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
goetz@7222	618	VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
goetz@7222	619
goetz@7222	620	// SHA (introduced with Power 8)
goetz@7222	621	VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
goetz@7222	622	VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
goetz@7222	623
goetz@7222	624	// Vector Binary Polynomial Multiplication (introduced with Power 8)
goetz@7222	625	VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
goetz@7222	626	VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
goetz@7222	627	VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
goetz@7222	628	VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
goetz@7222	629
goetz@7222	630	// Vector Permute and Xor (introduced with Power 8)
goetz@7222	631	VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
goetz@7222	632
goetz@7222	633	// Transactional Memory instructions (introduced with Power 8)
goetz@7222	634	TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
goetz@7222	635	TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
goetz@7222	636	TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
goetz@7222	637	TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
goetz@7222	638	TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
goetz@7222	639	TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
goetz@7222	640	TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
goetz@7222	641	TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
goetz@7222	642	TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
goetz@7222	643
aoqi@0	644	// Icache and dcache related instructions
aoqi@0	645	DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
aoqi@0	646	DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
aoqi@0	647	DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
aoqi@0	648	DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
aoqi@0	649
aoqi@0	650	DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
aoqi@0	651	DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
aoqi@0	652	ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
aoqi@0	653
aoqi@0	654	// Instruction synchronization
aoqi@0	655	ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
aoqi@0	656	// Memory barriers
aoqi@0	657	SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
aoqi@0	658	EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
aoqi@0	659
aoqi@0	660	// Trap instructions
aoqi@0	661	TDI_OPCODE = (2u << OPCODE_SHIFT),
aoqi@0	662	TWI_OPCODE = (3u << OPCODE_SHIFT),
aoqi@0	663	TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
aoqi@0	664	TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
aoqi@0	665
aoqi@0	666	// Atomics.
aoqi@0	667	LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
aoqi@0	668	LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
aoqi@0	669	STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
aoqi@0	670	STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
aoqi@0	671
aoqi@0	672	};
aoqi@0	673
aoqi@0	674	// Trap instructions TO bits
aoqi@0	675	enum trap_to_bits {
aoqi@0	676	// single bits
aoqi@0	677	traptoLessThanSigned = 1 << 4, // 0, left end
aoqi@0	678	traptoGreaterThanSigned = 1 << 3,
aoqi@0	679	traptoEqual = 1 << 2,
aoqi@0	680	traptoLessThanUnsigned = 1 << 1,
aoqi@0	681	traptoGreaterThanUnsigned = 1 << 0, // 4, right end
aoqi@0	682
aoqi@0	683	// compound ones
aoqi@0	684	traptoUnconditional = (traptoLessThanSigned |
aoqi@0	685	traptoGreaterThanSigned |
aoqi@0	686	traptoEqual |
aoqi@0	687	traptoLessThanUnsigned |
aoqi@0	688	traptoGreaterThanUnsigned)
aoqi@0	689	};
aoqi@0	690
aoqi@0	691	// Branch hints BH field
aoqi@0	692	enum branch_hint_bh {
aoqi@0	693	// bclr cases:
aoqi@0	694	bhintbhBCLRisReturn = 0,
aoqi@0	695	bhintbhBCLRisNotReturnButSame = 1,
aoqi@0	696	bhintbhBCLRisNotPredictable = 3,
aoqi@0	697
aoqi@0	698	// bcctr cases:
aoqi@0	699	bhintbhBCCTRisNotReturnButSame = 0,
aoqi@0	700	bhintbhBCCTRisNotPredictable = 3
aoqi@0	701	};
aoqi@0	702
aoqi@0	703	// Branch prediction hints AT field
aoqi@0	704	enum branch_hint_at {
aoqi@0	705	bhintatNoHint = 0, // at=00
aoqi@0	706	bhintatIsNotTaken = 2, // at=10
aoqi@0	707	bhintatIsTaken = 3 // at=11
aoqi@0	708	};
aoqi@0	709
aoqi@0	710	// Branch prediction hints
aoqi@0	711	enum branch_hint_concept {
aoqi@0	712	// Use the same encoding as branch_hint_at to simply code.
aoqi@0	713	bhintNoHint = bhintatNoHint,
aoqi@0	714	bhintIsNotTaken = bhintatIsNotTaken,
aoqi@0	715	bhintIsTaken = bhintatIsTaken
aoqi@0	716	};
aoqi@0	717
aoqi@0	718	// Used in BO field of branch instruction.
aoqi@0	719	enum branch_condition {
aoqi@0	720	bcondCRbiIs0 = 4, // bo=001at
aoqi@0	721	bcondCRbiIs1 = 12, // bo=011at
aoqi@0	722	bcondAlways = 20 // bo=10100
aoqi@0	723	};
aoqi@0	724
aoqi@0	725	// Branch condition with combined prediction hints.
aoqi@0	726	enum branch_condition_with_hint {
aoqi@0	727	bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
aoqi@0	728	bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
aoqi@0	729	bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
aoqi@0	730	bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
aoqi@0	731	bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
aoqi@0	732	bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
aoqi@0	733	};
aoqi@0	734
aoqi@0	735	// Elemental Memory Barriers (>=Power 8)
aoqi@0	736	enum Elemental_Membar_mask_bits {
aoqi@0	737	StoreStore = 1 << 0,
aoqi@0	738	StoreLoad = 1 << 1,
aoqi@0	739	LoadStore = 1 << 2,
aoqi@0	740	LoadLoad = 1 << 3
aoqi@0	741	};
aoqi@0	742
aoqi@0	743	// Branch prediction hints.
aoqi@0	744	inline static int add_bhint_to_boint(const int bhint, const int boint) {
aoqi@0	745	switch (boint) {
aoqi@0	746	case bcondCRbiIs0:
aoqi@0	747	case bcondCRbiIs1:
aoqi@0	748	// branch_hint and branch_hint_at have same encodings
aoqi@0	749	assert( (int)bhintNoHint == (int)bhintatNoHint
aoqi@0	750	&& (int)bhintIsNotTaken == (int)bhintatIsNotTaken
aoqi@0	751	&& (int)bhintIsTaken == (int)bhintatIsTaken,
aoqi@0	752	"wrong encodings");
aoqi@0	753	assert((bhint & 0x03) == bhint, "wrong encodings");
aoqi@0	754	return (boint & ~0x03) | bhint;
aoqi@0	755	case bcondAlways:
aoqi@0	756	// no branch_hint
aoqi@0	757	return boint;
aoqi@0	758	default:
aoqi@0	759	ShouldNotReachHere();
aoqi@0	760	return 0;
aoqi@0	761	}
aoqi@0	762	}
aoqi@0	763
aoqi@0	764	// Extract bcond from boint.
aoqi@0	765	inline static int inv_boint_bcond(const int boint) {
aoqi@0	766	int r_bcond = boint & ~0x03;
aoqi@0	767	assert(r_bcond == bcondCRbiIs0 ||
aoqi@0	768	r_bcond == bcondCRbiIs1 ||
aoqi@0	769	r_bcond == bcondAlways,
aoqi@0	770	"bad branch condition");
aoqi@0	771	return r_bcond;
aoqi@0	772	}
aoqi@0	773
aoqi@0	774	// Extract bhint from boint.
aoqi@0	775	inline static int inv_boint_bhint(const int boint) {
aoqi@0	776	int r_bhint = boint & 0x03;
aoqi@0	777	assert(r_bhint == bhintatNoHint ||
aoqi@0	778	r_bhint == bhintatIsNotTaken ||
aoqi@0	779	r_bhint == bhintatIsTaken,
aoqi@0	780	"bad branch hint");
aoqi@0	781	return r_bhint;
aoqi@0	782	}
aoqi@0	783
aoqi@0	784	// Calculate opposite of given bcond.
aoqi@0	785	inline static int opposite_bcond(const int bcond) {
aoqi@0	786	switch (bcond) {
aoqi@0	787	case bcondCRbiIs0:
aoqi@0	788	return bcondCRbiIs1;
aoqi@0	789	case bcondCRbiIs1:
aoqi@0	790	return bcondCRbiIs0;
aoqi@0	791	default:
aoqi@0	792	ShouldNotReachHere();
aoqi@0	793	return 0;
aoqi@0	794	}
aoqi@0	795	}
aoqi@0	796
aoqi@0	797	// Calculate opposite of given bhint.
aoqi@0	798	inline static int opposite_bhint(const int bhint) {
aoqi@0	799	switch (bhint) {
aoqi@0	800	case bhintatNoHint:
aoqi@0	801	return bhintatNoHint;
aoqi@0	802	case bhintatIsNotTaken:
aoqi@0	803	return bhintatIsTaken;
aoqi@0	804	case bhintatIsTaken:
aoqi@0	805	return bhintatIsNotTaken;
aoqi@0	806	default:
aoqi@0	807	ShouldNotReachHere();
aoqi@0	808	return 0;
aoqi@0	809	}
aoqi@0	810	}
aoqi@0	811
aoqi@0	812	// PPC branch instructions
aoqi@0	813	enum ppcops {
aoqi@0	814	b_op = 18,
aoqi@0	815	bc_op = 16,
aoqi@0	816	bcr_op = 19
aoqi@0	817	};
aoqi@0	818
aoqi@0	819	enum Condition {
aoqi@0	820	negative = 0,
aoqi@0	821	less = 0,
aoqi@0	822	positive = 1,
aoqi@0	823	greater = 1,
aoqi@0	824	zero = 2,
aoqi@0	825	equal = 2,
aoqi@0	826	summary_overflow = 3,
aoqi@0	827	};
aoqi@0	828
aoqi@0	829	public:
aoqi@0	830	// Helper functions for groups of instructions
aoqi@0	831
aoqi@0	832	enum Predict { pt = 1, pn = 0 }; // pt = predict taken
aoqi@0	833
aoqi@0	834	// instruction must start at passed address
aoqi@0	835	static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
aoqi@0	836
aoqi@0	837	// instruction must be left-justified in argument
aoqi@0	838	static int instr_len(unsigned long instr) { return BytesPerInstWord; }
aoqi@0	839
aoqi@0	840	// longest instructions
aoqi@0	841	static int instr_maxlen() { return BytesPerInstWord; }
aoqi@0	842
aoqi@0	843	// Test if x is within signed immediate range for nbits.
aoqi@0	844	static bool is_simm(int x, unsigned int nbits) {
aoqi@0	845	assert(0 < nbits && nbits < 32, "out of bounds");
aoqi@0	846	const int min = -( ((int)1) << nbits-1 );
aoqi@0	847	const int maxplus1 = ( ((int)1) << nbits-1 );
aoqi@0	848	return min <= x && x < maxplus1;
aoqi@0	849	}
aoqi@0	850
aoqi@0	851	static bool is_simm(jlong x, unsigned int nbits) {
aoqi@0	852	assert(0 < nbits && nbits < 64, "out of bounds");
aoqi@0	853	const jlong min = -( ((jlong)1) << nbits-1 );
aoqi@0	854	const jlong maxplus1 = ( ((jlong)1) << nbits-1 );
aoqi@0	855	return min <= x && x < maxplus1;
aoqi@0	856	}
aoqi@0	857
aoqi@0	858	// Test if x is within unsigned immediate range for nbits
aoqi@0	859	static bool is_uimm(int x, unsigned int nbits) {
aoqi@0	860	assert(0 < nbits && nbits < 32, "out of bounds");
aoqi@0	861	const int maxplus1 = ( ((int)1) << nbits );
aoqi@0	862	return 0 <= x && x < maxplus1;
aoqi@0	863	}
aoqi@0	864
aoqi@0	865	static bool is_uimm(jlong x, unsigned int nbits) {
aoqi@0	866	assert(0 < nbits && nbits < 64, "out of bounds");
aoqi@0	867	const jlong maxplus1 = ( ((jlong)1) << nbits );
aoqi@0	868	return 0 <= x && x < maxplus1;
aoqi@0	869	}
aoqi@0	870
aoqi@0	871	protected:
aoqi@0	872	// helpers
aoqi@0	873
aoqi@0	874	// X is supposed to fit in a field "nbits" wide
aoqi@0	875	// and be sign-extended. Check the range.
aoqi@0	876	static void assert_signed_range(intptr_t x, int nbits) {
aoqi@0	877	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
aoqi@0	878	"value out of range");
aoqi@0	879	}
aoqi@0	880
aoqi@0	881	static void assert_signed_word_disp_range(intptr_t x, int nbits) {
aoqi@0	882	assert((x & 3) == 0, "not word aligned");
aoqi@0	883	assert_signed_range(x, nbits + 2);
aoqi@0	884	}
aoqi@0	885
aoqi@0	886	static void assert_unsigned_const(int x, int nbits) {
aoqi@0	887	assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
aoqi@0	888	}
aoqi@0	889
aoqi@0	890	static int fmask(juint hi_bit, juint lo_bit) {
aoqi@0	891	assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
aoqi@0	892	return (1 << ( hi_bit-lo_bit + 1 )) - 1;
aoqi@0	893	}
aoqi@0	894
aoqi@0	895	// inverse of u_field
aoqi@0	896	static int inv_u_field(int x, int hi_bit, int lo_bit) {
aoqi@0	897	juint r = juint(x) >> lo_bit;
aoqi@0	898	r &= fmask(hi_bit, lo_bit);
aoqi@0	899	return int(r);
aoqi@0	900	}
aoqi@0	901
aoqi@0	902	// signed version: extract from field and sign-extend
aoqi@0	903	static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
aoqi@0	904	x = x << (31-hi_bit);
aoqi@0	905	x = x >> (31-hi_bit+lo_bit);
aoqi@0	906	return x;
aoqi@0	907	}
aoqi@0	908
aoqi@0	909	static int u_field(int x, int hi_bit, int lo_bit) {
aoqi@0	910	assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
aoqi@0	911	int r = x << lo_bit;
aoqi@0	912	assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
aoqi@0	913	return r;
aoqi@0	914	}
aoqi@0	915
aoqi@0	916	// Same as u_field for signed values
aoqi@0	917	static int s_field(int x, int hi_bit, int lo_bit) {
aoqi@0	918	int nbits = hi_bit - lo_bit + 1;
aoqi@0	919	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
aoqi@0	920	"value out of range");
aoqi@0	921	x &= fmask(hi_bit, lo_bit);
aoqi@0	922	int r = x << lo_bit;
aoqi@0	923	return r;
aoqi@0	924	}
aoqi@0	925
aoqi@0	926	// inv_op for ppc instructions
aoqi@0	927	static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
aoqi@0	928
aoqi@0	929	// Determine target address from li, bd field of branch instruction.
aoqi@0	930	static intptr_t inv_li_field(int x) {
aoqi@0	931	intptr_t r = inv_s_field_ppc(x, 25, 2);
aoqi@0	932	r = (r << 2);
aoqi@0	933	return r;
aoqi@0	934	}
aoqi@0	935	static intptr_t inv_bd_field(int x, intptr_t pos) {
aoqi@0	936	intptr_t r = inv_s_field_ppc(x, 15, 2);
aoqi@0	937	r = (r << 2) + pos;
aoqi@0	938	return r;
aoqi@0	939	}
aoqi@0	940
aoqi@0	941	#define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
aoqi@0	942	#define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
aoqi@0	943	// Extract instruction fields from instruction words.
aoqi@0	944	public:
aoqi@0	945	static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
aoqi@0	946	static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
aoqi@0	947	static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
aoqi@0	948	static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
aoqi@0	949	static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
aoqi@0	950	// Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
aoqi@0	951	// Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
aoqi@0	952	static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
aoqi@0	953	static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
aoqi@0	954	static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
aoqi@0	955	static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
aoqi@0	956	static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
aoqi@0	957	static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
aoqi@0	958	static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
aoqi@0	959
aoqi@0	960	#define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
aoqi@0	961	#define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
aoqi@0	962
aoqi@0	963	// instruction fields
aoqi@0	964	static int aa( int x) { return opp_u_field(x, 30, 30); }
aoqi@0	965	static int ba( int x) { return opp_u_field(x, 15, 11); }
aoqi@0	966	static int bb( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	967	static int bc( int x) { return opp_u_field(x, 25, 21); }
aoqi@0	968	static int bd( int x) { return opp_s_field(x, 29, 16); }
aoqi@0	969	static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
aoqi@0	970	static int bf( int x) { return opp_u_field(x, 8, 6); }
aoqi@0	971	static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
aoqi@0	972	static int bfa( int x) { return opp_u_field(x, 13, 11); }
aoqi@0	973	static int bh( int x) { return opp_u_field(x, 20, 19); }
aoqi@0	974	static int bi( int x) { return opp_u_field(x, 15, 11); }
aoqi@0	975	static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
aoqi@0	976	static int bo( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	977	static int bt( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	978	static int d1( int x) { return opp_s_field(x, 31, 16); }
aoqi@0	979	static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
aoqi@0	980	static int eh( int x) { return opp_u_field(x, 31, 31); }
aoqi@0	981	static int flm( int x) { return opp_u_field(x, 14, 7); }
aoqi@0	982	static int fra( FloatRegister r) { return fra(r->encoding());}
aoqi@0	983	static int frb( FloatRegister r) { return frb(r->encoding());}
aoqi@0	984	static int frc( FloatRegister r) { return frc(r->encoding());}
aoqi@0	985	static int frs( FloatRegister r) { return frs(r->encoding());}
aoqi@0	986	static int frt( FloatRegister r) { return frt(r->encoding());}
aoqi@0	987	static int fra( int x) { return opp_u_field(x, 15, 11); }
aoqi@0	988	static int frb( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	989	static int frc( int x) { return opp_u_field(x, 25, 21); }
aoqi@0	990	static int frs( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	991	static int frt( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	992	static int fxm( int x) { return opp_u_field(x, 19, 12); }
aoqi@0	993	static int l10( int x) { return opp_u_field(x, 10, 10); }
aoqi@0	994	static int l15( int x) { return opp_u_field(x, 15, 15); }
aoqi@0	995	static int l910( int x) { return opp_u_field(x, 10, 9); }
aoqi@0	996	static int e1215( int x) { return opp_u_field(x, 15, 12); }
aoqi@0	997	static int lev( int x) { return opp_u_field(x, 26, 20); }
aoqi@0	998	static int li( int x) { return opp_s_field(x, 29, 6); }
aoqi@0	999	static int lk( int x) { return opp_u_field(x, 31, 31); }
aoqi@0	1000	static int mb2125( int x) { return opp_u_field(x, 25, 21); }
aoqi@0	1001	static int me2630( int x) { return opp_u_field(x, 30, 26); }
aoqi@0	1002	static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
aoqi@0	1003	static int me2126( int x) { return mb2126(x); }
aoqi@0	1004	static int nb( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	1005	//static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
aoqi@0	1006	static int oe( int x) { return opp_u_field(x, 21, 21); }
aoqi@0	1007	static int ra( Register r) { return ra(r->encoding()); }
aoqi@0	1008	static int ra( int x) { return opp_u_field(x, 15, 11); }
aoqi@0	1009	static int rb( Register r) { return rb(r->encoding()); }
aoqi@0	1010	static int rb( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	1011	static int rc( int x) { return opp_u_field(x, 31, 31); }
aoqi@0	1012	static int rs( Register r) { return rs(r->encoding()); }
aoqi@0	1013	static int rs( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	1014	// we don't want to use R0 in memory accesses, because it has value `0' then
aoqi@0	1015	static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
aoqi@0	1016	static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
aoqi@0	1017
aoqi@0	1018	// register r is target
aoqi@0	1019	static int rt( Register r) { return rs(r); }
aoqi@0	1020	static int rt( int x) { return rs(x); }
aoqi@0	1021	static int rta( Register r) { return ra(r); }
aoqi@0	1022	static int rta0mem( Register r) { rta(r); return ra0mem(r); }
aoqi@0	1023
aoqi@0	1024	static int sh1620( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	1025	static int sh30( int x) { return opp_u_field(x, 30, 30); }
aoqi@0	1026	static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
aoqi@0	1027	static int si( int x) { return opp_s_field(x, 31, 16); }
aoqi@0	1028	static int spr( int x) { return opp_u_field(x, 20, 11); }
aoqi@0	1029	static int sr( int x) { return opp_u_field(x, 15, 12); }
aoqi@0	1030	static int tbr( int x) { return opp_u_field(x, 20, 11); }
aoqi@0	1031	static int th( int x) { return opp_u_field(x, 10, 7); }
aoqi@0	1032	static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
aoqi@0	1033	static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
aoqi@0	1034	static int to( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	1035	static int u( int x) { return opp_u_field(x, 19, 16); }
aoqi@0	1036	static int ui( int x) { return opp_u_field(x, 31, 16); }
aoqi@0	1037
aoqi@0	1038	// Support vector instructions for >= Power6.
aoqi@0	1039	static int vra( int x) { return opp_u_field(x, 15, 11); }
aoqi@0	1040	static int vrb( int x) { return opp_u_field(x, 20, 16); }
aoqi@0	1041	static int vrc( int x) { return opp_u_field(x, 25, 21); }
aoqi@0	1042	static int vrs( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	1043	static int vrt( int x) { return opp_u_field(x, 10, 6); }
aoqi@0	1044
aoqi@0	1045	static int vra( VectorRegister r) { return vra(r->encoding());}
aoqi@0	1046	static int vrb( VectorRegister r) { return vrb(r->encoding());}
aoqi@0	1047	static int vrc( VectorRegister r) { return vrc(r->encoding());}
aoqi@0	1048	static int vrs( VectorRegister r) { return vrs(r->encoding());}
aoqi@0	1049	static int vrt( VectorRegister r) { return vrt(r->encoding());}
aoqi@0	1050
aoqi@0	1051	static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
aoqi@0	1052	static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
aoqi@0	1053	static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
aoqi@0	1054	static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
aoqi@0	1055
aoqi@0	1056	//static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
aoqi@0	1057	//static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
aoqi@0	1058	//static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
aoqi@0	1059	//static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
aoqi@0	1060	//static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
aoqi@0	1061	//static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
aoqi@0	1062	//static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
aoqi@0	1063
aoqi@0	1064	protected:
aoqi@0	1065	// Compute relative address for branch.
aoqi@0	1066	static intptr_t disp(intptr_t x, intptr_t off) {
aoqi@0	1067	int xx = x - off;
aoqi@0	1068	xx = xx >> 2;
aoqi@0	1069	return xx;
aoqi@0	1070	}
aoqi@0	1071
aoqi@0	1072	public:
aoqi@0	1073	// signed immediate, in low bits, nbits long
aoqi@0	1074	static int simm(int x, int nbits) {
aoqi@0	1075	assert_signed_range(x, nbits);
aoqi@0	1076	return x & ((1 << nbits) - 1);
aoqi@0	1077	}
aoqi@0	1078
aoqi@0	1079	// unsigned immediate, in low bits, nbits long
aoqi@0	1080	static int uimm(int x, int nbits) {
aoqi@0	1081	assert_unsigned_const(x, nbits);
aoqi@0	1082	return x & ((1 << nbits) - 1);
aoqi@0	1083	}
aoqi@0	1084
aoqi@0	1085	static void set_imm(int* instr, short s) {
aoqi@0	1086	// imm is always in the lower 16 bits of the instruction,
aoqi@0	1087	// so this is endian-neutral. Same for the get_imm below.
aoqi@0	1088	uint32_t w = *(uint32_t *)instr;
aoqi@0	1089	*instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
aoqi@0	1090	}
aoqi@0	1091
aoqi@0	1092	static int get_imm(address a, int instruction_number) {
aoqi@0	1093	return (short)((int *)a)[instruction_number];
aoqi@0	1094	}
aoqi@0	1095
aoqi@0	1096	static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
aoqi@0	1097	static inline int lo16_unsigned(int x) { return x & 0xffff; }
aoqi@0	1098
aoqi@0	1099	protected:
aoqi@0	1100
aoqi@0	1101	// Extract the top 32 bits in a 64 bit word.
aoqi@0	1102	static int32_t hi32(int64_t x) {
aoqi@0	1103	int32_t r = int32_t((uint64_t)x >> 32);
aoqi@0	1104	return r;
aoqi@0	1105	}
aoqi@0	1106
aoqi@0	1107	public:
aoqi@0	1108
aoqi@0	1109	static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
aoqi@0	1110	return ((addr + (a - 1)) & ~(a - 1));
aoqi@0	1111	}
aoqi@0	1112
aoqi@0	1113	static inline bool is_aligned(unsigned int addr, unsigned int a) {
aoqi@0	1114	return (0 == addr % a);
aoqi@0	1115	}
aoqi@0	1116
aoqi@0	1117	void flush() {
aoqi@0	1118	AbstractAssembler::flush();
aoqi@0	1119	}
aoqi@0	1120
aoqi@0	1121	inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
aoqi@0	1122	inline void emit_data(int);
aoqi@0	1123	inline void emit_data(int, RelocationHolder const&);
aoqi@0	1124	inline void emit_data(int, relocInfo::relocType rtype);
aoqi@0	1125
aoqi@0	1126	// Emit an address.
aoqi@0	1127	inline address emit_addr(const address addr = NULL);
aoqi@0	1128
aoqi@0	1129	#if !defined(ABI_ELFv2)
aoqi@0	1130	// Emit a function descriptor with the specified entry point, TOC,
aoqi@0	1131	// and ENV. If the entry point is NULL, the descriptor will point
aoqi@0	1132	// just past the descriptor.
aoqi@0	1133	// Use values from friend functions as defaults.
aoqi@0	1134	inline address emit_fd(address entry = NULL,
aoqi@0	1135	address toc = (address) FunctionDescriptor::friend_toc,
aoqi@0	1136	address env = (address) FunctionDescriptor::friend_env);
aoqi@0	1137	#endif
aoqi@0	1138
aoqi@0	1139	/////////////////////////////////////////////////////////////////////////////////////
aoqi@0	1140	// PPC instructions
aoqi@0	1141	/////////////////////////////////////////////////////////////////////////////////////
aoqi@0	1142
aoqi@0	1143	// Memory instructions use r0 as hard coded 0, e.g. to simulate loading
aoqi@0	1144	// immediates. The normal instruction encoders enforce that r0 is not
aoqi@0	1145	// passed to them. Use either extended mnemonics encoders or the special ra0
aoqi@0	1146	// versions.
aoqi@0	1147
aoqi@0	1148	// Issue an illegal instruction.
aoqi@0	1149	inline void illtrap();
aoqi@0	1150	static inline bool is_illtrap(int x);
aoqi@0	1151
aoqi@0	1152	// PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
aoqi@0	1153	inline void addi( Register d, Register a, int si16);
aoqi@0	1154	inline void addis(Register d, Register a, int si16);
aoqi@0	1155	private:
aoqi@0	1156	inline void addi_r0ok( Register d, Register a, int si16);
aoqi@0	1157	inline void addis_r0ok(Register d, Register a, int si16);
aoqi@0	1158	public:
aoqi@0	1159	inline void addic_( Register d, Register a, int si16);
aoqi@0	1160	inline void subfic( Register d, Register a, int si16);
aoqi@0	1161	inline void add( Register d, Register a, Register b);
aoqi@0	1162	inline void add_( Register d, Register a, Register b);
aoqi@0	1163	inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
aoqi@0	1164	inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
aoqi@0	1165	inline void subf_( Register d, Register a, Register b);
aoqi@0	1166	inline void addc( Register d, Register a, Register b);
aoqi@0	1167	inline void addc_( Register d, Register a, Register b);
aoqi@0	1168	inline void subfc( Register d, Register a, Register b);
aoqi@0	1169	inline void subfc_( Register d, Register a, Register b);
aoqi@0	1170	inline void adde( Register d, Register a, Register b);
aoqi@0	1171	inline void adde_( Register d, Register a, Register b);
aoqi@0	1172	inline void subfe( Register d, Register a, Register b);
aoqi@0	1173	inline void subfe_( Register d, Register a, Register b);
aoqi@0	1174	inline void neg( Register d, Register a);
aoqi@0	1175	inline void neg_( Register d, Register a);
aoqi@0	1176	inline void mulli( Register d, Register a, int si16);
aoqi@0	1177	inline void mulld( Register d, Register a, Register b);
aoqi@0	1178	inline void mulld_( Register d, Register a, Register b);
aoqi@0	1179	inline void mullw( Register d, Register a, Register b);
aoqi@0	1180	inline void mullw_( Register d, Register a, Register b);
aoqi@0	1181	inline void mulhw( Register d, Register a, Register b);
aoqi@0	1182	inline void mulhw_( Register d, Register a, Register b);
aoqi@0	1183	inline void mulhd( Register d, Register a, Register b);
aoqi@0	1184	inline void mulhd_( Register d, Register a, Register b);
aoqi@0	1185	inline void mulhdu( Register d, Register a, Register b);
aoqi@0	1186	inline void mulhdu_(Register d, Register a, Register b);
aoqi@0	1187	inline void divd( Register d, Register a, Register b);
aoqi@0	1188	inline void divd_( Register d, Register a, Register b);
aoqi@0	1189	inline void divw( Register d, Register a, Register b);
aoqi@0	1190	inline void divw_( Register d, Register a, Register b);
aoqi@0	1191
aoqi@0	1192	// extended mnemonics
aoqi@0	1193	inline void li( Register d, int si16);
aoqi@0	1194	inline void lis( Register d, int si16);
aoqi@0	1195	inline void addir(Register d, int si16, Register a);
aoqi@0	1196
aoqi@0	1197	static bool is_addi(int x) {
aoqi@0	1198	return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
aoqi@0	1199	}
aoqi@0	1200	static bool is_addis(int x) {
aoqi@0	1201	return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
aoqi@0	1202	}
aoqi@0	1203	static bool is_bxx(int x) {
aoqi@0	1204	return BXX_OPCODE == (x & BXX_OPCODE_MASK);
aoqi@0	1205	}
aoqi@0	1206	static bool is_b(int x) {
aoqi@0	1207	return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
aoqi@0	1208	}
aoqi@0	1209	static bool is_bl(int x) {
aoqi@0	1210	return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
aoqi@0	1211	}
aoqi@0	1212	static bool is_bcxx(int x) {
aoqi@0	1213	return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
aoqi@0	1214	}
aoqi@0	1215	static bool is_bxx_or_bcxx(int x) {
aoqi@0	1216	return is_bxx(x) || is_bcxx(x);
aoqi@0	1217	}
aoqi@0	1218	static bool is_bctrl(int x) {
aoqi@0	1219	return x == 0x4e800421;
aoqi@0	1220	}
aoqi@0	1221	static bool is_bctr(int x) {
aoqi@0	1222	return x == 0x4e800420;
aoqi@0	1223	}
aoqi@0	1224	static bool is_bclr(int x) {
aoqi@0	1225	return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
aoqi@0	1226	}
aoqi@0	1227	static bool is_li(int x) {
aoqi@0	1228	return is_addi(x) && inv_ra_field(x)==0;
aoqi@0	1229	}
aoqi@0	1230	static bool is_lis(int x) {
aoqi@0	1231	return is_addis(x) && inv_ra_field(x)==0;
aoqi@0	1232	}
aoqi@0	1233	static bool is_mtctr(int x) {
aoqi@0	1234	return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
aoqi@0	1235	}
aoqi@0	1236	static bool is_ld(int x) {
aoqi@0	1237	return LD_OPCODE == (x & LD_OPCODE_MASK);
aoqi@0	1238	}
aoqi@0	1239	static bool is_std(int x) {
aoqi@0	1240	return STD_OPCODE == (x & STD_OPCODE_MASK);
aoqi@0	1241	}
aoqi@0	1242	static bool is_stdu(int x) {
aoqi@0	1243	return STDU_OPCODE == (x & STDU_OPCODE_MASK);
aoqi@0	1244	}
aoqi@0	1245	static bool is_stdx(int x) {
aoqi@0	1246	return STDX_OPCODE == (x & STDX_OPCODE_MASK);
aoqi@0	1247	}
aoqi@0	1248	static bool is_stdux(int x) {
aoqi@0	1249	return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
aoqi@0	1250	}
aoqi@0	1251	static bool is_stwx(int x) {
aoqi@0	1252	return STWX_OPCODE == (x & STWX_OPCODE_MASK);
aoqi@0	1253	}
aoqi@0	1254	static bool is_stwux(int x) {
aoqi@0	1255	return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
aoqi@0	1256	}
aoqi@0	1257	static bool is_stw(int x) {
aoqi@0	1258	return STW_OPCODE == (x & STW_OPCODE_MASK);
aoqi@0	1259	}
aoqi@0	1260	static bool is_stwu(int x) {
aoqi@0	1261	return STWU_OPCODE == (x & STWU_OPCODE_MASK);
aoqi@0	1262	}
aoqi@0	1263	static bool is_ori(int x) {
aoqi@0	1264	return ORI_OPCODE == (x & ORI_OPCODE_MASK);
aoqi@0	1265	};
aoqi@0	1266	static bool is_oris(int x) {
aoqi@0	1267	return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
aoqi@0	1268	};
aoqi@0	1269	static bool is_rldicr(int x) {
aoqi@0	1270	return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
aoqi@0	1271	};
aoqi@0	1272	static bool is_nop(int x) {
aoqi@0	1273	return x == 0x60000000;
aoqi@0	1274	}
aoqi@0	1275	// endgroup opcode for Power6
aoqi@0	1276	static bool is_endgroup(int x) {
aoqi@0	1277	return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
aoqi@0	1278	}
aoqi@0	1279
aoqi@0	1280
aoqi@0	1281	private:
aoqi@0	1282	// PPC 1, section 3.3.9, Fixed-Point Compare Instructions
aoqi@0	1283	inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
aoqi@0	1284	inline void cmp( ConditionRegister bf, int l, Register a, Register b);
aoqi@0	1285	inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
aoqi@0	1286	inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
aoqi@0	1287
aoqi@0	1288	public:
aoqi@0	1289	// extended mnemonics of Compare Instructions
aoqi@0	1290	inline void cmpwi( ConditionRegister crx, Register a, int si16);
aoqi@0	1291	inline void cmpdi( ConditionRegister crx, Register a, int si16);
aoqi@0	1292	inline void cmpw( ConditionRegister crx, Register a, Register b);
aoqi@0	1293	inline void cmpd( ConditionRegister crx, Register a, Register b);
aoqi@0	1294	inline void cmplwi(ConditionRegister crx, Register a, int ui16);
aoqi@0	1295	inline void cmpldi(ConditionRegister crx, Register a, int ui16);
aoqi@0	1296	inline void cmplw( ConditionRegister crx, Register a, Register b);
aoqi@0	1297	inline void cmpld( ConditionRegister crx, Register a, Register b);
aoqi@0	1298
aoqi@0	1299	inline void isel( Register d, Register a, Register b, int bc);
aoqi@0	1300	// Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
aoqi@0	1301	inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
aoqi@0	1302	// Set d = 0 if (cr.cc) equals 1, otherwise b.
aoqi@0	1303	inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
aoqi@0	1304
aoqi@0	1305	// PPC 1, section 3.3.11, Fixed-Point Logical Instructions
aoqi@0	1306	void andi( Register a, Register s, int ui16); // optimized version
aoqi@0	1307	inline void andi_( Register a, Register s, int ui16);
aoqi@0	1308	inline void andis_( Register a, Register s, int ui16);
aoqi@0	1309	inline void ori( Register a, Register s, int ui16);
aoqi@0	1310	inline void oris( Register a, Register s, int ui16);
aoqi@0	1311	inline void xori( Register a, Register s, int ui16);
aoqi@0	1312	inline void xoris( Register a, Register s, int ui16);
aoqi@0	1313	inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
aoqi@0	1314	inline void and_( Register a, Register s, Register b);
aoqi@0	1315	// Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
aoqi@0	1316	// SMT-priority change instruction (see SMT instructions below).
aoqi@0	1317	inline void or_unchecked(Register a, Register s, Register b);
aoqi@0	1318	inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
aoqi@0	1319	inline void or_( Register a, Register s, Register b);
aoqi@0	1320	inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
aoqi@0	1321	inline void xor_( Register a, Register s, Register b);
aoqi@0	1322	inline void nand( Register a, Register s, Register b);
aoqi@0	1323	inline void nand_( Register a, Register s, Register b);
aoqi@0	1324	inline void nor( Register a, Register s, Register b);
aoqi@0	1325	inline void nor_( Register a, Register s, Register b);
aoqi@0	1326	inline void andc( Register a, Register s, Register b);
aoqi@0	1327	inline void andc_( Register a, Register s, Register b);
aoqi@0	1328	inline void orc( Register a, Register s, Register b);
aoqi@0	1329	inline void orc_( Register a, Register s, Register b);
aoqi@0	1330	inline void extsb( Register a, Register s);
aoqi@0	1331	inline void extsh( Register a, Register s);
aoqi@0	1332	inline void extsw( Register a, Register s);
aoqi@0	1333
aoqi@0	1334	// extended mnemonics
aoqi@0	1335	inline void nop();
aoqi@0	1336	// NOP for FP and BR units (different versions to allow them to be in one group)
aoqi@0	1337	inline void fpnop0();
aoqi@0	1338	inline void fpnop1();
aoqi@0	1339	inline void brnop0();
aoqi@0	1340	inline void brnop1();
aoqi@0	1341	inline void brnop2();
aoqi@0	1342
aoqi@0	1343	inline void mr( Register d, Register s);
aoqi@0	1344	inline void ori_opt( Register d, int ui16);
aoqi@0	1345	inline void oris_opt(Register d, int ui16);
aoqi@0	1346
aoqi@0	1347	// endgroup opcode for Power6
aoqi@0	1348	inline void endgroup();
aoqi@0	1349
aoqi@0	1350	// count instructions
aoqi@0	1351	inline void cntlzw( Register a, Register s);
aoqi@0	1352	inline void cntlzw_( Register a, Register s);
aoqi@0	1353	inline void cntlzd( Register a, Register s);
aoqi@0	1354	inline void cntlzd_( Register a, Register s);
aoqi@0	1355
aoqi@0	1356	// PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
aoqi@0	1357	inline void sld( Register a, Register s, Register b);
aoqi@0	1358	inline void sld_( Register a, Register s, Register b);
aoqi@0	1359	inline void slw( Register a, Register s, Register b);
aoqi@0	1360	inline void slw_( Register a, Register s, Register b);
aoqi@0	1361	inline void srd( Register a, Register s, Register b);
aoqi@0	1362	inline void srd_( Register a, Register s, Register b);
aoqi@0	1363	inline void srw( Register a, Register s, Register b);
aoqi@0	1364	inline void srw_( Register a, Register s, Register b);
aoqi@0	1365	inline void srad( Register a, Register s, Register b);
aoqi@0	1366	inline void srad_( Register a, Register s, Register b);
aoqi@0	1367	inline void sraw( Register a, Register s, Register b);
aoqi@0	1368	inline void sraw_( Register a, Register s, Register b);
aoqi@0	1369	inline void sradi( Register a, Register s, int sh6);
aoqi@0	1370	inline void sradi_( Register a, Register s, int sh6);
aoqi@0	1371	inline void srawi( Register a, Register s, int sh5);
aoqi@0	1372	inline void srawi_( Register a, Register s, int sh5);
aoqi@0	1373
aoqi@0	1374	// extended mnemonics for Shift Instructions
aoqi@0	1375	inline void sldi( Register a, Register s, int sh6);
aoqi@0	1376	inline void sldi_( Register a, Register s, int sh6);
aoqi@0	1377	inline void slwi( Register a, Register s, int sh5);
aoqi@0	1378	inline void slwi_( Register a, Register s, int sh5);
aoqi@0	1379	inline void srdi( Register a, Register s, int sh6);
aoqi@0	1380	inline void srdi_( Register a, Register s, int sh6);
aoqi@0	1381	inline void srwi( Register a, Register s, int sh5);
aoqi@0	1382	inline void srwi_( Register a, Register s, int sh5);
aoqi@0	1383
aoqi@0	1384	inline void clrrdi( Register a, Register s, int ui6);
aoqi@0	1385	inline void clrrdi_( Register a, Register s, int ui6);
aoqi@0	1386	inline void clrldi( Register a, Register s, int ui6);
aoqi@0	1387	inline void clrldi_( Register a, Register s, int ui6);
aoqi@0	1388	inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
aoqi@0	1389	inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
aoqi@0	1390	inline void extrdi( Register a, Register s, int n, int b);
aoqi@0	1391	// testbit with condition register
aoqi@0	1392	inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
aoqi@0	1393
aoqi@0	1394	// rotate instructions
aoqi@0	1395	inline void rotldi( Register a, Register s, int n);
aoqi@0	1396	inline void rotrdi( Register a, Register s, int n);
aoqi@0	1397	inline void rotlwi( Register a, Register s, int n);
aoqi@0	1398	inline void rotrwi( Register a, Register s, int n);
aoqi@0	1399
aoqi@0	1400	// Rotate Instructions
aoqi@0	1401	inline void rldic( Register a, Register s, int sh6, int mb6);
aoqi@0	1402	inline void rldic_( Register a, Register s, int sh6, int mb6);
aoqi@0	1403	inline void rldicr( Register a, Register s, int sh6, int mb6);
aoqi@0	1404	inline void rldicr_( Register a, Register s, int sh6, int mb6);
aoqi@0	1405	inline void rldicl( Register a, Register s, int sh6, int mb6);
aoqi@0	1406	inline void rldicl_( Register a, Register s, int sh6, int mb6);
aoqi@0	1407	inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
aoqi@0	1408	inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
aoqi@0	1409	inline void rldimi( Register a, Register s, int sh6, int mb6);
aoqi@0	1410	inline void rldimi_( Register a, Register s, int sh6, int mb6);
aoqi@0	1411	inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
aoqi@0	1412	inline void insrdi( Register a, Register s, int n, int b);
aoqi@0	1413	inline void insrwi( Register a, Register s, int n, int b);
aoqi@0	1414
aoqi@0	1415	// PPC 1, section 3.3.2 Fixed-Point Load Instructions
aoqi@0	1416	// 4 bytes
aoqi@0	1417	inline void lwzx( Register d, Register s1, Register s2);
aoqi@0	1418	inline void lwz( Register d, int si16, Register s1);
aoqi@0	1419	inline void lwzu( Register d, int si16, Register s1);
aoqi@0	1420
aoqi@0	1421	// 4 bytes
aoqi@0	1422	inline void lwax( Register d, Register s1, Register s2);
aoqi@0	1423	inline void lwa( Register d, int si16, Register s1);
aoqi@0	1424
kvn@7132	1425	// 4 bytes reversed
kvn@7132	1426	inline void lwbrx( Register d, Register s1, Register s2);
kvn@7132	1427
aoqi@0	1428	// 2 bytes
aoqi@0	1429	inline void lhzx( Register d, Register s1, Register s2);
aoqi@0	1430	inline void lhz( Register d, int si16, Register s1);
aoqi@0	1431	inline void lhzu( Register d, int si16, Register s1);
aoqi@0	1432
kvn@7132	1433	// 2 bytes reversed
kvn@7132	1434	inline void lhbrx( Register d, Register s1, Register s2);
kvn@7132	1435
aoqi@0	1436	// 2 bytes
aoqi@0	1437	inline void lhax( Register d, Register s1, Register s2);
aoqi@0	1438	inline void lha( Register d, int si16, Register s1);
aoqi@0	1439	inline void lhau( Register d, int si16, Register s1);
aoqi@0	1440
aoqi@0	1441	// 1 byte
aoqi@0	1442	inline void lbzx( Register d, Register s1, Register s2);
aoqi@0	1443	inline void lbz( Register d, int si16, Register s1);
aoqi@0	1444	inline void lbzu( Register d, int si16, Register s1);
aoqi@0	1445
aoqi@0	1446	// 8 bytes
aoqi@0	1447	inline void ldx( Register d, Register s1, Register s2);
aoqi@0	1448	inline void ld( Register d, int si16, Register s1);
aoqi@0	1449	inline void ldu( Register d, int si16, Register s1);
aoqi@0	1450
aoqi@0	1451	// PPC 1, section 3.3.3 Fixed-Point Store Instructions
aoqi@0	1452	inline void stwx( Register d, Register s1, Register s2);
aoqi@0	1453	inline void stw( Register d, int si16, Register s1);
aoqi@0	1454	inline void stwu( Register d, int si16, Register s1);
aoqi@0	1455
aoqi@0	1456	inline void sthx( Register d, Register s1, Register s2);
aoqi@0	1457	inline void sth( Register d, int si16, Register s1);
aoqi@0	1458	inline void sthu( Register d, int si16, Register s1);
aoqi@0	1459
aoqi@0	1460	inline void stbx( Register d, Register s1, Register s2);
aoqi@0	1461	inline void stb( Register d, int si16, Register s1);
aoqi@0	1462	inline void stbu( Register d, int si16, Register s1);
aoqi@0	1463
aoqi@0	1464	inline void stdx( Register d, Register s1, Register s2);
aoqi@0	1465	inline void std( Register d, int si16, Register s1);
aoqi@0	1466	inline void stdu( Register d, int si16, Register s1);
aoqi@0	1467	inline void stdux(Register s, Register a, Register b);
aoqi@0	1468
aoqi@0	1469	// PPC 1, section 3.3.13 Move To/From System Register Instructions
aoqi@0	1470	inline void mtlr( Register s1);
aoqi@0	1471	inline void mflr( Register d);
aoqi@0	1472	inline void mtctr(Register s1);
aoqi@0	1473	inline void mfctr(Register d);
aoqi@0	1474	inline void mtcrf(int fxm, Register s);
aoqi@0	1475	inline void mfcr( Register d);
aoqi@0	1476	inline void mcrf( ConditionRegister crd, ConditionRegister cra);
aoqi@0	1477	inline void mtcr( Register s);
aoqi@0	1478
goetz@7222	1479	// Special purpose registers
goetz@7222	1480	// Exception Register
goetz@7222	1481	inline void mtxer(Register s1);
goetz@7222	1482	inline void mfxer(Register d);
goetz@7222	1483	// Vector Register Save Register
goetz@7222	1484	inline void mtvrsave(Register s1);
goetz@7222	1485	inline void mfvrsave(Register d);
goetz@7222	1486	// Timebase
goetz@7222	1487	inline void mftb(Register d);
goetz@7222	1488	// Introduced with Power 8:
goetz@7222	1489	// Data Stream Control Register
goetz@7222	1490	inline void mtdscr(Register s1);
goetz@7222	1491	inline void mfdscr(Register d );
goetz@7222	1492	// Transactional Memory Registers
goetz@7222	1493	inline void mftfhar(Register d);
goetz@7222	1494	inline void mftfiar(Register d);
goetz@7222	1495	inline void mftexasr(Register d);
goetz@7222	1496	inline void mftexasru(Register d);
goetz@7222	1497
aoqi@0	1498	// PPC 1, section 2.4.1 Branch Instructions
aoqi@0	1499	inline void b( address a, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1500	inline void b( Label& L);
aoqi@0	1501	inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1502	inline void bl( Label& L);
aoqi@0	1503	inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1504	inline void bc( int boint, int biint, Label& L);
aoqi@0	1505	inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1506	inline void bcl(int boint, int biint, Label& L);
aoqi@0	1507
aoqi@0	1508	inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1509	inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1510	inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
aoqi@0	1511	relocInfo::relocType rt = relocInfo::none);
aoqi@0	1512	inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
aoqi@0	1513	relocInfo::relocType rt = relocInfo::none);
aoqi@0	1514
aoqi@0	1515	// helper function for b, bcxx
aoqi@0	1516	inline bool is_within_range_of_b(address a, address pc);
aoqi@0	1517	inline bool is_within_range_of_bcxx(address a, address pc);
aoqi@0	1518
aoqi@0	1519	// get the destination of a bxx branch (b, bl, ba, bla)
aoqi@0	1520	static inline address bxx_destination(address baddr);
aoqi@0	1521	static inline address bxx_destination(int instr, address pc);
aoqi@0	1522	static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
aoqi@0	1523
aoqi@0	1524	// extended mnemonics for branch instructions
aoqi@0	1525	inline void blt(ConditionRegister crx, Label& L);
aoqi@0	1526	inline void bgt(ConditionRegister crx, Label& L);
aoqi@0	1527	inline void beq(ConditionRegister crx, Label& L);
aoqi@0	1528	inline void bso(ConditionRegister crx, Label& L);
aoqi@0	1529	inline void bge(ConditionRegister crx, Label& L);
aoqi@0	1530	inline void ble(ConditionRegister crx, Label& L);
aoqi@0	1531	inline void bne(ConditionRegister crx, Label& L);
aoqi@0	1532	inline void bns(ConditionRegister crx, Label& L);
aoqi@0	1533
aoqi@0	1534	// Branch instructions with static prediction hints.
aoqi@0	1535	inline void blt_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1536	inline void bgt_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1537	inline void beq_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1538	inline void bso_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1539	inline void bge_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1540	inline void ble_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1541	inline void bne_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1542	inline void bns_predict_taken( ConditionRegister crx, Label& L);
aoqi@0	1543	inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1544	inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1545	inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1546	inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1547	inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1548	inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1549	inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1550	inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
aoqi@0	1551
aoqi@0	1552	// for use in conjunction with testbitdi:
aoqi@0	1553	inline void btrue( ConditionRegister crx, Label& L);
aoqi@0	1554	inline void bfalse(ConditionRegister crx, Label& L);
aoqi@0	1555
aoqi@0	1556	inline void bltl(ConditionRegister crx, Label& L);
aoqi@0	1557	inline void bgtl(ConditionRegister crx, Label& L);
aoqi@0	1558	inline void beql(ConditionRegister crx, Label& L);
aoqi@0	1559	inline void bsol(ConditionRegister crx, Label& L);
aoqi@0	1560	inline void bgel(ConditionRegister crx, Label& L);
aoqi@0	1561	inline void blel(ConditionRegister crx, Label& L);
aoqi@0	1562	inline void bnel(ConditionRegister crx, Label& L);
aoqi@0	1563	inline void bnsl(ConditionRegister crx, Label& L);
aoqi@0	1564
aoqi@0	1565	// extended mnemonics for Branch Instructions via LR
aoqi@0	1566	// We use `blr' for returns.
aoqi@0	1567	inline void blr(relocInfo::relocType rt = relocInfo::none);
aoqi@0	1568
aoqi@0	1569	// extended mnemonics for Branch Instructions with CTR
aoqi@0	1570	// bdnz means `decrement CTR and jump to L if CTR is not zero'
aoqi@0	1571	inline void bdnz(Label& L);
aoqi@0	1572	// Decrement and branch if result is zero.
aoqi@0	1573	inline void bdz(Label& L);
aoqi@0	1574	// we use `bctr[l]' for jumps/calls in function descriptor glue
aoqi@0	1575	// code, e.g. calls to runtime functions
aoqi@0	1576	inline void bctr( relocInfo::relocType rt = relocInfo::none);
aoqi@0	1577	inline void bctrl(relocInfo::relocType rt = relocInfo::none);
aoqi@0	1578	// conditional jumps/branches via CTR
aoqi@0	1579	inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1580	inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1581	inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1582	inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1583
aoqi@0	1584	// condition register logic instructions
aoqi@0	1585	inline void crand( int d, int s1, int s2);
aoqi@0	1586	inline void crnand(int d, int s1, int s2);
aoqi@0	1587	inline void cror( int d, int s1, int s2);
aoqi@0	1588	inline void crxor( int d, int s1, int s2);
aoqi@0	1589	inline void crnor( int d, int s1, int s2);
aoqi@0	1590	inline void creqv( int d, int s1, int s2);
aoqi@0	1591	inline void crandc(int d, int s1, int s2);
aoqi@0	1592	inline void crorc( int d, int s1, int s2);
aoqi@0	1593
aoqi@0	1594	// icache and dcache related instructions
aoqi@0	1595	inline void icbi( Register s1, Register s2);
aoqi@0	1596	//inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
aoqi@0	1597	inline void dcbz( Register s1, Register s2);
aoqi@0	1598	inline void dcbst( Register s1, Register s2);
aoqi@0	1599	inline void dcbf( Register s1, Register s2);
aoqi@0	1600
aoqi@0	1601	enum ct_cache_specification {
aoqi@0	1602	ct_primary_cache = 0,
aoqi@0	1603	ct_secondary_cache = 2
aoqi@0	1604	};
aoqi@0	1605	// dcache read hint
aoqi@0	1606	inline void dcbt( Register s1, Register s2);
aoqi@0	1607	inline void dcbtct( Register s1, Register s2, int ct);
aoqi@0	1608	inline void dcbtds( Register s1, Register s2, int ds);
aoqi@0	1609	// dcache write hint
aoqi@0	1610	inline void dcbtst( Register s1, Register s2);
aoqi@0	1611	inline void dcbtstct(Register s1, Register s2, int ct);
aoqi@0	1612
aoqi@0	1613	// machine barrier instructions:
aoqi@0	1614	//
aoqi@0	1615	// - sync two-way memory barrier, aka fence
aoqi@0	1616	// - lwsync orders Store|Store,
aoqi@0	1617	// Load|Store,
aoqi@0	1618	// Load|Load,
aoqi@0	1619	// but not Store|Load
aoqi@0	1620	// - eieio orders memory accesses for device memory (only)
aoqi@0	1621	// - isync invalidates speculatively executed instructions
aoqi@0	1622	// From the Power ISA 2.06 documentation:
aoqi@0	1623	// "[...] an isync instruction prevents the execution of
aoqi@0	1624	// instructions following the isync until instructions
aoqi@0	1625	// preceding the isync have completed, [...]"
aoqi@0	1626	// From IBM's AIX assembler reference:
aoqi@0	1627	// "The isync [...] instructions causes the processor to
aoqi@0	1628	// refetch any instructions that might have been fetched
aoqi@0	1629	// prior to the isync instruction. The instruction isync
aoqi@0	1630	// causes the processor to wait for all previous instructions
aoqi@0	1631	// to complete. Then any instructions already fetched are
aoqi@0	1632	// discarded and instruction processing continues in the
aoqi@0	1633	// environment established by the previous instructions."
aoqi@0	1634	//
aoqi@0	1635	// semantic barrier instructions:
aoqi@0	1636	// (as defined in orderAccess.hpp)
aoqi@0	1637	//
aoqi@0	1638	// - release orders Store|Store, (maps to lwsync)
aoqi@0	1639	// Load|Store
aoqi@0	1640	// - acquire orders Load|Store, (maps to lwsync)
aoqi@0	1641	// Load|Load
aoqi@0	1642	// - fence orders Store|Store, (maps to sync)
aoqi@0	1643	// Load|Store,
aoqi@0	1644	// Load|Load,
aoqi@0	1645	// Store|Load
aoqi@0	1646	//
aoqi@0	1647	private:
aoqi@0	1648	inline void sync(int l);
aoqi@0	1649	public:
aoqi@0	1650	inline void sync();
aoqi@0	1651	inline void lwsync();
aoqi@0	1652	inline void ptesync();
aoqi@0	1653	inline void eieio();
aoqi@0	1654	inline void isync();
aoqi@0	1655	inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
aoqi@0	1656
aoqi@0	1657	// atomics
aoqi@0	1658	inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
aoqi@0	1659	inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
aoqi@0	1660	inline bool lxarx_hint_exclusive_access();
aoqi@0	1661	inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
aoqi@0	1662	inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
aoqi@0	1663	inline void stwcx_( Register s, Register a, Register b);
aoqi@0	1664	inline void stdcx_( Register s, Register a, Register b);
aoqi@0	1665
aoqi@0	1666	// Instructions for adjusting thread priority for simultaneous
aoqi@0	1667	// multithreading (SMT) on Power5.
aoqi@0	1668	private:
aoqi@0	1669	inline void smt_prio_very_low();
aoqi@0	1670	inline void smt_prio_medium_high();
aoqi@0	1671	inline void smt_prio_high();
aoqi@0	1672
aoqi@0	1673	public:
aoqi@0	1674	inline void smt_prio_low();
aoqi@0	1675	inline void smt_prio_medium_low();
aoqi@0	1676	inline void smt_prio_medium();
aoqi@0	1677
aoqi@0	1678	// trap instructions
aoqi@0	1679	inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
aoqi@0	1680	// NOT FOR DIRECT USE!!
aoqi@0	1681	protected:
aoqi@0	1682	inline void tdi_unchecked(int tobits, Register a, int si16);
aoqi@0	1683	inline void twi_unchecked(int tobits, Register a, int si16);
aoqi@0	1684	inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
aoqi@0	1685	inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
aoqi@0	1686	inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
aoqi@0	1687	inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
aoqi@0	1688
aoqi@0	1689	static bool is_tdi(int x, int tobits, int ra, int si16) {
aoqi@0	1690	return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
aoqi@0	1691	&& (tobits == inv_to_field(x))
aoqi@0	1692	&& (ra == -1/*any reg*/ || ra == inv_ra_field(x))
aoqi@0	1693	&& (si16 == inv_si_field(x));
aoqi@0	1694	}
aoqi@0	1695
aoqi@0	1696	static bool is_twi(int x, int tobits, int ra, int si16) {
aoqi@0	1697	return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
aoqi@0	1698	&& (tobits == inv_to_field(x))
aoqi@0	1699	&& (ra == -1/*any reg*/ || ra == inv_ra_field(x))
aoqi@0	1700	&& (si16 == inv_si_field(x));
aoqi@0	1701	}
aoqi@0	1702
aoqi@0	1703	static bool is_twi(int x, int tobits, int ra) {
aoqi@0	1704	return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
aoqi@0	1705	&& (tobits == inv_to_field(x))
aoqi@0	1706	&& (ra == -1/*any reg*/ || ra == inv_ra_field(x));
aoqi@0	1707	}
aoqi@0	1708
aoqi@0	1709	static bool is_td(int x, int tobits, int ra, int rb) {
aoqi@0	1710	return (TD_OPCODE == (x & TD_OPCODE_MASK))
aoqi@0	1711	&& (tobits == inv_to_field(x))
aoqi@0	1712	&& (ra == -1/*any reg*/ || ra == inv_ra_field(x))
aoqi@0	1713	&& (rb == -1/*any reg*/ || rb == inv_rb_field(x));
aoqi@0	1714	}
aoqi@0	1715
aoqi@0	1716	static bool is_tw(int x, int tobits, int ra, int rb) {
aoqi@0	1717	return (TW_OPCODE == (x & TW_OPCODE_MASK))
aoqi@0	1718	&& (tobits == inv_to_field(x))
aoqi@0	1719	&& (ra == -1/*any reg*/ || ra == inv_ra_field(x))
aoqi@0	1720	&& (rb == -1/*any reg*/ || rb == inv_rb_field(x));
aoqi@0	1721	}
aoqi@0	1722
aoqi@0	1723	public:
aoqi@0	1724	// PPC floating point instructions
aoqi@0	1725	// PPC 1, section 4.6.2 Floating-Point Load Instructions
aoqi@0	1726	inline void lfs( FloatRegister d, int si16, Register a);
aoqi@0	1727	inline void lfsu( FloatRegister d, int si16, Register a);
aoqi@0	1728	inline void lfsx( FloatRegister d, Register a, Register b);
aoqi@0	1729	inline void lfd( FloatRegister d, int si16, Register a);
aoqi@0	1730	inline void lfdu( FloatRegister d, int si16, Register a);
aoqi@0	1731	inline void lfdx( FloatRegister d, Register a, Register b);
aoqi@0	1732
aoqi@0	1733	// PPC 1, section 4.6.3 Floating-Point Store Instructions
aoqi@0	1734	inline void stfs( FloatRegister s, int si16, Register a);
aoqi@0	1735	inline void stfsu( FloatRegister s, int si16, Register a);
aoqi@0	1736	inline void stfsx( FloatRegister s, Register a, Register b);
aoqi@0	1737	inline void stfd( FloatRegister s, int si16, Register a);
aoqi@0	1738	inline void stfdu( FloatRegister s, int si16, Register a);
aoqi@0	1739	inline void stfdx( FloatRegister s, Register a, Register b);
aoqi@0	1740
aoqi@0	1741	// PPC 1, section 4.6.4 Floating-Point Move Instructions
aoqi@0	1742	inline void fmr( FloatRegister d, FloatRegister b);
aoqi@0	1743	inline void fmr_( FloatRegister d, FloatRegister b);
aoqi@0	1744
aoqi@0	1745	// inline void mffgpr( FloatRegister d, Register b);
aoqi@0	1746	// inline void mftgpr( Register d, FloatRegister b);
aoqi@0	1747	inline void cmpb( Register a, Register s, Register b);
aoqi@0	1748	inline void popcntb(Register a, Register s);
aoqi@0	1749	inline void popcntw(Register a, Register s);
aoqi@0	1750	inline void popcntd(Register a, Register s);
aoqi@0	1751
aoqi@0	1752	inline void fneg( FloatRegister d, FloatRegister b);
aoqi@0	1753	inline void fneg_( FloatRegister d, FloatRegister b);
aoqi@0	1754	inline void fabs( FloatRegister d, FloatRegister b);
aoqi@0	1755	inline void fabs_( FloatRegister d, FloatRegister b);
aoqi@0	1756	inline void fnabs( FloatRegister d, FloatRegister b);
aoqi@0	1757	inline void fnabs_(FloatRegister d, FloatRegister b);
aoqi@0	1758
aoqi@0	1759	// PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
aoqi@0	1760	inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1761	inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1762	inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1763	inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1764	inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1765	inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1766	inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1767	inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1768	inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
aoqi@0	1769	inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
aoqi@0	1770	inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
aoqi@0	1771	inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
aoqi@0	1772	inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1773	inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1774	inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1775	inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
aoqi@0	1776
aoqi@0	1777	// PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
aoqi@0	1778	inline void frsp( FloatRegister d, FloatRegister b);
aoqi@0	1779	inline void fctid( FloatRegister d, FloatRegister b);
aoqi@0	1780	inline void fctidz(FloatRegister d, FloatRegister b);
aoqi@0	1781	inline void fctiw( FloatRegister d, FloatRegister b);
aoqi@0	1782	inline void fctiwz(FloatRegister d, FloatRegister b);
aoqi@0	1783	inline void fcfid( FloatRegister d, FloatRegister b);
aoqi@0	1784	inline void fcfids(FloatRegister d, FloatRegister b);
aoqi@0	1785
aoqi@0	1786	// PPC 1, section 4.6.7 Floating-Point Compare Instructions
aoqi@0	1787	inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
aoqi@0	1788
aoqi@0	1789	inline void fsqrt( FloatRegister d, FloatRegister b);
aoqi@0	1790	inline void fsqrts(FloatRegister d, FloatRegister b);
aoqi@0	1791
aoqi@0	1792	// Vector instructions for >= Power6.
aoqi@0	1793	inline void lvebx( VectorRegister d, Register s1, Register s2);
aoqi@0	1794	inline void lvehx( VectorRegister d, Register s1, Register s2);
aoqi@0	1795	inline void lvewx( VectorRegister d, Register s1, Register s2);
aoqi@0	1796	inline void lvx( VectorRegister d, Register s1, Register s2);
aoqi@0	1797	inline void lvxl( VectorRegister d, Register s1, Register s2);
aoqi@0	1798	inline void stvebx( VectorRegister d, Register s1, Register s2);
aoqi@0	1799	inline void stvehx( VectorRegister d, Register s1, Register s2);
aoqi@0	1800	inline void stvewx( VectorRegister d, Register s1, Register s2);
aoqi@0	1801	inline void stvx( VectorRegister d, Register s1, Register s2);
aoqi@0	1802	inline void stvxl( VectorRegister d, Register s1, Register s2);
aoqi@0	1803	inline void lvsl( VectorRegister d, Register s1, Register s2);
aoqi@0	1804	inline void lvsr( VectorRegister d, Register s1, Register s2);
aoqi@0	1805	inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1806	inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1807	inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1808	inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1809	inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1810	inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1811	inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1812	inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1813	inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1814	inline void vupkhpx( VectorRegister d, VectorRegister b);
aoqi@0	1815	inline void vupkhsb( VectorRegister d, VectorRegister b);
aoqi@0	1816	inline void vupkhsh( VectorRegister d, VectorRegister b);
aoqi@0	1817	inline void vupklpx( VectorRegister d, VectorRegister b);
aoqi@0	1818	inline void vupklsb( VectorRegister d, VectorRegister b);
aoqi@0	1819	inline void vupklsh( VectorRegister d, VectorRegister b);
aoqi@0	1820	inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1821	inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1822	inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1823	inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1824	inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1825	inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1826	inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
aoqi@0	1827	inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
aoqi@0	1828	inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
aoqi@0	1829	inline void vspltisb( VectorRegister d, int si5);
aoqi@0	1830	inline void vspltish( VectorRegister d, int si5);
aoqi@0	1831	inline void vspltisw( VectorRegister d, int si5);
aoqi@0	1832	inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1833	inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1834	inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1835	inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
aoqi@0	1836	inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1837	inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1838	inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1839	inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1840	inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1841	inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1842	inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1843	inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1844	inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1845	inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1846	inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1847	inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1848	inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1849	inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1850	inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1851	inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1852	inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1853	inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1854	inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1855	inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1856	inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1857	inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1858	inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1859	inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1860	inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1861	inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1862	inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1863	inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1864	inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1865	inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1866	inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1867	inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1868	inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1869	inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1870	inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1871	inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1872	inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1873	inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1874	inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1875	inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
aoqi@0	1876	inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1877	inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1878	inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1879	inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1880	inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1881	inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1882	inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1883	inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1884	inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1885	inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1886	inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1887	inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1888	inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1889	inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1890	inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1891	inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1892	inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1893	inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1894	inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1895	inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1896	inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1897	inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1898	inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1899	inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1900	inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1901	inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1902	inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1903	inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1904	inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1905	inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1906	inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1907	inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1908	inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1909	inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1910	inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1911	inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1912	inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1913	inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1914	inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1915	inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1916	inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1917	inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1918	inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1919	inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1920	inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1921	inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
simonis@8608	1922	inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1923	inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1924	inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1925	inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1926	inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1927	inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1928	inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1929	inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1930	inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1931	inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1932	inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1933	inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1934	inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
aoqi@0	1935	// Vector Floating-Point not implemented yet
aoqi@0	1936	inline void mtvscr( VectorRegister b);
aoqi@0	1937	inline void mfvscr( VectorRegister d);
aoqi@0	1938
goetz@7222	1939	// AES (introduced with Power 8)
goetz@7222	1940	inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1941	inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1942	inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1943	inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1944	inline void vsbox( VectorRegister d, VectorRegister a);
goetz@7222	1945
goetz@7222	1946	// SHA (introduced with Power 8)
goetz@7222	1947	// Not yet implemented.
goetz@7222	1948
goetz@7222	1949	// Vector Binary Polynomial Multiplication (introduced with Power 8)
goetz@7222	1950	inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1951	inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1952	inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1953	inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
goetz@7222	1954
goetz@7222	1955	// Vector Permute and Xor (introduced with Power 8)
goetz@7222	1956	inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
goetz@7222	1957
goetz@7222	1958	// Transactional Memory instructions (introduced with Power 8)
goetz@7222	1959	inline void tbegin_(); // R=0
goetz@7222	1960	inline void tbeginrot_(); // R=1 Rollback-Only Transaction
goetz@7222	1961	inline void tend_(); // A=0
goetz@7222	1962	inline void tendall_(); // A=1
goetz@7222	1963	inline void tabort_(Register a);
goetz@7222	1964	inline void tabortwc_(int t, Register a, Register b);
goetz@7222	1965	inline void tabortwci_(int t, Register a, int si);
goetz@7222	1966	inline void tabortdc_(int t, Register a, Register b);
goetz@7222	1967	inline void tabortdci_(int t, Register a, int si);
goetz@7222	1968	inline void tsuspend_(); // tsr with L=0
goetz@7222	1969	inline void tresume_(); // tsr with L=1
goetz@7222	1970	inline void tcheck(int f);
goetz@7222	1971
aoqi@0	1972	// The following encoders use r0 as second operand. These instructions
aoqi@0	1973	// read r0 as '0'.
aoqi@0	1974	inline void lwzx( Register d, Register s2);
aoqi@0	1975	inline void lwz( Register d, int si16);
aoqi@0	1976	inline void lwax( Register d, Register s2);
aoqi@0	1977	inline void lwa( Register d, int si16);
kvn@7132	1978	inline void lwbrx(Register d, Register s2);
aoqi@0	1979	inline void lhzx( Register d, Register s2);
aoqi@0	1980	inline void lhz( Register d, int si16);
aoqi@0	1981	inline void lhax( Register d, Register s2);
aoqi@0	1982	inline void lha( Register d, int si16);
kvn@7132	1983	inline void lhbrx(Register d, Register s2);
aoqi@0	1984	inline void lbzx( Register d, Register s2);
aoqi@0	1985	inline void lbz( Register d, int si16);
aoqi@0	1986	inline void ldx( Register d, Register s2);
aoqi@0	1987	inline void ld( Register d, int si16);
aoqi@0	1988	inline void stwx( Register d, Register s2);
aoqi@0	1989	inline void stw( Register d, int si16);
aoqi@0	1990	inline void sthx( Register d, Register s2);
aoqi@0	1991	inline void sth( Register d, int si16);
aoqi@0	1992	inline void stbx( Register d, Register s2);
aoqi@0	1993	inline void stb( Register d, int si16);
aoqi@0	1994	inline void stdx( Register d, Register s2);
aoqi@0	1995	inline void std( Register d, int si16);
aoqi@0	1996
aoqi@0	1997	// PPC 2, section 3.2.1 Instruction Cache Instructions
aoqi@0	1998	inline void icbi( Register s2);
aoqi@0	1999	// PPC 2, section 3.2.2 Data Cache Instructions
aoqi@0	2000	//inlinevoid dcba( Register s2); // Instruction for embedded processor only.
aoqi@0	2001	inline void dcbz( Register s2);
aoqi@0	2002	inline void dcbst( Register s2);
aoqi@0	2003	inline void dcbf( Register s2);
aoqi@0	2004	// dcache read hint
aoqi@0	2005	inline void dcbt( Register s2);
aoqi@0	2006	inline void dcbtct( Register s2, int ct);
aoqi@0	2007	inline void dcbtds( Register s2, int ds);
aoqi@0	2008	// dcache write hint
aoqi@0	2009	inline void dcbtst( Register s2);
aoqi@0	2010	inline void dcbtstct(Register s2, int ct);
aoqi@0	2011
aoqi@0	2012	// Atomics: use ra0mem to disallow R0 as base.
aoqi@0	2013	inline void lwarx_unchecked(Register d, Register b, int eh1);
aoqi@0	2014	inline void ldarx_unchecked(Register d, Register b, int eh1);
aoqi@0	2015	inline void lwarx( Register d, Register b, bool hint_exclusive_access);
aoqi@0	2016	inline void ldarx( Register d, Register b, bool hint_exclusive_access);
aoqi@0	2017	inline void stwcx_(Register s, Register b);
aoqi@0	2018	inline void stdcx_(Register s, Register b);
aoqi@0	2019	inline void lfs( FloatRegister d, int si16);
aoqi@0	2020	inline void lfsx( FloatRegister d, Register b);
aoqi@0	2021	inline void lfd( FloatRegister d, int si16);
aoqi@0	2022	inline void lfdx( FloatRegister d, Register b);
aoqi@0	2023	inline void stfs( FloatRegister s, int si16);
aoqi@0	2024	inline void stfsx( FloatRegister s, Register b);
aoqi@0	2025	inline void stfd( FloatRegister s, int si16);
aoqi@0	2026	inline void stfdx( FloatRegister s, Register b);
aoqi@0	2027	inline void lvebx( VectorRegister d, Register s2);
aoqi@0	2028	inline void lvehx( VectorRegister d, Register s2);
aoqi@0	2029	inline void lvewx( VectorRegister d, Register s2);
aoqi@0	2030	inline void lvx( VectorRegister d, Register s2);
aoqi@0	2031	inline void lvxl( VectorRegister d, Register s2);
aoqi@0	2032	inline void stvebx(VectorRegister d, Register s2);
aoqi@0	2033	inline void stvehx(VectorRegister d, Register s2);
aoqi@0	2034	inline void stvewx(VectorRegister d, Register s2);
aoqi@0	2035	inline void stvx( VectorRegister d, Register s2);
aoqi@0	2036	inline void stvxl( VectorRegister d, Register s2);
aoqi@0	2037	inline void lvsl( VectorRegister d, Register s2);
aoqi@0	2038	inline void lvsr( VectorRegister d, Register s2);
aoqi@0	2039
aoqi@0	2040	// RegisterOrConstant versions.
aoqi@0	2041	// These emitters choose between the versions using two registers and
aoqi@0	2042	// those with register and immediate, depending on the content of roc.
aoqi@0	2043	// If the constant is not encodable as immediate, instructions to
aoqi@0	2044	// load the constant are emitted beforehand. Store instructions need a
aoqi@0	2045	// tmp reg if the constant is not encodable as immediate.
aoqi@0	2046	// Size unpredictable.
aoqi@0	2047	void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2048	void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2049	void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2050	void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2051	void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2052	void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
aoqi@0	2053	void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
aoqi@0	2054	void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
aoqi@0	2055	void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
aoqi@0	2056	void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
aoqi@0	2057	void add( Register d, RegisterOrConstant roc, Register s1);
aoqi@0	2058	void subf(Register d, RegisterOrConstant roc, Register s1);
aoqi@0	2059	void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
aoqi@0	2060
aoqi@0	2061
aoqi@0	2062	// Emit several instructions to load a 64 bit constant. This issues a fixed
aoqi@0	2063	// instruction pattern so that the constant can be patched later on.
aoqi@0	2064	enum {
aoqi@0	2065	load_const_size = 5 * BytesPerInstWord
aoqi@0	2066	};
aoqi@0	2067	void load_const(Register d, long a, Register tmp = noreg);
aoqi@0	2068	inline void load_const(Register d, void* a, Register tmp = noreg);
aoqi@0	2069	inline void load_const(Register d, Label& L, Register tmp = noreg);
aoqi@0	2070	inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
aoqi@0	2071
aoqi@0	2072	// Load a 64 bit constant, optimized, not identifyable.
aoqi@0	2073	// Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
aoqi@0	2074	// 16 bit immediate offset. This is useful if the offset can be encoded in
aoqi@0	2075	// a succeeding instruction.
aoqi@0	2076	int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
aoqi@0	2077	inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
aoqi@0	2078	return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
aoqi@0	2079	}
aoqi@0	2080
aoqi@0	2081	// Creation
aoqi@0	2082	Assembler(CodeBuffer* code) : AbstractAssembler(code) {
aoqi@0	2083	#ifdef CHECK_DELAY
aoqi@0	2084	delay_state = no_delay;
aoqi@0	2085	#endif
aoqi@0	2086	}
aoqi@0	2087
aoqi@0	2088	// Testing
aoqi@0	2089	#ifndef PRODUCT
aoqi@0	2090	void test_asm();
aoqi@0	2091	#endif
aoqi@0	2092	};
aoqi@0	2093
aoqi@0	2094
aoqi@0	2095	#endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP