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src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp@a5dd6e3ef9f3 (annotated)
src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp
Mon, 27 Aug 2012 15:17:17 -0700
- author
- twisti
- date
- Mon, 27 Aug 2012 15:17:17 -0700
- changeset 4020
- a5dd6e3ef9f3
- parent 3435
- 898522ae3c32
- child 4153
- b9a9ed0f8eeb
- permissions
- -rw-r--r--
6677625: Move platform specific flags from globals.hpp to globals_<arch>.hpp
Reviewed-by: kvn, dholmes, coleenp
Contributed-by: Tao Mao <tao.mao@oracle.com>
| duke@435 | 1 | /* |
| iveresov@2138 | 2 | * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| duke@435 | 4 | * |
| duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
| duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
| duke@435 | 7 | * published by the Free Software Foundation. |
| duke@435 | 8 | * |
| duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
| duke@435 | 13 | * accompanied this code). |
| duke@435 | 14 | * |
| duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
| duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
| duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| duke@435 | 18 | * |
| trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
| trims@1907 | 21 | * questions. |
| duke@435 | 22 | * |
| duke@435 | 23 | */ |
| duke@435 | 24 | |
| stefank@2314 | 25 | #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |
| stefank@2314 | 26 | #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |
| stefank@2314 | 27 | |
| duke@435 | 28 | private: |
| duke@435 | 29 | |
| duke@435 | 30 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| duke@435 | 31 | // |
| duke@435 | 32 | // Sparc load/store emission |
| duke@435 | 33 | // |
| duke@435 | 34 | // The sparc ld/st instructions cannot accomodate displacements > 13 bits long. |
| duke@435 | 35 | // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode |
| duke@435 | 36 | // by allowing 32 bit displacements: |
| duke@435 | 37 | // |
| duke@435 | 38 | // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]). |
| duke@435 | 39 | // When disp > 13 bits long, code is emitted to set the displacement into the O7 register, |
| duke@435 | 40 | // and then a load or store is emitted with ([O7] + [d]). |
| duke@435 | 41 | // |
| duke@435 | 42 | |
| iveresov@2344 | 43 | int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned); |
| iveresov@2344 | 44 | int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide); |
| duke@435 | 45 | |
| iveresov@2344 | 46 | int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned); |
| iveresov@2344 | 47 | int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide); |
| duke@435 | 48 | |
| duke@435 | 49 | void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no); |
| duke@435 | 50 | |
| duke@435 | 51 | int shift_amount(BasicType t); |
| duke@435 | 52 | |
| duke@435 | 53 | static bool is_single_instruction(LIR_Op* op); |
| duke@435 | 54 | |
| iveresov@2138 | 55 | // Record the type of the receiver in ReceiverTypeData |
| iveresov@2138 | 56 | void type_profile_helper(Register mdo, int mdo_offset_bias, |
| iveresov@2138 | 57 | ciMethodData *md, ciProfileData *data, |
| iveresov@2138 | 58 | Register recv, Register tmp1, Label* update_done); |
| iveresov@2146 | 59 | // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot. |
| iveresov@2146 | 60 | void setup_md_access(ciMethod* method, int bci, |
| iveresov@2146 | 61 | ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias); |
| duke@435 | 62 | public: |
| iveresov@2138 | 63 | void pack64(LIR_Opr src, LIR_Opr dst); |
| iveresov@2138 | 64 | void unpack64(LIR_Opr src, LIR_Opr dst); |
| duke@435 | 65 | |
| duke@435 | 66 | enum { |
| duke@435 | 67 | #ifdef _LP64 |
| duke@435 | 68 | call_stub_size = 68, |
| duke@435 | 69 | #else |
| duke@435 | 70 | call_stub_size = 20, |
| duke@435 | 71 | #endif // _LP64 |
| iveresov@3435 | 72 | exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(128), |
| iveresov@3435 | 73 | deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(64) }; |
| stefank@2314 | 74 | |
| stefank@2314 | 75 | #endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |
