Wed, 21 Jan 2015 12:38:11 +0100
8068013: [TESTBUG] Aix support in hotspot jtreg tests
Reviewed-by: ctornqvi, fzhinkin, farvidsson
duke@435 | 1 | /* |
drchase@6680 | 2 | * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
twisti@4318 | 26 | #include "asm/macroAssembler.hpp" |
stefank@2314 | 27 | #include "memory/resourceArea.hpp" |
stefank@2314 | 28 | #include "nativeInst_x86.hpp" |
stefank@2314 | 29 | #include "oops/oop.inline.hpp" |
stefank@2314 | 30 | #include "runtime/handles.hpp" |
stefank@2314 | 31 | #include "runtime/sharedRuntime.hpp" |
stefank@2314 | 32 | #include "runtime/stubRoutines.hpp" |
stefank@2314 | 33 | #include "utilities/ostream.hpp" |
stefank@2314 | 34 | #ifdef COMPILER1 |
stefank@2314 | 35 | #include "c1/c1_Runtime1.hpp" |
stefank@2314 | 36 | #endif |
duke@435 | 37 | |
drchase@6680 | 38 | PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC |
drchase@6680 | 39 | |
duke@435 | 40 | void NativeInstruction::wrote(int offset) { |
duke@435 | 41 | ICache::invalidate_word(addr_at(offset)); |
duke@435 | 42 | } |
duke@435 | 43 | |
duke@435 | 44 | |
duke@435 | 45 | void NativeCall::verify() { |
duke@435 | 46 | // Make sure code pattern is actually a call imm32 instruction. |
duke@435 | 47 | int inst = ubyte_at(0); |
duke@435 | 48 | if (inst != instruction_code) { |
duke@435 | 49 | tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(), |
duke@435 | 50 | inst); |
duke@435 | 51 | fatal("not a call disp32"); |
duke@435 | 52 | } |
duke@435 | 53 | } |
duke@435 | 54 | |
duke@435 | 55 | address NativeCall::destination() const { |
duke@435 | 56 | // Getting the destination of a call isn't safe because that call can |
duke@435 | 57 | // be getting patched while you're calling this. There's only special |
duke@435 | 58 | // places where this can be called but not automatically verifiable by |
duke@435 | 59 | // checking which locks are held. The solution is true atomic patching |
duke@435 | 60 | // on x86, nyi. |
duke@435 | 61 | return return_address() + displacement(); |
duke@435 | 62 | } |
duke@435 | 63 | |
duke@435 | 64 | void NativeCall::print() { |
duke@435 | 65 | tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT, |
duke@435 | 66 | instruction_address(), destination()); |
duke@435 | 67 | } |
duke@435 | 68 | |
duke@435 | 69 | // Inserts a native call instruction at a given pc |
duke@435 | 70 | void NativeCall::insert(address code_pos, address entry) { |
duke@435 | 71 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 72 | #ifdef AMD64 |
duke@435 | 73 | guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); |
duke@435 | 74 | #endif // AMD64 |
duke@435 | 75 | *code_pos = instruction_code; |
duke@435 | 76 | *((int32_t *)(code_pos+1)) = (int32_t) disp; |
duke@435 | 77 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 78 | } |
duke@435 | 79 | |
duke@435 | 80 | // MT-safe patching of a call instruction. |
duke@435 | 81 | // First patches first word of instruction to two jmp's that jmps to them |
duke@435 | 82 | // selfs (spinlock). Then patches the last byte, and then atomicly replaces |
duke@435 | 83 | // the jmp's with the first 4 byte of the new instruction. |
duke@435 | 84 | void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 85 | assert(Patching_lock->is_locked() || |
duke@435 | 86 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 87 | assert (instr_addr != NULL, "illegal address for code patching"); |
duke@435 | 88 | |
duke@435 | 89 | NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call |
duke@435 | 90 | if (os::is_MP()) { |
duke@435 | 91 | guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned"); |
duke@435 | 92 | } |
duke@435 | 93 | |
duke@435 | 94 | // First patch dummy jmp in place |
duke@435 | 95 | unsigned char patch[4]; |
duke@435 | 96 | assert(sizeof(patch)==sizeof(jint), "sanity check"); |
duke@435 | 97 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 98 | patch[1] = 0xFE; // jmp to self |
duke@435 | 99 | patch[2] = 0xEB; |
duke@435 | 100 | patch[3] = 0xFE; |
duke@435 | 101 | |
duke@435 | 102 | // First patch dummy jmp in place |
duke@435 | 103 | *(jint*)instr_addr = *(jint *)patch; |
duke@435 | 104 | |
duke@435 | 105 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 106 | n_call->wrote(0); |
duke@435 | 107 | |
duke@435 | 108 | // Patch 4th byte |
duke@435 | 109 | instr_addr[4] = code_buffer[4]; |
duke@435 | 110 | |
duke@435 | 111 | n_call->wrote(4); |
duke@435 | 112 | |
duke@435 | 113 | // Patch bytes 0-3 |
duke@435 | 114 | *(jint*)instr_addr = *(jint *)code_buffer; |
duke@435 | 115 | |
duke@435 | 116 | n_call->wrote(0); |
duke@435 | 117 | |
duke@435 | 118 | #ifdef ASSERT |
duke@435 | 119 | // verify patching |
duke@435 | 120 | for ( int i = 0; i < instruction_size; i++) { |
duke@435 | 121 | address ptr = (address)((intptr_t)code_buffer + i); |
duke@435 | 122 | int a_byte = (*ptr) & 0xFF; |
duke@435 | 123 | assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed"); |
duke@435 | 124 | } |
duke@435 | 125 | #endif |
duke@435 | 126 | |
duke@435 | 127 | } |
duke@435 | 128 | |
duke@435 | 129 | |
duke@435 | 130 | // Similar to replace_mt_safe, but just changes the destination. The |
duke@435 | 131 | // important thing is that free-running threads are able to execute this |
duke@435 | 132 | // call instruction at all times. If the displacement field is aligned |
duke@435 | 133 | // we can simply rely on atomicity of 32-bit writes to make sure other threads |
duke@435 | 134 | // will see no intermediate states. Otherwise, the first two bytes of the |
duke@435 | 135 | // call are guaranteed to be aligned, and can be atomically patched to a |
duke@435 | 136 | // self-loop to guard the instruction while we change the other bytes. |
duke@435 | 137 | |
duke@435 | 138 | // We cannot rely on locks here, since the free-running threads must run at |
duke@435 | 139 | // full speed. |
duke@435 | 140 | // |
duke@435 | 141 | // Used in the runtime linkage of calls; see class CompiledIC. |
duke@435 | 142 | // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.) |
duke@435 | 143 | void NativeCall::set_destination_mt_safe(address dest) { |
duke@435 | 144 | debug_only(verify()); |
duke@435 | 145 | // Make sure patching code is locked. No two threads can patch at the same |
duke@435 | 146 | // time but one may be executing this code. |
duke@435 | 147 | assert(Patching_lock->is_locked() || |
duke@435 | 148 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 149 | // Both C1 and C2 should now be generating code which aligns the patched address |
duke@435 | 150 | // to be within a single cache line except that C1 does not do the alignment on |
duke@435 | 151 | // uniprocessor systems. |
duke@435 | 152 | bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size == |
duke@435 | 153 | ((uintptr_t)displacement_address() + 3) / cache_line_size; |
duke@435 | 154 | |
duke@435 | 155 | guarantee(!os::is_MP() || is_aligned, "destination must be aligned"); |
duke@435 | 156 | |
duke@435 | 157 | if (is_aligned) { |
duke@435 | 158 | // Simple case: The destination lies within a single cache line. |
duke@435 | 159 | set_destination(dest); |
duke@435 | 160 | } else if ((uintptr_t)instruction_address() / cache_line_size == |
duke@435 | 161 | ((uintptr_t)instruction_address()+1) / cache_line_size) { |
duke@435 | 162 | // Tricky case: The instruction prefix lies within a single cache line. |
duke@435 | 163 | intptr_t disp = dest - return_address(); |
duke@435 | 164 | #ifdef AMD64 |
duke@435 | 165 | guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); |
duke@435 | 166 | #endif // AMD64 |
duke@435 | 167 | |
duke@435 | 168 | int call_opcode = instruction_address()[0]; |
duke@435 | 169 | |
duke@435 | 170 | // First patch dummy jump in place: |
duke@435 | 171 | { |
duke@435 | 172 | u_char patch_jump[2]; |
duke@435 | 173 | patch_jump[0] = 0xEB; // jmp rel8 |
duke@435 | 174 | patch_jump[1] = 0xFE; // jmp to self |
duke@435 | 175 | |
duke@435 | 176 | assert(sizeof(patch_jump)==sizeof(short), "sanity check"); |
duke@435 | 177 | *(short*)instruction_address() = *(short*)patch_jump; |
duke@435 | 178 | } |
duke@435 | 179 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 180 | wrote(0); |
duke@435 | 181 | |
duke@435 | 182 | // (Note: We assume any reader which has already started to read |
duke@435 | 183 | // the unpatched call will completely read the whole unpatched call |
duke@435 | 184 | // without seeing the next writes we are about to make.) |
duke@435 | 185 | |
duke@435 | 186 | // Next, patch the last three bytes: |
duke@435 | 187 | u_char patch_disp[5]; |
duke@435 | 188 | patch_disp[0] = call_opcode; |
duke@435 | 189 | *(int32_t*)&patch_disp[1] = (int32_t)disp; |
duke@435 | 190 | assert(sizeof(patch_disp)==instruction_size, "sanity check"); |
duke@435 | 191 | for (int i = sizeof(short); i < instruction_size; i++) |
duke@435 | 192 | instruction_address()[i] = patch_disp[i]; |
duke@435 | 193 | |
duke@435 | 194 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 195 | wrote(sizeof(short)); |
duke@435 | 196 | |
duke@435 | 197 | // (Note: We assume that any reader which reads the opcode we are |
duke@435 | 198 | // about to repatch will also read the writes we just made.) |
duke@435 | 199 | |
duke@435 | 200 | // Finally, overwrite the jump: |
duke@435 | 201 | *(short*)instruction_address() = *(short*)patch_disp; |
duke@435 | 202 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 203 | wrote(0); |
duke@435 | 204 | |
duke@435 | 205 | debug_only(verify()); |
duke@435 | 206 | guarantee(destination() == dest, "patch succeeded"); |
duke@435 | 207 | } else { |
duke@435 | 208 | // Impossible: One or the other must be atomically writable. |
duke@435 | 209 | ShouldNotReachHere(); |
duke@435 | 210 | } |
duke@435 | 211 | } |
duke@435 | 212 | |
duke@435 | 213 | |
duke@435 | 214 | void NativeMovConstReg::verify() { |
duke@435 | 215 | #ifdef AMD64 |
duke@435 | 216 | // make sure code pattern is actually a mov reg64, imm64 instruction |
duke@435 | 217 | if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) || |
duke@435 | 218 | (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) { |
duke@435 | 219 | print(); |
duke@435 | 220 | fatal("not a REX.W[B] mov reg64, imm64"); |
duke@435 | 221 | } |
duke@435 | 222 | #else |
duke@435 | 223 | // make sure code pattern is actually a mov reg, imm32 instruction |
duke@435 | 224 | u_char test_byte = *(u_char*)instruction_address(); |
duke@435 | 225 | u_char test_byte_2 = test_byte & ( 0xff ^ register_mask); |
duke@435 | 226 | if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32"); |
duke@435 | 227 | #endif // AMD64 |
duke@435 | 228 | } |
duke@435 | 229 | |
duke@435 | 230 | |
duke@435 | 231 | void NativeMovConstReg::print() { |
duke@435 | 232 | tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT, |
duke@435 | 233 | instruction_address(), data()); |
duke@435 | 234 | } |
duke@435 | 235 | |
duke@435 | 236 | //------------------------------------------------------------------- |
duke@435 | 237 | |
never@739 | 238 | int NativeMovRegMem::instruction_start() const { |
never@739 | 239 | int off = 0; |
never@739 | 240 | u_char instr_0 = ubyte_at(off); |
duke@435 | 241 | |
kvn@3388 | 242 | // See comment in Assembler::locate_operand() about VEX prefixes. |
kvn@3388 | 243 | if (instr_0 == instruction_VEX_prefix_2bytes) { |
kvn@3388 | 244 | assert((UseAVX > 0), "shouldn't have VEX prefix"); |
kvn@3388 | 245 | NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions")); |
kvn@3388 | 246 | return 2; |
kvn@3388 | 247 | } |
kvn@3388 | 248 | if (instr_0 == instruction_VEX_prefix_3bytes) { |
kvn@3388 | 249 | assert((UseAVX > 0), "shouldn't have VEX prefix"); |
kvn@3388 | 250 | NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions")); |
kvn@3388 | 251 | return 3; |
kvn@3388 | 252 | } |
kvn@3388 | 253 | |
never@739 | 254 | // First check to see if we have a (prefixed or not) xor |
kvn@3388 | 255 | if (instr_0 >= instruction_prefix_wide_lo && // 0x40 |
kvn@3388 | 256 | instr_0 <= instruction_prefix_wide_hi) { // 0x4f |
never@739 | 257 | off++; |
never@739 | 258 | instr_0 = ubyte_at(off); |
never@739 | 259 | } |
duke@435 | 260 | |
never@739 | 261 | if (instr_0 == instruction_code_xor) { |
never@739 | 262 | off += 2; |
never@739 | 263 | instr_0 = ubyte_at(off); |
duke@435 | 264 | } |
duke@435 | 265 | |
never@739 | 266 | // Now look for the real instruction and the many prefix/size specifiers. |
never@739 | 267 | |
never@739 | 268 | if (instr_0 == instruction_operandsize_prefix ) { // 0x66 |
never@739 | 269 | off++; // Not SSE instructions |
never@739 | 270 | instr_0 = ubyte_at(off); |
duke@435 | 271 | } |
never@739 | 272 | |
kvn@3388 | 273 | if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3 |
never@739 | 274 | instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2 |
never@739 | 275 | off++; |
never@739 | 276 | instr_0 = ubyte_at(off); |
never@739 | 277 | } |
never@739 | 278 | |
kvn@3388 | 279 | if ( instr_0 >= instruction_prefix_wide_lo && // 0x40 |
never@739 | 280 | instr_0 <= instruction_prefix_wide_hi) { // 0x4f |
never@739 | 281 | off++; |
never@739 | 282 | instr_0 = ubyte_at(off); |
never@739 | 283 | } |
never@739 | 284 | |
never@739 | 285 | |
never@739 | 286 | if (instr_0 == instruction_extended_prefix ) { // 0x0f |
never@739 | 287 | off++; |
never@739 | 288 | } |
never@739 | 289 | |
never@739 | 290 | return off; |
never@739 | 291 | } |
never@739 | 292 | |
never@739 | 293 | address NativeMovRegMem::instruction_address() const { |
never@739 | 294 | return addr_at(instruction_start()); |
never@739 | 295 | } |
never@739 | 296 | |
never@739 | 297 | address NativeMovRegMem::next_instruction_address() const { |
never@739 | 298 | address ret = instruction_address() + instruction_size; |
never@739 | 299 | u_char instr_0 = *(u_char*) instruction_address(); |
never@739 | 300 | switch (instr_0) { |
never@739 | 301 | case instruction_operandsize_prefix: |
never@739 | 302 | |
never@739 | 303 | fatal("should have skipped instruction_operandsize_prefix"); |
never@739 | 304 | break; |
never@739 | 305 | |
never@739 | 306 | case instruction_extended_prefix: |
never@739 | 307 | fatal("should have skipped instruction_extended_prefix"); |
never@739 | 308 | break; |
never@739 | 309 | |
never@739 | 310 | case instruction_code_mem2reg_movslq: // 0x63 |
never@739 | 311 | case instruction_code_mem2reg_movzxb: // 0xB6 |
never@739 | 312 | case instruction_code_mem2reg_movsxb: // 0xBE |
never@739 | 313 | case instruction_code_mem2reg_movzxw: // 0xB7 |
never@739 | 314 | case instruction_code_mem2reg_movsxw: // 0xBF |
never@739 | 315 | case instruction_code_reg2mem: // 0x89 (q/l) |
never@739 | 316 | case instruction_code_mem2reg: // 0x8B (q/l) |
never@739 | 317 | case instruction_code_reg2memb: // 0x88 |
never@739 | 318 | case instruction_code_mem2regb: // 0x8a |
never@739 | 319 | |
never@739 | 320 | case instruction_code_float_s: // 0xd9 fld_s a |
never@739 | 321 | case instruction_code_float_d: // 0xdd fld_d a |
never@739 | 322 | |
never@739 | 323 | case instruction_code_xmm_load: // 0x10 |
never@739 | 324 | case instruction_code_xmm_store: // 0x11 |
never@739 | 325 | case instruction_code_xmm_lpd: // 0x12 |
never@739 | 326 | { |
never@739 | 327 | // If there is an SIB then instruction is longer than expected |
never@739 | 328 | u_char mod_rm = *(u_char*)(instruction_address() + 1); |
never@739 | 329 | if ((mod_rm & 7) == 0x4) { |
never@739 | 330 | ret++; |
never@739 | 331 | } |
never@739 | 332 | } |
never@739 | 333 | case instruction_code_xor: |
never@739 | 334 | fatal("should have skipped xor lead in"); |
never@739 | 335 | break; |
never@739 | 336 | |
never@739 | 337 | default: |
never@739 | 338 | fatal("not a NativeMovRegMem"); |
never@739 | 339 | } |
never@739 | 340 | return ret; |
never@739 | 341 | |
never@739 | 342 | } |
never@739 | 343 | |
never@739 | 344 | int NativeMovRegMem::offset() const{ |
never@739 | 345 | int off = data_offset + instruction_start(); |
never@739 | 346 | u_char mod_rm = *(u_char*)(instruction_address() + 1); |
never@739 | 347 | // nnnn(r12|rsp) isn't coded as simple mod/rm since that is |
never@739 | 348 | // the encoding to use an SIB byte. Which will have the nnnn |
never@739 | 349 | // field off by one byte |
never@739 | 350 | if ((mod_rm & 7) == 0x4) { |
never@739 | 351 | off++; |
never@739 | 352 | } |
never@739 | 353 | return int_at(off); |
never@739 | 354 | } |
never@739 | 355 | |
never@739 | 356 | void NativeMovRegMem::set_offset(int x) { |
never@739 | 357 | int off = data_offset + instruction_start(); |
never@739 | 358 | u_char mod_rm = *(u_char*)(instruction_address() + 1); |
never@739 | 359 | // nnnn(r12|rsp) isn't coded as simple mod/rm since that is |
never@739 | 360 | // the encoding to use an SIB byte. Which will have the nnnn |
never@739 | 361 | // field off by one byte |
never@739 | 362 | if ((mod_rm & 7) == 0x4) { |
never@739 | 363 | off++; |
never@739 | 364 | } |
never@739 | 365 | set_int_at(off, x); |
duke@435 | 366 | } |
duke@435 | 367 | |
duke@435 | 368 | void NativeMovRegMem::verify() { |
duke@435 | 369 | // make sure code pattern is actually a mov [reg+offset], reg instruction |
duke@435 | 370 | u_char test_byte = *(u_char*)instruction_address(); |
never@739 | 371 | switch (test_byte) { |
never@739 | 372 | case instruction_code_reg2memb: // 0x88 movb a, r |
never@739 | 373 | case instruction_code_reg2mem: // 0x89 movl a, r (can be movq in 64bit) |
never@739 | 374 | case instruction_code_mem2regb: // 0x8a movb r, a |
never@739 | 375 | case instruction_code_mem2reg: // 0x8b movl r, a (can be movq in 64bit) |
never@739 | 376 | break; |
never@739 | 377 | |
never@739 | 378 | case instruction_code_mem2reg_movslq: // 0x63 movsql r, a |
never@739 | 379 | case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb) |
never@739 | 380 | case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw) |
never@739 | 381 | case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb) |
never@739 | 382 | case instruction_code_mem2reg_movsxw: // 0xbf movswl r, a (movsxw) |
never@739 | 383 | break; |
never@739 | 384 | |
never@739 | 385 | case instruction_code_float_s: // 0xd9 fld_s a |
never@739 | 386 | case instruction_code_float_d: // 0xdd fld_d a |
never@739 | 387 | case instruction_code_xmm_load: // 0x10 movsd xmm, a |
never@739 | 388 | case instruction_code_xmm_store: // 0x11 movsd a, xmm |
never@739 | 389 | case instruction_code_xmm_lpd: // 0x12 movlpd xmm, a |
never@739 | 390 | break; |
never@739 | 391 | |
never@739 | 392 | default: |
duke@435 | 393 | fatal ("not a mov [reg+offs], reg instruction"); |
duke@435 | 394 | } |
duke@435 | 395 | } |
duke@435 | 396 | |
duke@435 | 397 | |
duke@435 | 398 | void NativeMovRegMem::print() { |
duke@435 | 399 | tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset()); |
duke@435 | 400 | } |
duke@435 | 401 | |
duke@435 | 402 | //------------------------------------------------------------------- |
duke@435 | 403 | |
duke@435 | 404 | void NativeLoadAddress::verify() { |
duke@435 | 405 | // make sure code pattern is actually a mov [reg+offset], reg instruction |
duke@435 | 406 | u_char test_byte = *(u_char*)instruction_address(); |
never@739 | 407 | #ifdef _LP64 |
never@739 | 408 | if ( (test_byte == instruction_prefix_wide || |
never@739 | 409 | test_byte == instruction_prefix_wide_extended) ) { |
never@739 | 410 | test_byte = *(u_char*)(instruction_address() + 1); |
never@739 | 411 | } |
never@739 | 412 | #endif // _LP64 |
never@739 | 413 | if ( ! ((test_byte == lea_instruction_code) |
never@739 | 414 | LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) { |
duke@435 | 415 | fatal ("not a lea reg, [reg+offs] instruction"); |
duke@435 | 416 | } |
duke@435 | 417 | } |
duke@435 | 418 | |
duke@435 | 419 | |
duke@435 | 420 | void NativeLoadAddress::print() { |
duke@435 | 421 | tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset()); |
duke@435 | 422 | } |
duke@435 | 423 | |
duke@435 | 424 | //-------------------------------------------------------------------------------- |
duke@435 | 425 | |
duke@435 | 426 | void NativeJump::verify() { |
duke@435 | 427 | if (*(u_char*)instruction_address() != instruction_code) { |
duke@435 | 428 | fatal("not a jump instruction"); |
duke@435 | 429 | } |
duke@435 | 430 | } |
duke@435 | 431 | |
duke@435 | 432 | |
duke@435 | 433 | void NativeJump::insert(address code_pos, address entry) { |
duke@435 | 434 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 435 | #ifdef AMD64 |
duke@435 | 436 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 437 | #endif // AMD64 |
duke@435 | 438 | |
duke@435 | 439 | *code_pos = instruction_code; |
duke@435 | 440 | *((int32_t*)(code_pos + 1)) = (int32_t)disp; |
duke@435 | 441 | |
duke@435 | 442 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 443 | } |
duke@435 | 444 | |
duke@435 | 445 | void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) { |
duke@435 | 446 | // Patching to not_entrant can happen while activations of the method are |
duke@435 | 447 | // in use. The patching in that instance must happen only when certain |
duke@435 | 448 | // alignment restrictions are true. These guarantees check those |
duke@435 | 449 | // conditions. |
duke@435 | 450 | #ifdef AMD64 |
duke@435 | 451 | const int linesize = 64; |
duke@435 | 452 | #else |
duke@435 | 453 | const int linesize = 32; |
duke@435 | 454 | #endif // AMD64 |
duke@435 | 455 | |
duke@435 | 456 | // Must be wordSize aligned |
duke@435 | 457 | guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0, |
duke@435 | 458 | "illegal address for code patching 2"); |
duke@435 | 459 | // First 5 bytes must be within the same cache line - 4827828 |
duke@435 | 460 | guarantee((uintptr_t) verified_entry / linesize == |
duke@435 | 461 | ((uintptr_t) verified_entry + 4) / linesize, |
duke@435 | 462 | "illegal address for code patching 3"); |
duke@435 | 463 | } |
duke@435 | 464 | |
duke@435 | 465 | |
duke@435 | 466 | // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) |
duke@435 | 467 | // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes. |
duke@435 | 468 | // First patches the first word atomically to be a jump to itself. |
duke@435 | 469 | // Then patches the last byte and then atomically patches the first word (4-bytes), |
duke@435 | 470 | // thus inserting the desired jump |
duke@435 | 471 | // This code is mt-safe with the following conditions: entry point is 4 byte aligned, |
duke@435 | 472 | // entry point is in same cache line as unverified entry point, and the instruction being |
duke@435 | 473 | // patched is >= 5 byte (size of patch). |
duke@435 | 474 | // |
duke@435 | 475 | // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit. |
duke@435 | 476 | // In C1 the restriction is enforced by CodeEmitter::method_entry |
duke@435 | 477 | // |
duke@435 | 478 | void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { |
duke@435 | 479 | // complete jump instruction (to be inserted) is in code_buffer; |
duke@435 | 480 | unsigned char code_buffer[5]; |
duke@435 | 481 | code_buffer[0] = instruction_code; |
duke@435 | 482 | intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4); |
duke@435 | 483 | #ifdef AMD64 |
duke@435 | 484 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 485 | #endif // AMD64 |
duke@435 | 486 | *(int32_t*)(code_buffer + 1) = (int32_t)disp; |
duke@435 | 487 | |
duke@435 | 488 | check_verified_entry_alignment(entry, verified_entry); |
duke@435 | 489 | |
duke@435 | 490 | // Can't call nativeJump_at() because it's asserts jump exists |
duke@435 | 491 | NativeJump* n_jump = (NativeJump*) verified_entry; |
duke@435 | 492 | |
duke@435 | 493 | //First patch dummy jmp in place |
duke@435 | 494 | |
duke@435 | 495 | unsigned char patch[4]; |
duke@435 | 496 | assert(sizeof(patch)==sizeof(int32_t), "sanity check"); |
duke@435 | 497 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 498 | patch[1] = 0xFE; // jmp to self |
duke@435 | 499 | patch[2] = 0xEB; |
duke@435 | 500 | patch[3] = 0xFE; |
duke@435 | 501 | |
duke@435 | 502 | // First patch dummy jmp in place |
duke@435 | 503 | *(int32_t*)verified_entry = *(int32_t *)patch; |
duke@435 | 504 | |
duke@435 | 505 | n_jump->wrote(0); |
duke@435 | 506 | |
duke@435 | 507 | // Patch 5th byte (from jump instruction) |
duke@435 | 508 | verified_entry[4] = code_buffer[4]; |
duke@435 | 509 | |
duke@435 | 510 | n_jump->wrote(4); |
duke@435 | 511 | |
duke@435 | 512 | // Patch bytes 0-3 (from jump instruction) |
duke@435 | 513 | *(int32_t*)verified_entry = *(int32_t *)code_buffer; |
duke@435 | 514 | // Invalidate. Opteron requires a flush after every write. |
duke@435 | 515 | n_jump->wrote(0); |
duke@435 | 516 | |
duke@435 | 517 | } |
duke@435 | 518 | |
duke@435 | 519 | void NativePopReg::insert(address code_pos, Register reg) { |
duke@435 | 520 | assert(reg->encoding() < 8, "no space for REX"); |
duke@435 | 521 | assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update"); |
duke@435 | 522 | *code_pos = (u_char)(instruction_code | reg->encoding()); |
duke@435 | 523 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 524 | } |
duke@435 | 525 | |
duke@435 | 526 | |
duke@435 | 527 | void NativeIllegalInstruction::insert(address code_pos) { |
duke@435 | 528 | assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update"); |
duke@435 | 529 | *(short *)code_pos = instruction_code; |
duke@435 | 530 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 531 | } |
duke@435 | 532 | |
duke@435 | 533 | void NativeGeneralJump::verify() { |
duke@435 | 534 | assert(((NativeInstruction *)this)->is_jump() || |
duke@435 | 535 | ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); |
duke@435 | 536 | } |
duke@435 | 537 | |
duke@435 | 538 | |
duke@435 | 539 | void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { |
duke@435 | 540 | intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4); |
duke@435 | 541 | #ifdef AMD64 |
duke@435 | 542 | guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset"); |
duke@435 | 543 | #endif // AMD64 |
duke@435 | 544 | |
duke@435 | 545 | *code_pos = unconditional_long_jump; |
duke@435 | 546 | *((int32_t *)(code_pos+1)) = (int32_t) disp; |
duke@435 | 547 | ICache::invalidate_range(code_pos, instruction_size); |
duke@435 | 548 | } |
duke@435 | 549 | |
duke@435 | 550 | |
duke@435 | 551 | // MT-safe patching of a long jump instruction. |
duke@435 | 552 | // First patches first word of instruction to two jmp's that jmps to them |
duke@435 | 553 | // selfs (spinlock). Then patches the last byte, and then atomicly replaces |
duke@435 | 554 | // the jmp's with the first 4 byte of the new instruction. |
duke@435 | 555 | void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 556 | assert (instr_addr != NULL, "illegal address for code patching (4)"); |
duke@435 | 557 | NativeGeneralJump* n_jump = nativeGeneralJump_at (instr_addr); // checking that it is a jump |
duke@435 | 558 | |
duke@435 | 559 | // Temporary code |
duke@435 | 560 | unsigned char patch[4]; |
duke@435 | 561 | assert(sizeof(patch)==sizeof(int32_t), "sanity check"); |
duke@435 | 562 | patch[0] = 0xEB; // jmp rel8 |
duke@435 | 563 | patch[1] = 0xFE; // jmp to self |
duke@435 | 564 | patch[2] = 0xEB; |
duke@435 | 565 | patch[3] = 0xFE; |
duke@435 | 566 | |
duke@435 | 567 | // First patch dummy jmp in place |
duke@435 | 568 | *(int32_t*)instr_addr = *(int32_t *)patch; |
duke@435 | 569 | n_jump->wrote(0); |
duke@435 | 570 | |
duke@435 | 571 | // Patch 4th byte |
duke@435 | 572 | instr_addr[4] = code_buffer[4]; |
duke@435 | 573 | |
duke@435 | 574 | n_jump->wrote(4); |
duke@435 | 575 | |
duke@435 | 576 | // Patch bytes 0-3 |
duke@435 | 577 | *(jint*)instr_addr = *(jint *)code_buffer; |
duke@435 | 578 | |
duke@435 | 579 | n_jump->wrote(0); |
duke@435 | 580 | |
duke@435 | 581 | #ifdef ASSERT |
duke@435 | 582 | // verify patching |
duke@435 | 583 | for ( int i = 0; i < instruction_size; i++) { |
duke@435 | 584 | address ptr = (address)((intptr_t)code_buffer + i); |
duke@435 | 585 | int a_byte = (*ptr) & 0xFF; |
duke@435 | 586 | assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed"); |
duke@435 | 587 | } |
duke@435 | 588 | #endif |
duke@435 | 589 | |
duke@435 | 590 | } |
duke@435 | 591 | |
duke@435 | 592 | |
duke@435 | 593 | |
duke@435 | 594 | address NativeGeneralJump::jump_destination() const { |
duke@435 | 595 | int op_code = ubyte_at(0); |
duke@435 | 596 | bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F); |
duke@435 | 597 | int offset = (op_code == 0x0F) ? 2 : 1; |
duke@435 | 598 | int length = offset + ((is_rel32off) ? 4 : 1); |
duke@435 | 599 | |
duke@435 | 600 | if (is_rel32off) |
duke@435 | 601 | return addr_at(0) + length + int_at(offset); |
duke@435 | 602 | else |
duke@435 | 603 | return addr_at(0) + length + sbyte_at(offset); |
duke@435 | 604 | } |
kamg@551 | 605 | |
kamg@551 | 606 | bool NativeInstruction::is_dtrace_trap() { |
kamg@551 | 607 | return (*(int32_t*)this & 0xff) == 0xcc; |
kamg@551 | 608 | } |