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src/cpu/x86/vm/c1_FrameMap_x86.cpp@a1980da045cc (annotated)

src/cpu/x86/vm/c1_FrameMap_x86.cpp

Fri, 07 Nov 2008 09:29:38 -0800

author

kvn

date

Fri, 07 Nov 2008 09:29:38 -0800

changeset 855

a1980da045cc

parent 772

9ee9cf798b59

child 1907

c18cbe5936b8

child 1919

61b2245abf36

permissions

-rw-r--r--

6462850: generate biased locking code in C2 ideal graph
Summary: Inline biased locking code in C2 ideal graph during macro nodes expansion
Reviewed-by: never

duke@435	1	/*
xdono@772	2	* Copyright 1999-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	# include "incls/_precompiled.incl"
duke@435	26	# include "incls/_c1_FrameMap_x86.cpp.incl"
duke@435	27
duke@435	28	const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
duke@435	29
duke@435	30	LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
duke@435	31	LIR_Opr opr = LIR_OprFact::illegalOpr;
duke@435	32	VMReg r_1 = reg->first();
duke@435	33	VMReg r_2 = reg->second();
duke@435	34	if (r_1->is_stack()) {
duke@435	35	// Convert stack slot to an SP offset
duke@435	36	// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
duke@435	37	// so we must add it in here.
duke@435	38	int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@435	39	opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
duke@435	40	} else if (r_1->is_Register()) {
duke@435	41	Register reg = r_1->as_Register();
never@739	42	if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
duke@435	43	Register reg2 = r_2->as_Register();
never@739	44	#ifdef _LP64
never@739	45	assert(reg2 == reg, "must be same register");
never@739	46	opr = as_long_opr(reg);
never@739	47	#else
duke@435	48	opr = as_long_opr(reg2, reg);
never@739	49	#endif // _LP64
never@739	50	} else if (type == T_OBJECT || type == T_ARRAY) {
duke@435	51	opr = as_oop_opr(reg);
duke@435	52	} else {
duke@435	53	opr = as_opr(reg);
duke@435	54	}
duke@435	55	} else if (r_1->is_FloatRegister()) {
duke@435	56	assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
duke@435	57	int num = r_1->as_FloatRegister()->encoding();
duke@435	58	if (type == T_FLOAT) {
duke@435	59	opr = LIR_OprFact::single_fpu(num);
duke@435	60	} else {
duke@435	61	opr = LIR_OprFact::double_fpu(num);
duke@435	62	}
duke@435	63	} else if (r_1->is_XMMRegister()) {
duke@435	64	assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
duke@435	65	int num = r_1->as_XMMRegister()->encoding();
duke@435	66	if (type == T_FLOAT) {
duke@435	67	opr = LIR_OprFact::single_xmm(num);
duke@435	68	} else {
duke@435	69	opr = LIR_OprFact::double_xmm(num);
duke@435	70	}
duke@435	71	} else {
duke@435	72	ShouldNotReachHere();
duke@435	73	}
duke@435	74	return opr;
duke@435	75	}
duke@435	76
duke@435	77
duke@435	78	LIR_Opr FrameMap::rsi_opr;
duke@435	79	LIR_Opr FrameMap::rdi_opr;
duke@435	80	LIR_Opr FrameMap::rbx_opr;
duke@435	81	LIR_Opr FrameMap::rax_opr;
duke@435	82	LIR_Opr FrameMap::rdx_opr;
duke@435	83	LIR_Opr FrameMap::rcx_opr;
duke@435	84	LIR_Opr FrameMap::rsp_opr;
duke@435	85	LIR_Opr FrameMap::rbp_opr;
duke@435	86
duke@435	87	LIR_Opr FrameMap::receiver_opr;
duke@435	88
duke@435	89	LIR_Opr FrameMap::rsi_oop_opr;
duke@435	90	LIR_Opr FrameMap::rdi_oop_opr;
duke@435	91	LIR_Opr FrameMap::rbx_oop_opr;
duke@435	92	LIR_Opr FrameMap::rax_oop_opr;
duke@435	93	LIR_Opr FrameMap::rdx_oop_opr;
duke@435	94	LIR_Opr FrameMap::rcx_oop_opr;
duke@435	95
never@739	96	LIR_Opr FrameMap::long0_opr;
never@739	97	LIR_Opr FrameMap::long1_opr;
duke@435	98	LIR_Opr FrameMap::fpu0_float_opr;
duke@435	99	LIR_Opr FrameMap::fpu0_double_opr;
duke@435	100	LIR_Opr FrameMap::xmm0_float_opr;
duke@435	101	LIR_Opr FrameMap::xmm0_double_opr;
duke@435	102
never@739	103	#ifdef _LP64
never@739	104
never@739	105	LIR_Opr FrameMap::r8_opr;
never@739	106	LIR_Opr FrameMap::r9_opr;
never@739	107	LIR_Opr FrameMap::r10_opr;
never@739	108	LIR_Opr FrameMap::r11_opr;
never@739	109	LIR_Opr FrameMap::r12_opr;
never@739	110	LIR_Opr FrameMap::r13_opr;
never@739	111	LIR_Opr FrameMap::r14_opr;
never@739	112	LIR_Opr FrameMap::r15_opr;
never@739	113
never@739	114	// r10 and r15 can never contain oops since they aren't available to
never@739	115	// the allocator
never@739	116	LIR_Opr FrameMap::r8_oop_opr;
never@739	117	LIR_Opr FrameMap::r9_oop_opr;
never@739	118	LIR_Opr FrameMap::r11_oop_opr;
never@739	119	LIR_Opr FrameMap::r12_oop_opr;
never@739	120	LIR_Opr FrameMap::r13_oop_opr;
never@739	121	LIR_Opr FrameMap::r14_oop_opr;
never@739	122	#endif // _LP64
never@739	123
duke@435	124	LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
duke@435	125	LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
duke@435	126	LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
duke@435	127
never@739	128	XMMRegister FrameMap::_xmm_regs [] = { 0, };
duke@435	129
duke@435	130	XMMRegister FrameMap::nr2xmmreg(int rnr) {
duke@435	131	assert(_init_done, "tables not initialized");
duke@435	132	return _xmm_regs[rnr];
duke@435	133	}
duke@435	134
duke@435	135	//--------------------------------------------------------
duke@435	136	// FrameMap
duke@435	137	//--------------------------------------------------------
duke@435	138
duke@435	139	void FrameMap::init() {
duke@435	140	if (_init_done) return;
duke@435	141
never@739	142	assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
never@739	143	map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
never@739	144	map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
never@739	145	map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
never@739	146	map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
never@739	147	map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
never@739	148	map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
duke@435	149
never@739	150	#ifndef _LP64
never@739	151	// The unallocatable registers are at the end
never@739	152	map_register(6, rsp);
never@739	153	map_register(7, rbp);
never@739	154	#else
never@739	155	map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
never@739	156	map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
never@739	157	map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
never@739	158	map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
never@739	159	map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
never@739	160	map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
never@739	161	// The unallocatable registers are at the end
never@739	162	map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
never@739	163	map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
never@739	164	map_register(14, rsp);
never@739	165	map_register(15, rbp);
never@739	166	#endif // _LP64
never@739	167
never@739	168	#ifdef _LP64
never@739	169	long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
never@739	170	long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
never@739	171	#else
never@739	172	long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
never@739	173	long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
never@739	174	#endif // _LP64
duke@435	175	fpu0_float_opr = LIR_OprFact::single_fpu(0);
duke@435	176	fpu0_double_opr = LIR_OprFact::double_fpu(0);
duke@435	177	xmm0_float_opr = LIR_OprFact::single_xmm(0);
duke@435	178	xmm0_double_opr = LIR_OprFact::double_xmm(0);
duke@435	179
duke@435	180	_caller_save_cpu_regs[0] = rsi_opr;
duke@435	181	_caller_save_cpu_regs[1] = rdi_opr;
duke@435	182	_caller_save_cpu_regs[2] = rbx_opr;
duke@435	183	_caller_save_cpu_regs[3] = rax_opr;
duke@435	184	_caller_save_cpu_regs[4] = rdx_opr;
duke@435	185	_caller_save_cpu_regs[5] = rcx_opr;
duke@435	186
never@739	187	#ifdef _LP64
never@739	188	_caller_save_cpu_regs[6] = r8_opr;
never@739	189	_caller_save_cpu_regs[7] = r9_opr;
never@739	190	_caller_save_cpu_regs[8] = r11_opr;
never@739	191	_caller_save_cpu_regs[9] = r12_opr;
never@739	192	_caller_save_cpu_regs[10] = r13_opr;
never@739	193	_caller_save_cpu_regs[11] = r14_opr;
never@739	194	#endif // _LP64
never@739	195
duke@435	196
duke@435	197	_xmm_regs[0] = xmm0;
duke@435	198	_xmm_regs[1] = xmm1;
duke@435	199	_xmm_regs[2] = xmm2;
duke@435	200	_xmm_regs[3] = xmm3;
duke@435	201	_xmm_regs[4] = xmm4;
duke@435	202	_xmm_regs[5] = xmm5;
duke@435	203	_xmm_regs[6] = xmm6;
duke@435	204	_xmm_regs[7] = xmm7;
duke@435	205
never@739	206	#ifdef _LP64
never@739	207	_xmm_regs[8] = xmm8;
never@739	208	_xmm_regs[9] = xmm9;
never@739	209	_xmm_regs[10] = xmm10;
never@739	210	_xmm_regs[11] = xmm11;
never@739	211	_xmm_regs[12] = xmm12;
never@739	212	_xmm_regs[13] = xmm13;
never@739	213	_xmm_regs[14] = xmm14;
never@739	214	_xmm_regs[15] = xmm15;
never@739	215	#endif // _LP64
never@739	216
duke@435	217	for (int i = 0; i < 8; i++) {
duke@435	218	_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
never@739	219	}
never@739	220
never@739	221	for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
duke@435	222	_caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
duke@435	223	}
duke@435	224
duke@435	225	_init_done = true;
duke@435	226
never@739	227	rsi_oop_opr = as_oop_opr(rsi);
never@739	228	rdi_oop_opr = as_oop_opr(rdi);
never@739	229	rbx_oop_opr = as_oop_opr(rbx);
never@739	230	rax_oop_opr = as_oop_opr(rax);
never@739	231	rdx_oop_opr = as_oop_opr(rdx);
never@739	232	rcx_oop_opr = as_oop_opr(rcx);
never@739	233
never@739	234	rsp_opr = as_pointer_opr(rsp);
never@739	235	rbp_opr = as_pointer_opr(rbp);
never@739	236
never@739	237	#ifdef _LP64
never@739	238	r8_oop_opr = as_oop_opr(r8);
never@739	239	r9_oop_opr = as_oop_opr(r9);
never@739	240	r11_oop_opr = as_oop_opr(r11);
never@739	241	r12_oop_opr = as_oop_opr(r12);
never@739	242	r13_oop_opr = as_oop_opr(r13);
never@739	243	r14_oop_opr = as_oop_opr(r14);
never@739	244	#endif // _LP64
never@739	245
duke@435	246	VMRegPair regs;
duke@435	247	BasicType sig_bt = T_OBJECT;
duke@435	248	SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true);
duke@435	249	receiver_opr = as_oop_opr(regs.first()->as_Register());
never@739	250
duke@435	251	}
duke@435	252
duke@435	253
duke@435	254	Address FrameMap::make_new_address(ByteSize sp_offset) const {
duke@435	255	// for rbp, based address use this:
duke@435	256	// return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
duke@435	257	return Address(rsp, in_bytes(sp_offset));
duke@435	258	}
duke@435	259
duke@435	260
duke@435	261	// ----------------mapping-----------------------
duke@435	262	// all mapping is based on rbp, addressing, except for simple leaf methods where we access
duke@435	263	// the locals rsp based (and no frame is built)
duke@435	264
duke@435	265
duke@435	266	// Frame for simple leaf methods (quick entries)
duke@435	267	//
duke@435	268	// +----------+
duke@435	269	// | ret addr | <- TOS
duke@435	270	// +----------+
duke@435	271	// | args |
duke@435	272	// | ...... |
duke@435	273
duke@435	274	// Frame for standard methods
duke@435	275	//
duke@435	276	// | .........| <- TOS
duke@435	277	// | locals |
duke@435	278	// +----------+
duke@435	279	// | old rbp, | <- EBP
duke@435	280	// +----------+
duke@435	281	// | ret addr |
duke@435	282	// +----------+
duke@435	283	// | args |
duke@435	284	// | .........|
duke@435	285
duke@435	286
duke@435	287	// For OopMaps, map a local variable or spill index to an VMRegImpl name.
duke@435	288	// This is the offset from sp() in the frame of the slot for the index,
duke@435	289	// skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
duke@435	290	//
duke@435	291	// framesize +
duke@435	292	// stack0 stack0 0 <- VMReg
duke@435	293	// | | <registers> |
duke@435	294	// ...........|..............|.............|
duke@435	295	// 0 1 2 3 x x 4 5 6 ... | <- local indices
duke@435	296	// ^ ^ sp() ( x x indicate link
duke@435	297	// | | and return addr)
duke@435	298	// arguments non-argument locals
duke@435	299
duke@435	300
duke@435	301	VMReg FrameMap::fpu_regname (int n) {
duke@435	302	// Return the OptoReg name for the fpu stack slot "n"
duke@435	303	// A spilled fpu stack slot comprises to two single-word OptoReg's.
duke@435	304	return as_FloatRegister(n)->as_VMReg();
duke@435	305	}
duke@435	306
duke@435	307	LIR_Opr FrameMap::stack_pointer() {
duke@435	308	return FrameMap::rsp_opr;
duke@435	309	}
duke@435	310
duke@435	311
duke@435	312	bool FrameMap::validate_frame() {
duke@435	313	return true;
duke@435	314	}