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src/cpu/sparc/vm/c1_FrameMap_sparc.cpp@a1980da045cc (annotated)

src/cpu/sparc/vm/c1_FrameMap_sparc.cpp

Fri, 07 Nov 2008 09:29:38 -0800

author

kvn

date

Fri, 07 Nov 2008 09:29:38 -0800

changeset 855

a1980da045cc

parent 435

a61af66fc99e

child 1162

6b2273dd6fa9

permissions

-rw-r--r--

6462850: generate biased locking code in C2 ideal graph
Summary: Inline biased locking code in C2 ideal graph during macro nodes expansion
Reviewed-by: never

duke@435	1	/*
duke@435	2	* Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	# include "incls/_precompiled.incl"
duke@435	26	# include "incls/_c1_FrameMap_sparc.cpp.incl"
duke@435	27
duke@435	28
duke@435	29	const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
duke@435	30
duke@435	31
duke@435	32	LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
duke@435	33	LIR_Opr opr = LIR_OprFact::illegalOpr;
duke@435	34	VMReg r_1 = reg->first();
duke@435	35	VMReg r_2 = reg->second();
duke@435	36	if (r_1->is_stack()) {
duke@435	37	// Convert stack slot to an SP offset
duke@435	38	// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
duke@435	39	// so we must add it in here.
duke@435	40	int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@435	41	opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
duke@435	42	} else if (r_1->is_Register()) {
duke@435	43	Register reg = r_1->as_Register();
duke@435	44	if (outgoing) {
duke@435	45	assert(!reg->is_in(), "should be using I regs");
duke@435	46	} else {
duke@435	47	assert(!reg->is_out(), "should be using O regs");
duke@435	48	}
duke@435	49	if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
duke@435	50	opr = as_long_opr(reg);
duke@435	51	} else if (type == T_OBJECT || type == T_ARRAY) {
duke@435	52	opr = as_oop_opr(reg);
duke@435	53	} else {
duke@435	54	opr = as_opr(reg);
duke@435	55	}
duke@435	56	} else if (r_1->is_FloatRegister()) {
duke@435	57	assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
duke@435	58	FloatRegister f = r_1->as_FloatRegister();
duke@435	59	if (type == T_DOUBLE) {
duke@435	60	opr = as_double_opr(f);
duke@435	61	} else {
duke@435	62	opr = as_float_opr(f);
duke@435	63	}
duke@435	64	}
duke@435	65	return opr;
duke@435	66	}
duke@435	67
duke@435	68	// FrameMap
duke@435	69	//--------------------------------------------------------
duke@435	70
duke@435	71	FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
duke@435	72
duke@435	73	// some useful constant RInfo's:
duke@435	74	LIR_Opr FrameMap::in_long_opr;
duke@435	75	LIR_Opr FrameMap::out_long_opr;
duke@435	76
duke@435	77	LIR_Opr FrameMap::F0_opr;
duke@435	78	LIR_Opr FrameMap::F0_double_opr;
duke@435	79
duke@435	80	LIR_Opr FrameMap::G0_opr;
duke@435	81	LIR_Opr FrameMap::G1_opr;
duke@435	82	LIR_Opr FrameMap::G2_opr;
duke@435	83	LIR_Opr FrameMap::G3_opr;
duke@435	84	LIR_Opr FrameMap::G4_opr;
duke@435	85	LIR_Opr FrameMap::G5_opr;
duke@435	86	LIR_Opr FrameMap::G6_opr;
duke@435	87	LIR_Opr FrameMap::G7_opr;
duke@435	88	LIR_Opr FrameMap::O0_opr;
duke@435	89	LIR_Opr FrameMap::O1_opr;
duke@435	90	LIR_Opr FrameMap::O2_opr;
duke@435	91	LIR_Opr FrameMap::O3_opr;
duke@435	92	LIR_Opr FrameMap::O4_opr;
duke@435	93	LIR_Opr FrameMap::O5_opr;
duke@435	94	LIR_Opr FrameMap::O6_opr;
duke@435	95	LIR_Opr FrameMap::O7_opr;
duke@435	96	LIR_Opr FrameMap::L0_opr;
duke@435	97	LIR_Opr FrameMap::L1_opr;
duke@435	98	LIR_Opr FrameMap::L2_opr;
duke@435	99	LIR_Opr FrameMap::L3_opr;
duke@435	100	LIR_Opr FrameMap::L4_opr;
duke@435	101	LIR_Opr FrameMap::L5_opr;
duke@435	102	LIR_Opr FrameMap::L6_opr;
duke@435	103	LIR_Opr FrameMap::L7_opr;
duke@435	104	LIR_Opr FrameMap::I0_opr;
duke@435	105	LIR_Opr FrameMap::I1_opr;
duke@435	106	LIR_Opr FrameMap::I2_opr;
duke@435	107	LIR_Opr FrameMap::I3_opr;
duke@435	108	LIR_Opr FrameMap::I4_opr;
duke@435	109	LIR_Opr FrameMap::I5_opr;
duke@435	110	LIR_Opr FrameMap::I6_opr;
duke@435	111	LIR_Opr FrameMap::I7_opr;
duke@435	112
duke@435	113	LIR_Opr FrameMap::G0_oop_opr;
duke@435	114	LIR_Opr FrameMap::G1_oop_opr;
duke@435	115	LIR_Opr FrameMap::G2_oop_opr;
duke@435	116	LIR_Opr FrameMap::G3_oop_opr;
duke@435	117	LIR_Opr FrameMap::G4_oop_opr;
duke@435	118	LIR_Opr FrameMap::G5_oop_opr;
duke@435	119	LIR_Opr FrameMap::G6_oop_opr;
duke@435	120	LIR_Opr FrameMap::G7_oop_opr;
duke@435	121	LIR_Opr FrameMap::O0_oop_opr;
duke@435	122	LIR_Opr FrameMap::O1_oop_opr;
duke@435	123	LIR_Opr FrameMap::O2_oop_opr;
duke@435	124	LIR_Opr FrameMap::O3_oop_opr;
duke@435	125	LIR_Opr FrameMap::O4_oop_opr;
duke@435	126	LIR_Opr FrameMap::O5_oop_opr;
duke@435	127	LIR_Opr FrameMap::O6_oop_opr;
duke@435	128	LIR_Opr FrameMap::O7_oop_opr;
duke@435	129	LIR_Opr FrameMap::L0_oop_opr;
duke@435	130	LIR_Opr FrameMap::L1_oop_opr;
duke@435	131	LIR_Opr FrameMap::L2_oop_opr;
duke@435	132	LIR_Opr FrameMap::L3_oop_opr;
duke@435	133	LIR_Opr FrameMap::L4_oop_opr;
duke@435	134	LIR_Opr FrameMap::L5_oop_opr;
duke@435	135	LIR_Opr FrameMap::L6_oop_opr;
duke@435	136	LIR_Opr FrameMap::L7_oop_opr;
duke@435	137	LIR_Opr FrameMap::I0_oop_opr;
duke@435	138	LIR_Opr FrameMap::I1_oop_opr;
duke@435	139	LIR_Opr FrameMap::I2_oop_opr;
duke@435	140	LIR_Opr FrameMap::I3_oop_opr;
duke@435	141	LIR_Opr FrameMap::I4_oop_opr;
duke@435	142	LIR_Opr FrameMap::I5_oop_opr;
duke@435	143	LIR_Opr FrameMap::I6_oop_opr;
duke@435	144	LIR_Opr FrameMap::I7_oop_opr;
duke@435	145
duke@435	146	LIR_Opr FrameMap::SP_opr;
duke@435	147	LIR_Opr FrameMap::FP_opr;
duke@435	148
duke@435	149	LIR_Opr FrameMap::Oexception_opr;
duke@435	150	LIR_Opr FrameMap::Oissuing_pc_opr;
duke@435	151
duke@435	152	LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
duke@435	153	LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
duke@435	154
duke@435	155
duke@435	156	FloatRegister FrameMap::nr2floatreg (int rnr) {
duke@435	157	assert(_init_done, "tables not initialized");
duke@435	158	debug_only(fpu_range_check(rnr);)
duke@435	159	return _fpu_regs[rnr];
duke@435	160	}
duke@435	161
duke@435	162
duke@435	163	// returns true if reg could be smashed by a callee.
duke@435	164	bool FrameMap::is_caller_save_register (LIR_Opr reg) {
duke@435	165	if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
duke@435	166	if (reg->is_double_cpu()) {
duke@435	167	return is_caller_save_register(reg->as_register_lo()) ||
duke@435	168	is_caller_save_register(reg->as_register_hi());
duke@435	169	}
duke@435	170	return is_caller_save_register(reg->as_register());
duke@435	171	}
duke@435	172
duke@435	173
duke@435	174	NEEDS_CLEANUP // once the new calling convention is enabled, we no
duke@435	175	// longer need to treat I5, I4 and L0 specially
duke@435	176	// Because the interpreter destroys caller's I5, I4 and L0,
duke@435	177	// we must spill them before doing a Java call as we may land in
duke@435	178	// interpreter.
duke@435	179	bool FrameMap::is_caller_save_register (Register r) {
duke@435	180	return (r->is_global() && (r != G0)) || r->is_out();
duke@435	181	}
duke@435	182
duke@435	183
duke@435	184	void FrameMap::init () {
duke@435	185	if (_init_done) return;
duke@435	186
duke@435	187	int i=0;
duke@435	188	// Register usage:
duke@435	189	// O6: sp
duke@435	190	// I6: fp
duke@435	191	// I7: return address
duke@435	192	// G0: zero
duke@435	193	// G2: thread
duke@435	194	// G7: not available
duke@435	195	// G6: not available
duke@435	196	/* 0 */ map_register(i++, L0);
duke@435	197	/* 1 */ map_register(i++, L1);
duke@435	198	/* 2 */ map_register(i++, L2);
duke@435	199	/* 3 */ map_register(i++, L3);
duke@435	200	/* 4 */ map_register(i++, L4);
duke@435	201	/* 5 */ map_register(i++, L5);
duke@435	202	/* 6 */ map_register(i++, L6);
duke@435	203	/* 7 */ map_register(i++, L7);
duke@435	204
duke@435	205	/* 8 */ map_register(i++, I0);
duke@435	206	/* 9 */ map_register(i++, I1);
duke@435	207	/* 10 */ map_register(i++, I2);
duke@435	208	/* 11 */ map_register(i++, I3);
duke@435	209	/* 12 */ map_register(i++, I4);
duke@435	210	/* 13 */ map_register(i++, I5);
duke@435	211	/* 14 */ map_register(i++, O0);
duke@435	212	/* 15 */ map_register(i++, O1);
duke@435	213	/* 16 */ map_register(i++, O2);
duke@435	214	/* 17 */ map_register(i++, O3);
duke@435	215	/* 18 */ map_register(i++, O4);
duke@435	216	/* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs)
duke@435	217	/* 20 */ map_register(i++, G1);
duke@435	218	/* 21 */ map_register(i++, G3);
duke@435	219	/* 22 */ map_register(i++, G4);
duke@435	220	/* 23 */ map_register(i++, G5);
duke@435	221	/* 24 */ map_register(i++, G0);
duke@435	222
duke@435	223	// the following registers are not normally available
duke@435	224	/* 25 */ map_register(i++, O7);
duke@435	225	/* 26 */ map_register(i++, G2);
duke@435	226	/* 27 */ map_register(i++, O6);
duke@435	227	/* 28 */ map_register(i++, I6);
duke@435	228	/* 29 */ map_register(i++, I7);
duke@435	229	/* 30 */ map_register(i++, G6);
duke@435	230	/* 31 */ map_register(i++, G7);
duke@435	231	assert(i == nof_cpu_regs, "number of CPU registers");
duke@435	232
duke@435	233	for (i = 0; i < nof_fpu_regs; i++) {
duke@435	234	_fpu_regs[i] = as_FloatRegister(i);
duke@435	235	}
duke@435	236
duke@435	237	_init_done = true;
duke@435	238
duke@435	239	in_long_opr = as_long_opr(I0);
duke@435	240	out_long_opr = as_long_opr(O0);
duke@435	241
duke@435	242	G0_opr = as_opr(G0);
duke@435	243	G1_opr = as_opr(G1);
duke@435	244	G2_opr = as_opr(G2);
duke@435	245	G3_opr = as_opr(G3);
duke@435	246	G4_opr = as_opr(G4);
duke@435	247	G5_opr = as_opr(G5);
duke@435	248	G6_opr = as_opr(G6);
duke@435	249	G7_opr = as_opr(G7);
duke@435	250	O0_opr = as_opr(O0);
duke@435	251	O1_opr = as_opr(O1);
duke@435	252	O2_opr = as_opr(O2);
duke@435	253	O3_opr = as_opr(O3);
duke@435	254	O4_opr = as_opr(O4);
duke@435	255	O5_opr = as_opr(O5);
duke@435	256	O6_opr = as_opr(O6);
duke@435	257	O7_opr = as_opr(O7);
duke@435	258	L0_opr = as_opr(L0);
duke@435	259	L1_opr = as_opr(L1);
duke@435	260	L2_opr = as_opr(L2);
duke@435	261	L3_opr = as_opr(L3);
duke@435	262	L4_opr = as_opr(L4);
duke@435	263	L5_opr = as_opr(L5);
duke@435	264	L6_opr = as_opr(L6);
duke@435	265	L7_opr = as_opr(L7);
duke@435	266	I0_opr = as_opr(I0);
duke@435	267	I1_opr = as_opr(I1);
duke@435	268	I2_opr = as_opr(I2);
duke@435	269	I3_opr = as_opr(I3);
duke@435	270	I4_opr = as_opr(I4);
duke@435	271	I5_opr = as_opr(I5);
duke@435	272	I6_opr = as_opr(I6);
duke@435	273	I7_opr = as_opr(I7);
duke@435	274
duke@435	275	G0_oop_opr = as_oop_opr(G0);
duke@435	276	G1_oop_opr = as_oop_opr(G1);
duke@435	277	G2_oop_opr = as_oop_opr(G2);
duke@435	278	G3_oop_opr = as_oop_opr(G3);
duke@435	279	G4_oop_opr = as_oop_opr(G4);
duke@435	280	G5_oop_opr = as_oop_opr(G5);
duke@435	281	G6_oop_opr = as_oop_opr(G6);
duke@435	282	G7_oop_opr = as_oop_opr(G7);
duke@435	283	O0_oop_opr = as_oop_opr(O0);
duke@435	284	O1_oop_opr = as_oop_opr(O1);
duke@435	285	O2_oop_opr = as_oop_opr(O2);
duke@435	286	O3_oop_opr = as_oop_opr(O3);
duke@435	287	O4_oop_opr = as_oop_opr(O4);
duke@435	288	O5_oop_opr = as_oop_opr(O5);
duke@435	289	O6_oop_opr = as_oop_opr(O6);
duke@435	290	O7_oop_opr = as_oop_opr(O7);
duke@435	291	L0_oop_opr = as_oop_opr(L0);
duke@435	292	L1_oop_opr = as_oop_opr(L1);
duke@435	293	L2_oop_opr = as_oop_opr(L2);
duke@435	294	L3_oop_opr = as_oop_opr(L3);
duke@435	295	L4_oop_opr = as_oop_opr(L4);
duke@435	296	L5_oop_opr = as_oop_opr(L5);
duke@435	297	L6_oop_opr = as_oop_opr(L6);
duke@435	298	L7_oop_opr = as_oop_opr(L7);
duke@435	299	I0_oop_opr = as_oop_opr(I0);
duke@435	300	I1_oop_opr = as_oop_opr(I1);
duke@435	301	I2_oop_opr = as_oop_opr(I2);
duke@435	302	I3_oop_opr = as_oop_opr(I3);
duke@435	303	I4_oop_opr = as_oop_opr(I4);
duke@435	304	I5_oop_opr = as_oop_opr(I5);
duke@435	305	I6_oop_opr = as_oop_opr(I6);
duke@435	306	I7_oop_opr = as_oop_opr(I7);
duke@435	307
duke@435	308	FP_opr = as_pointer_opr(FP);
duke@435	309	SP_opr = as_pointer_opr(SP);
duke@435	310
duke@435	311	F0_opr = as_float_opr(F0);
duke@435	312	F0_double_opr = as_double_opr(F0);
duke@435	313
duke@435	314	Oexception_opr = as_oop_opr(Oexception);
duke@435	315	Oissuing_pc_opr = as_opr(Oissuing_pc);
duke@435	316
duke@435	317	_caller_save_cpu_regs[0] = FrameMap::O0_opr;
duke@435	318	_caller_save_cpu_regs[1] = FrameMap::O1_opr;
duke@435	319	_caller_save_cpu_regs[2] = FrameMap::O2_opr;
duke@435	320	_caller_save_cpu_regs[3] = FrameMap::O3_opr;
duke@435	321	_caller_save_cpu_regs[4] = FrameMap::O4_opr;
duke@435	322	_caller_save_cpu_regs[5] = FrameMap::O5_opr;
duke@435	323	for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
duke@435	324	_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
duke@435	325	}
duke@435	326	}
duke@435	327
duke@435	328
duke@435	329	Address FrameMap::make_new_address(ByteSize sp_offset) const {
duke@435	330	return Address(SP, 0, STACK_BIAS + in_bytes(sp_offset));
duke@435	331	}
duke@435	332
duke@435	333
duke@435	334	VMReg FrameMap::fpu_regname (int n) {
duke@435	335	return as_FloatRegister(n)->as_VMReg();
duke@435	336	}
duke@435	337
duke@435	338
duke@435	339	LIR_Opr FrameMap::stack_pointer() {
duke@435	340	return SP_opr;
duke@435	341	}
duke@435	342
duke@435	343
duke@435	344	bool FrameMap::validate_frame() {
duke@435	345	int max_offset = in_bytes(framesize_in_bytes());
duke@435	346	int java_index = 0;
duke@435	347	for (int i = 0; i < _incoming_arguments->length(); i++) {
duke@435	348	LIR_Opr opr = _incoming_arguments->at(i);
duke@435	349	if (opr->is_stack()) {
duke@435	350	max_offset = MAX2(_argument_locations->at(java_index), max_offset);
duke@435	351	}
duke@435	352	java_index += type2size[opr->type()];
duke@435	353	}
duke@435	354	return Assembler::is_simm13(max_offset + STACK_BIAS);
duke@435	355	}