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src/share/vm/c1/c1_LIRAssembler.hpp@9f4457a14b58 (annotated)

src/share/vm/c1/c1_LIRAssembler.hpp

Wed, 09 Apr 2008 15:10:22 -0700

author

rasbold

date

Wed, 09 Apr 2008 15:10:22 -0700

changeset 544

9f4457a14b58

parent 435

a61af66fc99e

child 739

dc7f315e41f7

child 777

37f87013dfd8

permissions

-rw-r--r--

Merge

duke@435	1	/*
duke@435	2	* Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	class Compilation;
duke@435	26	class ScopeValue;
duke@435	27
duke@435	28	class LIR_Assembler: public CompilationResourceObj {
duke@435	29	private:
duke@435	30	C1_MacroAssembler* _masm;
duke@435	31	CodeStubList* _slow_case_stubs;
duke@435	32
duke@435	33	Compilation* _compilation;
duke@435	34	FrameMap* _frame_map;
duke@435	35	BlockBegin* _current_block;
duke@435	36
duke@435	37	Instruction* _pending_non_safepoint;
duke@435	38	int _pending_non_safepoint_offset;
duke@435	39
duke@435	40	#ifdef ASSERT
duke@435	41	BlockList _branch_target_blocks;
duke@435	42	void check_no_unbound_labels();
duke@435	43	#endif
duke@435	44
duke@435	45	FrameMap* frame_map() const { return _frame_map; }
duke@435	46
duke@435	47	void set_current_block(BlockBegin* b) { _current_block = b; }
duke@435	48	BlockBegin* current_block() const { return _current_block; }
duke@435	49
duke@435	50	// non-safepoint debug info management
duke@435	51	void flush_debug_info(int before_pc_offset) {
duke@435	52	if (_pending_non_safepoint != NULL) {
duke@435	53	if (_pending_non_safepoint_offset < before_pc_offset)
duke@435	54	record_non_safepoint_debug_info();
duke@435	55	_pending_non_safepoint = NULL;
duke@435	56	}
duke@435	57	}
duke@435	58	void process_debug_info(LIR_Op* op);
duke@435	59	void record_non_safepoint_debug_info();
duke@435	60
duke@435	61	// unified bailout support
duke@435	62	void bailout(const char* msg) const { compilation()->bailout(msg); }
duke@435	63	bool bailed_out() const { return compilation()->bailed_out(); }
duke@435	64
duke@435	65	// code emission patterns and accessors
duke@435	66	void check_codespace();
duke@435	67	bool needs_icache(ciMethod* method) const;
duke@435	68
duke@435	69	// returns offset of icache check
duke@435	70	int check_icache();
duke@435	71
duke@435	72	void jobject2reg(jobject o, Register reg);
duke@435	73	void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
duke@435	74
duke@435	75	void emit_stubs(CodeStubList* stub_list);
duke@435	76
duke@435	77	// addresses
duke@435	78	static Address as_Address(LIR_Address* addr);
duke@435	79	static Address as_Address_lo(LIR_Address* addr);
duke@435	80	static Address as_Address_hi(LIR_Address* addr);
duke@435	81
duke@435	82	// debug information
duke@435	83	void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
duke@435	84	void add_debug_info_for_branch(CodeEmitInfo* info);
duke@435	85	void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
duke@435	86	void add_debug_info_for_div0_here(CodeEmitInfo* info);
duke@435	87	void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
duke@435	88	void add_debug_info_for_null_check_here(CodeEmitInfo* info);
duke@435	89
duke@435	90	void set_24bit_FPU();
duke@435	91	void reset_FPU();
duke@435	92	void fpop();
duke@435	93	void fxch(int i);
duke@435	94	void fld(int i);
duke@435	95	void ffree(int i);
duke@435	96
duke@435	97	void breakpoint();
duke@435	98	void push(LIR_Opr opr);
duke@435	99	void pop(LIR_Opr opr);
duke@435	100
duke@435	101	// patching
duke@435	102	void append_patching_stub(PatchingStub* stub);
duke@435	103	void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
duke@435	104
duke@435	105	void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
duke@435	106
duke@435	107	public:
duke@435	108	LIR_Assembler(Compilation* c);
duke@435	109	~LIR_Assembler();
duke@435	110	C1_MacroAssembler* masm() const { return _masm; }
duke@435	111	Compilation* compilation() const { return _compilation; }
duke@435	112	ciMethod* method() const { return compilation()->method(); }
duke@435	113
duke@435	114	CodeOffsets* offsets() const { return _compilation->offsets(); }
duke@435	115	int code_offset() const;
duke@435	116	address pc() const;
duke@435	117
duke@435	118	int initial_frame_size_in_bytes();
duke@435	119
duke@435	120	// test for constants which can be encoded directly in instructions
duke@435	121	static bool is_small_constant(LIR_Opr opr);
duke@435	122
duke@435	123	static LIR_Opr receiverOpr();
duke@435	124	static LIR_Opr incomingReceiverOpr();
duke@435	125	static LIR_Opr osrBufferPointer();
duke@435	126
duke@435	127	// stubs
duke@435	128	void emit_slow_case_stubs();
duke@435	129	void emit_static_call_stub();
duke@435	130	void emit_code_stub(CodeStub* op);
duke@435	131	void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
duke@435	132
duke@435	133	// code patterns
duke@435	134	void emit_exception_handler();
duke@435	135	void emit_exception_entries(ExceptionInfoList* info_list);
duke@435	136	void emit_deopt_handler();
duke@435	137
duke@435	138	void emit_code(BlockList* hir);
duke@435	139	void emit_block(BlockBegin* block);
duke@435	140	void emit_lir_list(LIR_List* list);
duke@435	141
duke@435	142	// any last minute peephole optimizations are performed here. In
duke@435	143	// particular sparc uses this for delay slot filling.
duke@435	144	void peephole(LIR_List* list);
duke@435	145
duke@435	146	void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);
duke@435	147
duke@435	148	void return_op(LIR_Opr result);
duke@435	149
duke@435	150	// returns offset of poll instruction
duke@435	151	int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
duke@435	152
duke@435	153	void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
duke@435	154	void const2stack(LIR_Opr src, LIR_Opr dest);
duke@435	155	void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info);
duke@435	156	void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
duke@435	157	void reg2reg (LIR_Opr src, LIR_Opr dest);
duke@435	158	void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned);
duke@435	159	void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
duke@435	160	void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
duke@435	161	void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
duke@435	162	LIR_PatchCode patch_code = lir_patch_none,
duke@435	163	CodeEmitInfo* info = NULL, bool unaligned = false);
duke@435	164
duke@435	165	void prefetchr (LIR_Opr src);
duke@435	166	void prefetchw (LIR_Opr src);
duke@435	167
duke@435	168	void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
duke@435	169	void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
duke@435	170
duke@435	171	void move_regs(Register from_reg, Register to_reg);
duke@435	172	void swap_reg(Register a, Register b);
duke@435	173
duke@435	174	void emit_op0(LIR_Op0* op);
duke@435	175	void emit_op1(LIR_Op1* op);
duke@435	176	void emit_op2(LIR_Op2* op);
duke@435	177	void emit_op3(LIR_Op3* op);
duke@435	178	void emit_opBranch(LIR_OpBranch* op);
duke@435	179	void emit_opLabel(LIR_OpLabel* op);
duke@435	180	void emit_arraycopy(LIR_OpArrayCopy* op);
duke@435	181	void emit_opConvert(LIR_OpConvert* op);
duke@435	182	void emit_alloc_obj(LIR_OpAllocObj* op);
duke@435	183	void emit_alloc_array(LIR_OpAllocArray* op);
duke@435	184	void emit_opTypeCheck(LIR_OpTypeCheck* op);
duke@435	185	void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
duke@435	186	void emit_lock(LIR_OpLock* op);
duke@435	187	void emit_call(LIR_OpJavaCall* op);
duke@435	188	void emit_rtcall(LIR_OpRTCall* op);
duke@435	189	void emit_profile_call(LIR_OpProfileCall* op);
duke@435	190	void emit_delay(LIR_OpDelay* op);
duke@435	191
duke@435	192	void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
duke@435	193	void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
duke@435	194	void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
duke@435	195
duke@435	196	void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
duke@435	197
duke@435	198	void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
duke@435	199	void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
duke@435	200	LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned);
duke@435	201	void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
duke@435	202	void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
duke@435	203	void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
duke@435	204	void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result);
duke@435	205
duke@435	206	void ic_call(address destination, CodeEmitInfo* info);
duke@435	207	void vtable_call(int vtable_offset, CodeEmitInfo* info);
duke@435	208	void call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info);
duke@435	209
duke@435	210	void osr_entry();
duke@435	211
duke@435	212	void build_frame();
duke@435	213
duke@435	214	void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind);
duke@435	215	void monitor_address(int monitor_ix, LIR_Opr dst);
duke@435	216
duke@435	217	void align_backward_branch_target();
duke@435	218	void align_call(LIR_Code code);
duke@435	219
duke@435	220	void negate(LIR_Opr left, LIR_Opr dest);
duke@435	221	void leal(LIR_Opr left, LIR_Opr dest);
duke@435	222
duke@435	223	void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
duke@435	224
duke@435	225	void membar();
duke@435	226	void membar_acquire();
duke@435	227	void membar_release();
duke@435	228	void get_thread(LIR_Opr result);
duke@435	229
duke@435	230	void verify_oop_map(CodeEmitInfo* info);
duke@435	231
duke@435	232	#include "incls/_c1_LIRAssembler_pd.hpp.incl"
duke@435	233	};