Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/zero/vm/icache_zero.hpp@8c95980d0b66 (annotated)
src/cpu/zero/vm/icache_zero.hpp
Sat, 07 Nov 2020 10:30:02 +0800
- author
- aoqi
- date
- Sat, 07 Nov 2020 10:30:02 +0800
- changeset 10026
- 8c95980d0b66
- parent 6876
- 710a3c8b516e
- permissions
- -rw-r--r--
Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f
| aoqi@0 | 1 | /* |
| aoqi@0 | 2 | * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@0 | 3 | * Copyright 2007, 2009 Red Hat, Inc. |
| aoqi@0 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@0 | 5 | * |
| aoqi@0 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@0 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@0 | 8 | * published by the Free Software Foundation. |
| aoqi@0 | 9 | * |
| aoqi@0 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@0 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@0 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@0 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@0 | 14 | * accompanied this code). |
| aoqi@0 | 15 | * |
| aoqi@0 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@0 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@0 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@0 | 19 | * |
| aoqi@0 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@0 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@0 | 22 | * questions. |
| aoqi@0 | 23 | * |
| aoqi@0 | 24 | */ |
| aoqi@0 | 25 | |
| aoqi@0 | 26 | #ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP |
| aoqi@0 | 27 | #define CPU_ZERO_VM_ICACHE_ZERO_HPP |
| aoqi@0 | 28 | |
| aoqi@0 | 29 | // Interface for updating the instruction cache. Whenever the VM |
| aoqi@0 | 30 | // modifies code, part of the processor instruction cache potentially |
| aoqi@0 | 31 | // has to be flushed. This implementation is empty: Zero never deals |
| aoqi@0 | 32 | // with code, and LLVM handles cache flushing for Shark. |
| aoqi@0 | 33 | |
| aoqi@0 | 34 | class ICache : public AbstractICache { |
| aoqi@0 | 35 | public: |
| aoqi@0 | 36 | static void initialize() {} |
| aoqi@0 | 37 | static void invalidate_word(address addr) {} |
| aoqi@0 | 38 | static void invalidate_range(address start, int nbytes) {} |
| aoqi@0 | 39 | }; |
| aoqi@0 | 40 | |
| aoqi@0 | 41 | #endif // CPU_ZERO_VM_ICACHE_ZERO_HPP |
