Sat, 07 Nov 2020 10:30:02 +0800
Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@0 | 25 | #ifndef CPU_X86_VM_VMREG_X86_INLINE_HPP |
aoqi@0 | 26 | #define CPU_X86_VM_VMREG_X86_INLINE_HPP |
aoqi@0 | 27 | |
aoqi@0 | 28 | inline VMReg RegisterImpl::as_VMReg() { |
aoqi@0 | 29 | if( this==noreg ) return VMRegImpl::Bad(); |
aoqi@0 | 30 | #ifdef AMD64 |
aoqi@0 | 31 | return VMRegImpl::as_VMReg(encoding() << 1 ); |
aoqi@0 | 32 | #else |
aoqi@0 | 33 | return VMRegImpl::as_VMReg(encoding() ); |
aoqi@0 | 34 | #endif // AMD64 |
aoqi@0 | 35 | } |
aoqi@0 | 36 | |
aoqi@0 | 37 | inline VMReg FloatRegisterImpl::as_VMReg() { |
aoqi@0 | 38 | return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); |
aoqi@0 | 39 | } |
aoqi@0 | 40 | |
aoqi@0 | 41 | inline VMReg XMMRegisterImpl::as_VMReg() { |
aoqi@0 | 42 | return VMRegImpl::as_VMReg((encoding() << 3) + ConcreteRegisterImpl::max_fpr); |
aoqi@0 | 43 | } |
aoqi@0 | 44 | |
aoqi@0 | 45 | |
aoqi@0 | 46 | inline bool VMRegImpl::is_Register() { |
aoqi@0 | 47 | return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; |
aoqi@0 | 48 | } |
aoqi@0 | 49 | |
aoqi@0 | 50 | inline bool VMRegImpl::is_FloatRegister() { |
aoqi@0 | 51 | return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; |
aoqi@0 | 52 | } |
aoqi@0 | 53 | |
aoqi@0 | 54 | inline bool VMRegImpl::is_XMMRegister() { |
aoqi@0 | 55 | return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_xmm; |
aoqi@0 | 56 | } |
aoqi@0 | 57 | |
aoqi@0 | 58 | inline Register VMRegImpl::as_Register() { |
aoqi@0 | 59 | |
aoqi@0 | 60 | assert( is_Register(), "must be"); |
aoqi@0 | 61 | // Yuk |
aoqi@0 | 62 | #ifdef AMD64 |
aoqi@0 | 63 | return ::as_Register(value() >> 1); |
aoqi@0 | 64 | #else |
aoqi@0 | 65 | return ::as_Register(value()); |
aoqi@0 | 66 | #endif // AMD64 |
aoqi@0 | 67 | } |
aoqi@0 | 68 | |
aoqi@0 | 69 | inline FloatRegister VMRegImpl::as_FloatRegister() { |
aoqi@0 | 70 | assert( is_FloatRegister() && is_even(value()), "must be" ); |
aoqi@0 | 71 | // Yuk |
aoqi@0 | 72 | return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); |
aoqi@0 | 73 | } |
aoqi@0 | 74 | |
aoqi@0 | 75 | inline XMMRegister VMRegImpl::as_XMMRegister() { |
aoqi@0 | 76 | assert( is_XMMRegister() && is_even(value()), "must be" ); |
aoqi@0 | 77 | // Yuk |
aoqi@0 | 78 | return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 3); |
aoqi@0 | 79 | } |
aoqi@0 | 80 | |
aoqi@0 | 81 | inline bool VMRegImpl::is_concrete() { |
aoqi@0 | 82 | assert(is_reg(), "must be"); |
aoqi@0 | 83 | #ifndef AMD64 |
aoqi@0 | 84 | if (is_Register()) return true; |
aoqi@0 | 85 | #endif // AMD64 |
aoqi@0 | 86 | return is_even(value()); |
aoqi@0 | 87 | } |
aoqi@0 | 88 | |
aoqi@0 | 89 | #endif // CPU_X86_VM_VMREG_X86_INLINE_HPP |