Sat, 07 Nov 2020 10:30:02 +0800
Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@0 | 25 | #ifndef CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP |
aoqi@0 | 26 | #define CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP |
aoqi@0 | 27 | |
aoqi@0 | 28 | #include "asm/assembler.inline.hpp" |
aoqi@0 | 29 | #include "asm/codeBuffer.hpp" |
aoqi@0 | 30 | #include "code/codeCache.hpp" |
aoqi@0 | 31 | |
aoqi@0 | 32 | #ifndef _LP64 |
aoqi@0 | 33 | inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; } |
aoqi@0 | 34 | inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; } |
aoqi@0 | 35 | |
aoqi@0 | 36 | inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; } |
aoqi@0 | 37 | inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; } |
aoqi@0 | 38 | |
aoqi@0 | 39 | inline void Assembler::prefix(Register reg) {} |
aoqi@0 | 40 | inline void Assembler::prefix(Address adr) {} |
aoqi@0 | 41 | inline void Assembler::prefixq(Address adr) {} |
aoqi@0 | 42 | |
aoqi@0 | 43 | inline void Assembler::prefix(Address adr, Register reg, bool byteinst) {} |
aoqi@0 | 44 | inline void Assembler::prefixq(Address adr, Register reg) {} |
aoqi@0 | 45 | |
aoqi@0 | 46 | inline void Assembler::prefix(Address adr, XMMRegister reg) {} |
aoqi@0 | 47 | inline void Assembler::prefixq(Address adr, XMMRegister reg) {} |
aoqi@0 | 48 | #endif // _LP64 |
aoqi@0 | 49 | |
aoqi@0 | 50 | #endif // CPU_X86_VM_ASSEMBLER_X86_INLINE_HPP |