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src/cpu/sparc/vm/assembler_sparc.hpp@7ae4e26cb1e0 (annotated)

src/cpu/sparc/vm/assembler_sparc.hpp

Thu, 12 Oct 2017 21:27:07 +0800

author

aoqi

date

Thu, 12 Oct 2017 21:27:07 +0800

changeset 7535

7ae4e26cb1e0

parent 7027

b20a35eae442

parent 6876

710a3c8b516e

child 9806

758c07667682

permissions

-rw-r--r--

merge

aoqi@0	1	/*
aoqi@0	2	* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@0	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0	4	*
aoqi@0	5	* This code is free software; you can redistribute it and/or modify it
aoqi@0	6	* under the terms of the GNU General Public License version 2 only, as
aoqi@0	7	* published by the Free Software Foundation.
aoqi@0	8	*
aoqi@0	9	* This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0	12	* version 2 for more details (a copy is included in the LICENSE file that
aoqi@0	13	* accompanied this code).
aoqi@0	14	*
aoqi@0	15	* You should have received a copy of the GNU General Public License version
aoqi@0	16	* 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0	18	*
aoqi@0	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0	20	* or visit www.oracle.com if you need additional information or have any
aoqi@0	21	* questions.
aoqi@0	22	*
aoqi@0	23	*/
aoqi@0	24
aoqi@0	25	#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
aoqi@0	26	#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
aoqi@0	27
aoqi@0	28	#include "asm/register.hpp"
aoqi@0	29
aoqi@0	30	// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
aoqi@0	31	// level; i.e., what you write
aoqi@0	32	// is what you get. The Assembler is generating code into a CodeBuffer.
aoqi@0	33
aoqi@0	34	class Assembler : public AbstractAssembler {
aoqi@0	35	friend class AbstractAssembler;
aoqi@0	36	friend class AddressLiteral;
aoqi@0	37
aoqi@0	38	// code patchers need various routines like inv_wdisp()
aoqi@0	39	friend class NativeInstruction;
aoqi@0	40	friend class NativeGeneralJump;
aoqi@0	41	friend class Relocation;
aoqi@0	42	friend class Label;
aoqi@0	43
aoqi@0	44	public:
aoqi@0	45	// op carries format info; see page 62 & 267
aoqi@0	46
aoqi@0	47	enum ops {
aoqi@0	48	call_op = 1, // fmt 1
aoqi@0	49	branch_op = 0, // also sethi (fmt2)
aoqi@0	50	arith_op = 2, // fmt 3, arith & misc
aoqi@0	51	ldst_op = 3 // fmt 3, load/store
aoqi@0	52	};
aoqi@0	53
aoqi@0	54	enum op2s {
aoqi@0	55	bpr_op2 = 3,
aoqi@0	56	fb_op2 = 6,
aoqi@0	57	fbp_op2 = 5,
aoqi@0	58	br_op2 = 2,
aoqi@0	59	bp_op2 = 1,
aoqi@0	60	sethi_op2 = 4
aoqi@0	61	};
aoqi@0	62
aoqi@0	63	enum op3s {
aoqi@0	64	// selected op3s
aoqi@0	65	add_op3 = 0x00,
aoqi@0	66	and_op3 = 0x01,
aoqi@0	67	or_op3 = 0x02,
aoqi@0	68	xor_op3 = 0x03,
aoqi@0	69	sub_op3 = 0x04,
aoqi@0	70	andn_op3 = 0x05,
aoqi@0	71	orn_op3 = 0x06,
aoqi@0	72	xnor_op3 = 0x07,
aoqi@0	73	addc_op3 = 0x08,
aoqi@0	74	mulx_op3 = 0x09,
aoqi@0	75	umul_op3 = 0x0a,
aoqi@0	76	smul_op3 = 0x0b,
aoqi@0	77	subc_op3 = 0x0c,
aoqi@0	78	udivx_op3 = 0x0d,
aoqi@0	79	udiv_op3 = 0x0e,
aoqi@0	80	sdiv_op3 = 0x0f,
aoqi@0	81
aoqi@0	82	addcc_op3 = 0x10,
aoqi@0	83	andcc_op3 = 0x11,
aoqi@0	84	orcc_op3 = 0x12,
aoqi@0	85	xorcc_op3 = 0x13,
aoqi@0	86	subcc_op3 = 0x14,
aoqi@0	87	andncc_op3 = 0x15,
aoqi@0	88	orncc_op3 = 0x16,
aoqi@0	89	xnorcc_op3 = 0x17,
aoqi@0	90	addccc_op3 = 0x18,
aoqi@0	91	aes4_op3 = 0x19,
aoqi@0	92	umulcc_op3 = 0x1a,
aoqi@0	93	smulcc_op3 = 0x1b,
aoqi@0	94	subccc_op3 = 0x1c,
aoqi@0	95	udivcc_op3 = 0x1e,
aoqi@0	96	sdivcc_op3 = 0x1f,
aoqi@0	97
aoqi@0	98	taddcc_op3 = 0x20,
aoqi@0	99	tsubcc_op3 = 0x21,
aoqi@0	100	taddcctv_op3 = 0x22,
aoqi@0	101	tsubcctv_op3 = 0x23,
aoqi@0	102	mulscc_op3 = 0x24,
aoqi@0	103	sll_op3 = 0x25,
aoqi@0	104	sllx_op3 = 0x25,
aoqi@0	105	srl_op3 = 0x26,
aoqi@0	106	srlx_op3 = 0x26,
aoqi@0	107	sra_op3 = 0x27,
aoqi@0	108	srax_op3 = 0x27,
aoqi@0	109	rdreg_op3 = 0x28,
aoqi@0	110	membar_op3 = 0x28,
aoqi@0	111
aoqi@0	112	flushw_op3 = 0x2b,
aoqi@0	113	movcc_op3 = 0x2c,
aoqi@0	114	sdivx_op3 = 0x2d,
aoqi@0	115	popc_op3 = 0x2e,
aoqi@0	116	movr_op3 = 0x2f,
aoqi@0	117
aoqi@0	118	sir_op3 = 0x30,
aoqi@0	119	wrreg_op3 = 0x30,
aoqi@0	120	saved_op3 = 0x31,
aoqi@0	121
aoqi@0	122	fpop1_op3 = 0x34,
aoqi@0	123	fpop2_op3 = 0x35,
aoqi@0	124	impdep1_op3 = 0x36,
aoqi@0	125	aes3_op3 = 0x36,
kvn@7027	126	sha_op3 = 0x36,
aoqi@0	127	alignaddr_op3 = 0x36,
aoqi@0	128	faligndata_op3 = 0x36,
aoqi@0	129	flog3_op3 = 0x36,
aoqi@0	130	edge_op3 = 0x36,
aoqi@0	131	fsrc_op3 = 0x36,
aoqi@0	132	impdep2_op3 = 0x37,
aoqi@0	133	stpartialf_op3 = 0x37,
aoqi@0	134	jmpl_op3 = 0x38,
aoqi@0	135	rett_op3 = 0x39,
aoqi@0	136	trap_op3 = 0x3a,
aoqi@0	137	flush_op3 = 0x3b,
aoqi@0	138	save_op3 = 0x3c,
aoqi@0	139	restore_op3 = 0x3d,
aoqi@0	140	done_op3 = 0x3e,
aoqi@0	141	retry_op3 = 0x3e,
aoqi@0	142
aoqi@0	143	lduw_op3 = 0x00,
aoqi@0	144	ldub_op3 = 0x01,
aoqi@0	145	lduh_op3 = 0x02,
aoqi@0	146	ldd_op3 = 0x03,
aoqi@0	147	stw_op3 = 0x04,
aoqi@0	148	stb_op3 = 0x05,
aoqi@0	149	sth_op3 = 0x06,
aoqi@0	150	std_op3 = 0x07,
aoqi@0	151	ldsw_op3 = 0x08,
aoqi@0	152	ldsb_op3 = 0x09,
aoqi@0	153	ldsh_op3 = 0x0a,
aoqi@0	154	ldx_op3 = 0x0b,
aoqi@0	155
aoqi@0	156	stx_op3 = 0x0e,
aoqi@0	157	swap_op3 = 0x0f,
aoqi@0	158
aoqi@0	159	stwa_op3 = 0x14,
aoqi@0	160	stxa_op3 = 0x1e,
aoqi@0	161
aoqi@0	162	ldf_op3 = 0x20,
aoqi@0	163	ldfsr_op3 = 0x21,
aoqi@0	164	ldqf_op3 = 0x22,
aoqi@0	165	lddf_op3 = 0x23,
aoqi@0	166	stf_op3 = 0x24,
aoqi@0	167	stfsr_op3 = 0x25,
aoqi@0	168	stqf_op3 = 0x26,
aoqi@0	169	stdf_op3 = 0x27,
aoqi@0	170
aoqi@0	171	prefetch_op3 = 0x2d,
aoqi@0	172
aoqi@0	173	casa_op3 = 0x3c,
aoqi@0	174	casxa_op3 = 0x3e,
aoqi@0	175
aoqi@0	176	mftoi_op3 = 0x36,
aoqi@0	177
aoqi@0	178	alt_bit_op3 = 0x10,
aoqi@0	179	cc_bit_op3 = 0x10
aoqi@0	180	};
aoqi@0	181
aoqi@0	182	enum opfs {
aoqi@0	183	// selected opfs
aoqi@0	184	edge8n_opf = 0x01,
aoqi@0	185
aoqi@0	186	fmovs_opf = 0x01,
aoqi@0	187	fmovd_opf = 0x02,
aoqi@0	188
aoqi@0	189	fnegs_opf = 0x05,
aoqi@0	190	fnegd_opf = 0x06,
aoqi@0	191
aoqi@0	192	alignaddr_opf = 0x18,
aoqi@0	193
aoqi@0	194	fadds_opf = 0x41,
aoqi@0	195	faddd_opf = 0x42,
aoqi@0	196	fsubs_opf = 0x45,
aoqi@0	197	fsubd_opf = 0x46,
aoqi@0	198
aoqi@0	199	faligndata_opf = 0x48,
aoqi@0	200
aoqi@0	201	fmuls_opf = 0x49,
aoqi@0	202	fmuld_opf = 0x4a,
aoqi@0	203	fdivs_opf = 0x4d,
aoqi@0	204	fdivd_opf = 0x4e,
aoqi@0	205
aoqi@0	206	fcmps_opf = 0x51,
aoqi@0	207	fcmpd_opf = 0x52,
aoqi@0	208
aoqi@0	209	fstox_opf = 0x81,
aoqi@0	210	fdtox_opf = 0x82,
aoqi@0	211	fxtos_opf = 0x84,
aoqi@0	212	fxtod_opf = 0x88,
aoqi@0	213	fitos_opf = 0xc4,
aoqi@0	214	fdtos_opf = 0xc6,
aoqi@0	215	fitod_opf = 0xc8,
aoqi@0	216	fstod_opf = 0xc9,
aoqi@0	217	fstoi_opf = 0xd1,
aoqi@0	218	fdtoi_opf = 0xd2,
aoqi@0	219
aoqi@0	220	mdtox_opf = 0x110,
aoqi@0	221	mstouw_opf = 0x111,
aoqi@0	222	mstosw_opf = 0x113,
aoqi@0	223	mxtod_opf = 0x118,
aoqi@0	224	mwtos_opf = 0x119,
aoqi@0	225
aoqi@0	226	aes_kexpand0_opf = 0x130,
kvn@7027	227	aes_kexpand2_opf = 0x131,
kvn@7027	228
kvn@7027	229	sha1_opf = 0x141,
kvn@7027	230	sha256_opf = 0x142,
kvn@7027	231	sha512_opf = 0x143
aoqi@0	232	};
aoqi@0	233
aoqi@0	234	enum op5s {
aoqi@0	235	aes_eround01_op5 = 0x00,
aoqi@0	236	aes_eround23_op5 = 0x01,
aoqi@0	237	aes_dround01_op5 = 0x02,
aoqi@0	238	aes_dround23_op5 = 0x03,
aoqi@0	239	aes_eround01_l_op5 = 0x04,
aoqi@0	240	aes_eround23_l_op5 = 0x05,
aoqi@0	241	aes_dround01_l_op5 = 0x06,
aoqi@0	242	aes_dround23_l_op5 = 0x07,
aoqi@0	243	aes_kexpand1_op5 = 0x08
aoqi@0	244	};
aoqi@0	245
aoqi@0	246	enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
aoqi@0	247
aoqi@0	248	enum Condition {
aoqi@0	249	// for FBfcc & FBPfcc instruction
aoqi@0	250	f_never = 0,
aoqi@0	251	f_notEqual = 1,
aoqi@0	252	f_notZero = 1,
aoqi@0	253	f_lessOrGreater = 2,
aoqi@0	254	f_unorderedOrLess = 3,
aoqi@0	255	f_less = 4,
aoqi@0	256	f_unorderedOrGreater = 5,
aoqi@0	257	f_greater = 6,
aoqi@0	258	f_unordered = 7,
aoqi@0	259	f_always = 8,
aoqi@0	260	f_equal = 9,
aoqi@0	261	f_zero = 9,
aoqi@0	262	f_unorderedOrEqual = 10,
aoqi@0	263	f_greaterOrEqual = 11,
aoqi@0	264	f_unorderedOrGreaterOrEqual = 12,
aoqi@0	265	f_lessOrEqual = 13,
aoqi@0	266	f_unorderedOrLessOrEqual = 14,
aoqi@0	267	f_ordered = 15,
aoqi@0	268
aoqi@0	269	// V8 coproc, pp 123 v8 manual
aoqi@0	270
aoqi@0	271	cp_always = 8,
aoqi@0	272	cp_never = 0,
aoqi@0	273	cp_3 = 7,
aoqi@0	274	cp_2 = 6,
aoqi@0	275	cp_2or3 = 5,
aoqi@0	276	cp_1 = 4,
aoqi@0	277	cp_1or3 = 3,
aoqi@0	278	cp_1or2 = 2,
aoqi@0	279	cp_1or2or3 = 1,
aoqi@0	280	cp_0 = 9,
aoqi@0	281	cp_0or3 = 10,
aoqi@0	282	cp_0or2 = 11,
aoqi@0	283	cp_0or2or3 = 12,
aoqi@0	284	cp_0or1 = 13,
aoqi@0	285	cp_0or1or3 = 14,
aoqi@0	286	cp_0or1or2 = 15,
aoqi@0	287
aoqi@0	288
aoqi@0	289	// for integers
aoqi@0	290
aoqi@0	291	never = 0,
aoqi@0	292	equal = 1,
aoqi@0	293	zero = 1,
aoqi@0	294	lessEqual = 2,
aoqi@0	295	less = 3,
aoqi@0	296	lessEqualUnsigned = 4,
aoqi@0	297	lessUnsigned = 5,
aoqi@0	298	carrySet = 5,
aoqi@0	299	negative = 6,
aoqi@0	300	overflowSet = 7,
aoqi@0	301	always = 8,
aoqi@0	302	notEqual = 9,
aoqi@0	303	notZero = 9,
aoqi@0	304	greater = 10,
aoqi@0	305	greaterEqual = 11,
aoqi@0	306	greaterUnsigned = 12,
aoqi@0	307	greaterEqualUnsigned = 13,
aoqi@0	308	carryClear = 13,
aoqi@0	309	positive = 14,
aoqi@0	310	overflowClear = 15
aoqi@0	311	};
aoqi@0	312
aoqi@0	313	enum CC {
aoqi@0	314	icc = 0, xcc = 2,
aoqi@0	315	// ptr_cc is the correct condition code for a pointer or intptr_t:
aoqi@0	316	ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
aoqi@0	317	fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
aoqi@0	318	};
aoqi@0	319
aoqi@0	320	enum PrefetchFcn {
aoqi@0	321	severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
aoqi@0	322	};
aoqi@0	323
aoqi@0	324	public:
aoqi@0	325	// Helper functions for groups of instructions
aoqi@0	326
aoqi@0	327	enum Predict { pt = 1, pn = 0 }; // pt = predict taken
aoqi@0	328
aoqi@0	329	enum Membar_mask_bits { // page 184, v9
aoqi@0	330	StoreStore = 1 << 3,
aoqi@0	331	LoadStore = 1 << 2,
aoqi@0	332	StoreLoad = 1 << 1,
aoqi@0	333	LoadLoad = 1 << 0,
aoqi@0	334
aoqi@0	335	Sync = 1 << 6,
aoqi@0	336	MemIssue = 1 << 5,
aoqi@0	337	Lookaside = 1 << 4
aoqi@0	338	};
aoqi@0	339
aoqi@0	340	static bool is_in_wdisp_range(address a, address b, int nbits) {
aoqi@0	341	intptr_t d = intptr_t(b) - intptr_t(a);
aoqi@0	342	return is_simm(d, nbits + 2);
aoqi@0	343	}
aoqi@0	344
aoqi@0	345	address target_distance(Label& L) {
aoqi@0	346	// Assembler::target(L) should be called only when
aoqi@0	347	// a branch instruction is emitted since non-bound
aoqi@0	348	// labels record current pc() as a branch address.
aoqi@0	349	if (L.is_bound()) return target(L);
aoqi@0	350	// Return current address for non-bound labels.
aoqi@0	351	return pc();
aoqi@0	352	}
aoqi@0	353
aoqi@0	354	// test if label is in simm16 range in words (wdisp16).
aoqi@0	355	bool is_in_wdisp16_range(Label& L) {
aoqi@0	356	return is_in_wdisp_range(target_distance(L), pc(), 16);
aoqi@0	357	}
aoqi@0	358	// test if the distance between two addresses fits in simm30 range in words
aoqi@0	359	static bool is_in_wdisp30_range(address a, address b) {
aoqi@0	360	return is_in_wdisp_range(a, b, 30);
aoqi@0	361	}
aoqi@0	362
aoqi@0	363	enum ASIs { // page 72, v9
aoqi@0	364	ASI_PRIMARY = 0x80,
aoqi@0	365	ASI_PRIMARY_NOFAULT = 0x82,
aoqi@0	366	ASI_PRIMARY_LITTLE = 0x88,
aoqi@0	367	// 8x8-bit partial store
aoqi@0	368	ASI_PST8_PRIMARY = 0xC0,
aoqi@0	369	// Block initializing store
aoqi@0	370	ASI_ST_BLKINIT_PRIMARY = 0xE2,
aoqi@0	371	// Most-Recently-Used (MRU) BIS variant
aoqi@0	372	ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
aoqi@0	373	// add more from book as needed
aoqi@0	374	};
aoqi@0	375
aoqi@0	376	protected:
aoqi@0	377	// helpers
aoqi@0	378
aoqi@0	379	// x is supposed to fit in a field "nbits" wide
aoqi@0	380	// and be sign-extended. Check the range.
aoqi@0	381
aoqi@0	382	static void assert_signed_range(intptr_t x, int nbits) {
aoqi@0	383	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
aoqi@0	384	err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
aoqi@0	385	}
aoqi@0	386
aoqi@0	387	static void assert_signed_word_disp_range(intptr_t x, int nbits) {
aoqi@0	388	assert( (x & 3) == 0, "not word aligned");
aoqi@0	389	assert_signed_range(x, nbits + 2);
aoqi@0	390	}
aoqi@0	391
aoqi@0	392	static void assert_unsigned_const(int x, int nbits) {
aoqi@0	393	assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
aoqi@0	394	}
aoqi@0	395
aoqi@0	396	// fields: note bits numbered from LSB = 0,
aoqi@0	397	// fields known by inclusive bit range
aoqi@0	398
aoqi@0	399	static int fmask(juint hi_bit, juint lo_bit) {
aoqi@0	400	assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
aoqi@0	401	return (1 << ( hi_bit-lo_bit + 1 )) - 1;
aoqi@0	402	}
aoqi@0	403
aoqi@0	404	// inverse of u_field
aoqi@0	405
aoqi@0	406	static int inv_u_field(int x, int hi_bit, int lo_bit) {
aoqi@0	407	juint r = juint(x) >> lo_bit;
aoqi@0	408	r &= fmask( hi_bit, lo_bit);
aoqi@0	409	return int(r);
aoqi@0	410	}
aoqi@0	411
aoqi@0	412
aoqi@0	413	// signed version: extract from field and sign-extend
aoqi@0	414
aoqi@0	415	static int inv_s_field(int x, int hi_bit, int lo_bit) {
aoqi@0	416	int sign_shift = 31 - hi_bit;
aoqi@0	417	return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
aoqi@0	418	}
aoqi@0	419
aoqi@0	420	// given a field that ranges from hi_bit to lo_bit (inclusive,
aoqi@0	421	// LSB = 0), and an unsigned value for the field,
aoqi@0	422	// shift it into the field
aoqi@0	423
aoqi@0	424	#ifdef ASSERT
aoqi@0	425	static int u_field(int x, int hi_bit, int lo_bit) {
aoqi@0	426	assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
aoqi@0	427	"value out of range");
aoqi@0	428	int r = x << lo_bit;
aoqi@0	429	assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
aoqi@0	430	return r;
aoqi@0	431	}
aoqi@0	432	#else
aoqi@0	433	// make sure this is inlined as it will reduce code size significantly
aoqi@0	434	#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
aoqi@0	435	#endif
aoqi@0	436
aoqi@0	437	static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
aoqi@0	438	static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
aoqi@0	439	static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
aoqi@0	440	static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
aoqi@0	441
aoqi@0	442	static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
aoqi@0	443
aoqi@0	444	static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
aoqi@0	445	static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
aoqi@0	446	static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
aoqi@0	447
aoqi@0	448	static int op( int x) { return u_field(x, 31, 30); }
aoqi@0	449	static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
aoqi@0	450	static int fcn( int x) { return u_field(x, 29, 25); }
aoqi@0	451	static int op3( int x) { return u_field(x, 24, 19); }
aoqi@0	452	static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
aoqi@0	453	static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
aoqi@0	454	static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
aoqi@0	455	static int cond( int x) { return u_field(x, 28, 25); }
aoqi@0	456	static int cond_mov( int x) { return u_field(x, 17, 14); }
aoqi@0	457	static int rcond( RCondition x) { return u_field(x, 12, 10); }
aoqi@0	458	static int op2( int x) { return u_field(x, 24, 22); }
aoqi@0	459	static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
aoqi@0	460	static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
aoqi@0	461	static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
aoqi@0	462	static int imm_asi( int x) { return u_field(x, 12, 5); }
aoqi@0	463	static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
aoqi@0	464	static int opf_low6( int w) { return u_field(w, 10, 5); }
aoqi@0	465	static int opf_low5( int w) { return u_field(w, 9, 5); }
aoqi@0	466	static int op5( int x) { return u_field(x, 8, 5); }
aoqi@0	467	static int trapcc( CC cc) { return u_field(cc, 12, 11); }
aoqi@0	468	static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
aoqi@0	469	static int opf( int x) { return u_field(x, 13, 5); }
aoqi@0	470
aoqi@0	471	static bool is_cbcond( int x ) {
aoqi@0	472	return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
aoqi@0	473	inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
aoqi@0	474	}
aoqi@0	475	static bool is_cxb( int x ) {
aoqi@0	476	assert(is_cbcond(x), "wrong instruction");
aoqi@0	477	return (x & (1<<21)) != 0;
aoqi@0	478	}
aoqi@0	479	static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
aoqi@0	480	static int inv_cond_cbcond(int x) {
aoqi@0	481	assert(is_cbcond(x), "wrong instruction");
aoqi@0	482	return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
aoqi@0	483	}
aoqi@0	484
aoqi@0	485	static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
aoqi@0	486	static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
aoqi@0	487
aoqi@0	488	static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
aoqi@0	489	static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
aoqi@0	490	static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
aoqi@0	491	static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
aoqi@0	492
aoqi@0	493	// some float instructions use this encoding on the op3 field
aoqi@0	494	static int alt_op3(int op, FloatRegisterImpl::Width w) {
aoqi@0	495	int r;
aoqi@0	496	switch(w) {
aoqi@0	497	case FloatRegisterImpl::S: r = op + 0; break;
aoqi@0	498	case FloatRegisterImpl::D: r = op + 3; break;
aoqi@0	499	case FloatRegisterImpl::Q: r = op + 2; break;
aoqi@0	500	default: ShouldNotReachHere(); break;
aoqi@0	501	}
aoqi@0	502	return op3(r);
aoqi@0	503	}
aoqi@0	504
aoqi@0	505
aoqi@0	506	// compute inverse of simm
aoqi@0	507	static int inv_simm(int x, int nbits) {
aoqi@0	508	return (int)(x << (32 - nbits)) >> (32 - nbits);
aoqi@0	509	}
aoqi@0	510
aoqi@0	511	static int inv_simm13( int x ) { return inv_simm(x, 13); }
aoqi@0	512
aoqi@0	513	// signed immediate, in low bits, nbits long
aoqi@0	514	static int simm(int x, int nbits) {
aoqi@0	515	assert_signed_range(x, nbits);
aoqi@0	516	return x & (( 1 << nbits ) - 1);
aoqi@0	517	}
aoqi@0	518
aoqi@0	519	// compute inverse of wdisp16
aoqi@0	520	static intptr_t inv_wdisp16(int x, intptr_t pos) {
aoqi@0	521	int lo = x & (( 1 << 14 ) - 1);
aoqi@0	522	int hi = (x >> 20) & 3;
aoqi@0	523	if (hi >= 2) hi |= ~1;
aoqi@0	524	return (((hi << 14) | lo) << 2) + pos;
aoqi@0	525	}
aoqi@0	526
aoqi@0	527	// word offset, 14 bits at LSend, 2 bits at B21, B20
aoqi@0	528	static int wdisp16(intptr_t x, intptr_t off) {
aoqi@0	529	intptr_t xx = x - off;
aoqi@0	530	assert_signed_word_disp_range(xx, 16);
aoqi@0	531	int r = (xx >> 2) & ((1 << 14) - 1)
aoqi@0	532	| ( ( (xx>>(2+14)) & 3 ) << 20 );
aoqi@0	533	assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
aoqi@0	534	return r;
aoqi@0	535	}
aoqi@0	536
aoqi@0	537	// compute inverse of wdisp10
aoqi@0	538	static intptr_t inv_wdisp10(int x, intptr_t pos) {
aoqi@0	539	assert(is_cbcond(x), "wrong instruction");
aoqi@0	540	int lo = inv_u_field(x, 12, 5);
aoqi@0	541	int hi = (x >> 19) & 3;
aoqi@0	542	if (hi >= 2) hi |= ~1;
aoqi@0	543	return (((hi << 8) | lo) << 2) + pos;
aoqi@0	544	}
aoqi@0	545
aoqi@0	546	// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
aoqi@0	547	static int wdisp10(intptr_t x, intptr_t off) {
aoqi@0	548	assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
aoqi@0	549	intptr_t xx = x - off;
aoqi@0	550	assert_signed_word_disp_range(xx, 10);
aoqi@0	551	int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
aoqi@0	552	| ( ( (xx >> (2+8)) & 3 ) << 19 );
aoqi@0	553	// Have to fake cbcond instruction to pass assert in inv_wdisp10()
aoqi@0	554	assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
aoqi@0	555	return r;
aoqi@0	556	}
aoqi@0	557
aoqi@0	558	// word displacement in low-order nbits bits
aoqi@0	559
aoqi@0	560	static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
aoqi@0	561	int pre_sign_extend = x & (( 1 << nbits ) - 1);
aoqi@0	562	int r = pre_sign_extend >= ( 1 << (nbits-1) )
aoqi@0	563	? pre_sign_extend | ~(( 1 << nbits ) - 1)
aoqi@0	564	: pre_sign_extend;
aoqi@0	565	return (r << 2) + pos;
aoqi@0	566	}
aoqi@0	567
aoqi@0	568	static int wdisp( intptr_t x, intptr_t off, int nbits ) {
aoqi@0	569	intptr_t xx = x - off;
aoqi@0	570	assert_signed_word_disp_range(xx, nbits);
aoqi@0	571	int r = (xx >> 2) & (( 1 << nbits ) - 1);
aoqi@0	572	assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
aoqi@0	573	return r;
aoqi@0	574	}
aoqi@0	575
aoqi@0	576
aoqi@0	577	// Extract the top 32 bits in a 64 bit word
aoqi@0	578	static int32_t hi32( int64_t x ) {
aoqi@0	579	int32_t r = int32_t( (uint64_t)x >> 32 );
aoqi@0	580	return r;
aoqi@0	581	}
aoqi@0	582
aoqi@0	583	// given a sethi instruction, extract the constant, left-justified
aoqi@0	584	static int inv_hi22( int x ) {
aoqi@0	585	return x << 10;
aoqi@0	586	}
aoqi@0	587
aoqi@0	588	// create an imm22 field, given a 32-bit left-justified constant
aoqi@0	589	static int hi22( int x ) {
aoqi@0	590	int r = int( juint(x) >> 10 );
aoqi@0	591	assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
aoqi@0	592	return r;
aoqi@0	593	}
aoqi@0	594
aoqi@0	595	// create a low10 __value__ (not a field) for a given a 32-bit constant
aoqi@0	596	static int low10( int x ) {
aoqi@0	597	return x & ((1 << 10) - 1);
aoqi@0	598	}
aoqi@0	599
aoqi@0	600	// AES crypto instructions supported only on certain processors
aoqi@0	601	static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
aoqi@0	602
kvn@7027	603	// SHA crypto instructions supported only on certain processors
kvn@7027	604	static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
kvn@7027	605	static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
kvn@7027	606	static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
kvn@7027	607
aoqi@0	608	// instruction only in VIS1
aoqi@0	609	static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
aoqi@0	610
aoqi@0	611	// instruction only in VIS2
aoqi@0	612	static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
aoqi@0	613
aoqi@0	614	// instruction only in VIS3
aoqi@0	615	static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
aoqi@0	616
aoqi@0	617	// instruction only in v9
aoqi@0	618	static void v9_only() { } // do nothing
aoqi@0	619
aoqi@0	620	// instruction deprecated in v9
aoqi@0	621	static void v9_dep() { } // do nothing for now
aoqi@0	622
aoqi@0	623	// v8 has no CC field
aoqi@0	624	static void v8_no_cc(CC cc) { if (cc) v9_only(); }
aoqi@0	625
aoqi@0	626	protected:
aoqi@0	627	// Simple delay-slot scheme:
aoqi@0	628	// In order to check the programmer, the assembler keeps track of deley slots.
aoqi@0	629	// It forbids CTIs in delay slots (conservative, but should be OK).
aoqi@0	630	// Also, when putting an instruction into a delay slot, you must say
aoqi@0	631	// asm->delayed()->add(...), in order to check that you don't omit
aoqi@0	632	// delay-slot instructions.
aoqi@0	633	// To implement this, we use a simple FSA
aoqi@0	634
aoqi@0	635	#ifdef ASSERT
aoqi@0	636	#define CHECK_DELAY
aoqi@0	637	#endif
aoqi@0	638	#ifdef CHECK_DELAY
aoqi@0	639	enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
aoqi@0	640	#endif
aoqi@0	641
aoqi@0	642	public:
aoqi@0	643	// Tells assembler next instruction must NOT be in delay slot.
aoqi@0	644	// Use at start of multinstruction macros.
aoqi@0	645	void assert_not_delayed() {
aoqi@0	646	// This is a separate overloading to avoid creation of string constants
aoqi@0	647	// in non-asserted code--with some compilers this pollutes the object code.
aoqi@0	648	#ifdef CHECK_DELAY
aoqi@0	649	assert_not_delayed("next instruction should not be a delay slot");
aoqi@0	650	#endif
aoqi@0	651	}
aoqi@0	652	void assert_not_delayed(const char* msg) {
aoqi@0	653	#ifdef CHECK_DELAY
aoqi@0	654	assert(delay_state == no_delay, msg);
aoqi@0	655	#endif
aoqi@0	656	}
aoqi@0	657
aoqi@0	658	protected:
aoqi@0	659	// Insert a nop if the previous is cbcond
aoqi@0	660	void insert_nop_after_cbcond() {
aoqi@0	661	if (UseCBCond && cbcond_before()) {
aoqi@0	662	nop();
aoqi@0	663	}
aoqi@0	664	}
aoqi@0	665	// Delay slot helpers
aoqi@0	666	// cti is called when emitting control-transfer instruction,
aoqi@0	667	// BEFORE doing the emitting.
aoqi@0	668	// Only effective when assertion-checking is enabled.
aoqi@0	669	void cti() {
aoqi@0	670	// A cbcond instruction immediately followed by a CTI
aoqi@0	671	// instruction introduces pipeline stalls, we need to avoid that.
aoqi@0	672	no_cbcond_before();
aoqi@0	673	#ifdef CHECK_DELAY
aoqi@0	674	assert_not_delayed("cti should not be in delay slot");
aoqi@0	675	#endif
aoqi@0	676	}
aoqi@0	677
aoqi@0	678	// called when emitting cti with a delay slot, AFTER emitting
aoqi@0	679	void has_delay_slot() {
aoqi@0	680	#ifdef CHECK_DELAY
aoqi@0	681	assert_not_delayed("just checking");
aoqi@0	682	delay_state = at_delay_slot;
aoqi@0	683	#endif
aoqi@0	684	}
aoqi@0	685
aoqi@0	686	// cbcond instruction should not be generated one after an other
aoqi@0	687	bool cbcond_before() {
aoqi@0	688	if (offset() == 0) return false; // it is first instruction
aoqi@0	689	int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
aoqi@0	690	return is_cbcond(x);
aoqi@0	691	}
aoqi@0	692
aoqi@0	693	void no_cbcond_before() {
aoqi@0	694	assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
aoqi@0	695	}
aoqi@0	696	public:
aoqi@0	697
aoqi@0	698	bool use_cbcond(Label& L) {
aoqi@0	699	if (!UseCBCond || cbcond_before()) return false;
aoqi@0	700	intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
aoqi@0	701	assert( (x & 3) == 0, "not word aligned");
aoqi@0	702	return is_simm12(x);
aoqi@0	703	}
aoqi@0	704
aoqi@0	705	// Tells assembler you know that next instruction is delayed
aoqi@0	706	Assembler* delayed() {
aoqi@0	707	#ifdef CHECK_DELAY
aoqi@0	708	assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
aoqi@0	709	delay_state = filling_delay_slot;
aoqi@0	710	#endif
aoqi@0	711	return this;
aoqi@0	712	}
aoqi@0	713
aoqi@0	714	void flush() {
aoqi@0	715	#ifdef CHECK_DELAY
aoqi@0	716	assert ( delay_state == no_delay, "ending code with a delay slot");
aoqi@0	717	#endif
aoqi@0	718	AbstractAssembler::flush();
aoqi@0	719	}
aoqi@0	720
aoqi@0	721	inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
aoqi@0	722	inline void emit_data(int x) { emit_int32(x); }
aoqi@0	723	inline void emit_data(int, RelocationHolder const&);
aoqi@0	724	inline void emit_data(int, relocInfo::relocType rtype);
aoqi@0	725	// helper for above fcns
aoqi@0	726	inline void check_delay();
aoqi@0	727
aoqi@0	728
aoqi@0	729	public:
aoqi@0	730	// instructions, refer to page numbers in the SPARC Architecture Manual, V9
aoqi@0	731
aoqi@0	732	// pp 135 (addc was addx in v8)
aoqi@0	733
aoqi@0	734	inline void add(Register s1, Register s2, Register d );
aoqi@0	735	inline void add(Register s1, int simm13a, Register d );
aoqi@0	736
aoqi@0	737	void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	738	void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	739	void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	740	void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	741	void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	742	void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	743
aoqi@0	744
aoqi@0	745	// 4-operand AES instructions
aoqi@0	746
aoqi@0	747	void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	748	void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	749	void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	750	void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	751	void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	752	void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	753	void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	754	void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	755	void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	756
aoqi@0	757
aoqi@0	758	// 3-operand AES instructions
aoqi@0	759
aoqi@0	760	void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	761	void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
aoqi@0	762
aoqi@0	763	// pp 136
aoqi@0	764
aoqi@0	765	inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
aoqi@0	766	inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
aoqi@0	767
aoqi@0	768	// compare and branch
aoqi@0	769	inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
aoqi@0	770	inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
aoqi@0	771
aoqi@0	772	protected: // use MacroAssembler::br instead
aoqi@0	773
aoqi@0	774	// pp 138
aoqi@0	775
aoqi@0	776	inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
aoqi@0	777	inline void fb( Condition c, bool a, Label& L );
aoqi@0	778
aoqi@0	779	// pp 141
aoqi@0	780
aoqi@0	781	inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
aoqi@0	782	inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
aoqi@0	783
aoqi@0	784	// pp 144
aoqi@0	785
aoqi@0	786	inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
aoqi@0	787	inline void br( Condition c, bool a, Label& L );
aoqi@0	788
aoqi@0	789	// pp 146
aoqi@0	790
aoqi@0	791	inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
aoqi@0	792	inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
aoqi@0	793
aoqi@0	794	// pp 149
aoqi@0	795
aoqi@0	796	inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
aoqi@0	797	inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
aoqi@0	798
aoqi@0	799	public:
aoqi@0	800
aoqi@0	801	// pp 150
aoqi@0	802
aoqi@0	803	// These instructions compare the contents of s2 with the contents of
aoqi@0	804	// memory at address in s1. If the values are equal, the contents of memory
aoqi@0	805	// at address s1 is swapped with the data in d. If the values are not equal,
aoqi@0	806	// the the contents of memory at s1 is loaded into d, without the swap.
aoqi@0	807
aoqi@0	808	void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
aoqi@0	809	void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
aoqi@0	810
aoqi@0	811	// pp 152
aoqi@0	812
aoqi@0	813	void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
aoqi@0	814	void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	815	void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
aoqi@0	816	void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	817	void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
aoqi@0	818	void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	819	void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
aoqi@0	820	void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	821
aoqi@0	822	// pp 155
aoqi@0	823
aoqi@0	824	void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
aoqi@0	825	void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
aoqi@0	826
aoqi@0	827	// pp 156
aoqi@0	828
aoqi@0	829	void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
aoqi@0	830	void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
aoqi@0	831
aoqi@0	832	// pp 157
aoqi@0	833
aoqi@0	834	void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
aoqi@0	835	void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
aoqi@0	836
aoqi@0	837	// pp 159
aoqi@0	838
aoqi@0	839	void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
aoqi@0	840	void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
aoqi@0	841
aoqi@0	842	// pp 160
aoqi@0	843
aoqi@0	844	void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
aoqi@0	845
aoqi@0	846	// pp 161
aoqi@0	847
aoqi@0	848	void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
aoqi@0	849	void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
aoqi@0	850
aoqi@0	851	// pp 162
aoqi@0	852
aoqi@0	853	void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
aoqi@0	854
aoqi@0	855	void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
aoqi@0	856
aoqi@0	857	void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
aoqi@0	858
aoqi@0	859	// pp 163
aoqi@0	860
aoqi@0	861	void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
aoqi@0	862	void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
aoqi@0	863	void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
aoqi@0	864
aoqi@0	865	// FXORs/FXORd instructions
aoqi@0	866
aoqi@0	867	void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
aoqi@0	868
aoqi@0	869	// pp 164
aoqi@0	870
aoqi@0	871	void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
aoqi@0	872
aoqi@0	873	// pp 165
aoqi@0	874
aoqi@0	875	inline void flush( Register s1, Register s2 );
aoqi@0	876	inline void flush( Register s1, int simm13a);
aoqi@0	877
aoqi@0	878	// pp 167
aoqi@0	879
aoqi@0	880	void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
aoqi@0	881
aoqi@0	882	// pp 168
aoqi@0	883
aoqi@0	884	void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
aoqi@0	885	// v8 unimp == illtrap(0)
aoqi@0	886
aoqi@0	887	// pp 169
aoqi@0	888
aoqi@0	889	void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
aoqi@0	890	void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
aoqi@0	891
aoqi@0	892	// pp 170
aoqi@0	893
aoqi@0	894	void jmpl( Register s1, Register s2, Register d );
aoqi@0	895	void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
aoqi@0	896
aoqi@0	897	// 171
aoqi@0	898
aoqi@0	899	inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
aoqi@0	900	inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
aoqi@0	901
aoqi@0	902
aoqi@0	903	inline void ldfsr( Register s1, Register s2 );
aoqi@0	904	inline void ldfsr( Register s1, int simm13a);
aoqi@0	905	inline void ldxfsr( Register s1, Register s2 );
aoqi@0	906	inline void ldxfsr( Register s1, int simm13a);
aoqi@0	907
aoqi@0	908	// 173
aoqi@0	909
aoqi@0	910	void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	911	void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	912
aoqi@0	913	// pp 175, lduw is ld on v8
aoqi@0	914
aoqi@0	915	inline void ldsb( Register s1, Register s2, Register d );
aoqi@0	916	inline void ldsb( Register s1, int simm13a, Register d);
aoqi@0	917	inline void ldsh( Register s1, Register s2, Register d );
aoqi@0	918	inline void ldsh( Register s1, int simm13a, Register d);
aoqi@0	919	inline void ldsw( Register s1, Register s2, Register d );
aoqi@0	920	inline void ldsw( Register s1, int simm13a, Register d);
aoqi@0	921	inline void ldub( Register s1, Register s2, Register d );
aoqi@0	922	inline void ldub( Register s1, int simm13a, Register d);
aoqi@0	923	inline void lduh( Register s1, Register s2, Register d );
aoqi@0	924	inline void lduh( Register s1, int simm13a, Register d);
aoqi@0	925	inline void lduw( Register s1, Register s2, Register d );
aoqi@0	926	inline void lduw( Register s1, int simm13a, Register d);
aoqi@0	927	inline void ldx( Register s1, Register s2, Register d );
aoqi@0	928	inline void ldx( Register s1, int simm13a, Register d);
aoqi@0	929	inline void ldd( Register s1, Register s2, Register d );
aoqi@0	930	inline void ldd( Register s1, int simm13a, Register d);
aoqi@0	931
aoqi@0	932	// pp 177
aoqi@0	933
aoqi@0	934	void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	935	void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	936	void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	937	void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	938	void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	939	void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	940	void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	941	void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	942	void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	943	void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	944	void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	945	void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	946	void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	947	void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	948
aoqi@0	949	// pp 181
aoqi@0	950
aoqi@0	951	void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	952	void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	953	void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	954	void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	955	void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	956	void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	957	void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	958	void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	959	void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	960	void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	961	void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	962	void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	963	void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	964	void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	965	void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	966	void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	967	void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	968	void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	969	void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	970	void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	971	void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	972	void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	973	void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	974	void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	975
aoqi@0	976	// pp 183
aoqi@0	977
aoqi@0	978	void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
aoqi@0	979
aoqi@0	980	// pp 185
aoqi@0	981
aoqi@0	982	void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
aoqi@0	983
aoqi@0	984	// pp 189
aoqi@0	985
aoqi@0	986	void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
aoqi@0	987
aoqi@0	988	// pp 191
aoqi@0	989
aoqi@0	990	void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
aoqi@0	991	void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
aoqi@0	992
aoqi@0	993	// pp 195
aoqi@0	994
aoqi@0	995	void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
aoqi@0	996	void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
aoqi@0	997
aoqi@0	998	// pp 196
aoqi@0	999
aoqi@0	1000	void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1001	void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1002	void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1003	void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1004	void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1005	void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1006
aoqi@0	1007	// pp 197
aoqi@0	1008
aoqi@0	1009	void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1010	void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1011	void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1012	void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1013	void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1014	void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1015	void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1016	void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1017
aoqi@0	1018	// pp 201
aoqi@0	1019
aoqi@0	1020	void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
aoqi@0	1021
aoqi@0	1022
aoqi@0	1023	// pp 202
aoqi@0	1024
aoqi@0	1025	void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
aoqi@0	1026	void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
aoqi@0	1027
aoqi@0	1028	// pp 203
aoqi@0	1029
aoqi@0	1030	void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1031	void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
aoqi@0	1032
aoqi@0	1033	void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1034	void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1035
aoqi@0	1036	// pp 208
aoqi@0	1037
aoqi@0	1038	// not implementing read privileged register
aoqi@0	1039
aoqi@0	1040	inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
aoqi@0	1041	inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
aoqi@0	1042	inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
aoqi@0	1043	inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
aoqi@0	1044	inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
aoqi@0	1045	inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
aoqi@0	1046
aoqi@0	1047	// pp 213
aoqi@0	1048
aoqi@0	1049	inline void rett( Register s1, Register s2);
aoqi@0	1050	inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
aoqi@0	1051
aoqi@0	1052	// pp 214
aoqi@0	1053
aoqi@0	1054	void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1055	void save( Register s1, int simm13a, Register d ) {
aoqi@0	1056	// make sure frame is at least large enough for the register save area
aoqi@0	1057	assert(-simm13a >= 16 * wordSize, "frame too small");
aoqi@0	1058	emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
aoqi@0	1059	}
aoqi@0	1060
aoqi@0	1061	void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1062	void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1063
aoqi@0	1064	// pp 216
aoqi@0	1065
aoqi@0	1066	void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
aoqi@0	1067	void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
aoqi@0	1068
aoqi@0	1069	// pp 217
aoqi@0	1070
aoqi@0	1071	inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
aoqi@0	1072	// pp 218
aoqi@0	1073
aoqi@0	1074	void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
aoqi@0	1075	void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
aoqi@0	1076	void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
aoqi@0	1077	void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
aoqi@0	1078	void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
aoqi@0	1079	void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
aoqi@0	1080
aoqi@0	1081	void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
aoqi@0	1082	void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
aoqi@0	1083	void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
aoqi@0	1084	void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
aoqi@0	1085	void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
aoqi@0	1086	void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
aoqi@0	1087
aoqi@0	1088	// pp 220
aoqi@0	1089
aoqi@0	1090	void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
aoqi@0	1091
aoqi@0	1092	// pp 221
aoqi@0	1093
aoqi@0	1094	void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
aoqi@0	1095
aoqi@0	1096	// pp 222
aoqi@0	1097
aoqi@0	1098	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
aoqi@0	1099	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
aoqi@0	1100
aoqi@0	1101	inline void stfsr( Register s1, Register s2 );
aoqi@0	1102	inline void stfsr( Register s1, int simm13a);
aoqi@0	1103	inline void stxfsr( Register s1, Register s2 );
aoqi@0	1104	inline void stxfsr( Register s1, int simm13a);
aoqi@0	1105
aoqi@0	1106	// pp 224
aoqi@0	1107
aoqi@0	1108	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1109	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1110
aoqi@0	1111	// p 226
aoqi@0	1112
aoqi@0	1113	inline void stb( Register d, Register s1, Register s2 );
aoqi@0	1114	inline void stb( Register d, Register s1, int simm13a);
aoqi@0	1115	inline void sth( Register d, Register s1, Register s2 );
aoqi@0	1116	inline void sth( Register d, Register s1, int simm13a);
aoqi@0	1117	inline void stw( Register d, Register s1, Register s2 );
aoqi@0	1118	inline void stw( Register d, Register s1, int simm13a);
aoqi@0	1119	inline void stx( Register d, Register s1, Register s2 );
aoqi@0	1120	inline void stx( Register d, Register s1, int simm13a);
aoqi@0	1121	inline void std( Register d, Register s1, Register s2 );
aoqi@0	1122	inline void std( Register d, Register s1, int simm13a);
aoqi@0	1123
aoqi@0	1124	// pp 177
aoqi@0	1125
aoqi@0	1126	void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1127	void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1128	void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1129	void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1130	void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1131	void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1132	void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1133	void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1134	void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1135	void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1136
aoqi@0	1137	// pp 230
aoqi@0	1138
aoqi@0	1139	void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1140	void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1141
aoqi@0	1142	void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1143	void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1144	void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1145	void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1146	void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
aoqi@0	1147	void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1148
aoqi@0	1149	// pp 231
aoqi@0	1150
aoqi@0	1151	inline void swap( Register s1, Register s2, Register d );
aoqi@0	1152	inline void swap( Register s1, int simm13a, Register d);
aoqi@0	1153
aoqi@0	1154	// pp 232
aoqi@0	1155
aoqi@0	1156	void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
aoqi@0	1157	void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1158
aoqi@0	1159	// pp 234, note op in book is wrong, see pp 268
aoqi@0	1160
aoqi@0	1161	void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1162	void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1163
aoqi@0	1164	// pp 235
aoqi@0	1165
aoqi@0	1166	void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
aoqi@0	1167	void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
aoqi@0	1168
aoqi@0	1169	// pp 237
aoqi@0	1170
aoqi@0	1171	void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
aoqi@0	1172	void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
aoqi@0	1173	// simple uncond. trap
aoqi@0	1174	void trap( int trapa ) { trap( always, icc, G0, trapa ); }
aoqi@0	1175
aoqi@0	1176	// pp 239 omit write priv register for now
aoqi@0	1177
aoqi@0	1178	inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
aoqi@0	1179	inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
aoqi@0	1180	inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
aoqi@0	1181	rs1(s) |
aoqi@0	1182	op3(wrreg_op3) |
aoqi@0	1183	u_field(2, 29, 25) |
aoqi@0	1184	immed(true) |
aoqi@0	1185	simm(simm13a, 13)); }
aoqi@0	1186	inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
aoqi@0	1187	// wrasi(d, imm) stores (d xor imm) to asi
aoqi@0	1188	inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
aoqi@0	1189	u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
aoqi@0	1190	inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
aoqi@0	1191
aoqi@0	1192	// VIS1 instructions
aoqi@0	1193
aoqi@0	1194	void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
aoqi@0	1195
aoqi@0	1196	void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
aoqi@0	1197
aoqi@0	1198	void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
aoqi@0	1199
aoqi@0	1200	void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
aoqi@0	1201
aoqi@0	1202	// VIS2 instructions
aoqi@0	1203
aoqi@0	1204	void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
aoqi@0	1205
aoqi@0	1206	// VIS3 instructions
aoqi@0	1207
aoqi@0	1208	void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
aoqi@0	1209	void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
aoqi@0	1210	void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
aoqi@0	1211
aoqi@0	1212	void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
aoqi@0	1213	void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
aoqi@0	1214
kvn@7027	1215	// Crypto SHA instructions
kvn@7027	1216
kvn@7027	1217	void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
kvn@7027	1218	void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
kvn@7027	1219	void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
kvn@7027	1220
aoqi@0	1221	// Creation
aoqi@0	1222	Assembler(CodeBuffer* code) : AbstractAssembler(code) {
aoqi@0	1223	#ifdef CHECK_DELAY
aoqi@0	1224	delay_state = no_delay;
aoqi@0	1225	#endif
aoqi@0	1226	}
aoqi@0	1227	};
aoqi@0	1228
aoqi@0	1229	#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP