src/share/vm/code/vmreg.hpp

Tue, 08 Aug 2017 15:57:29 +0800

author
aoqi
date
Tue, 08 Aug 2017 15:57:29 +0800
changeset 6876
710a3c8b516e
parent 6461
bdd155477289
parent 1
2d8a650513c2
child 7994
04ff2f6cd0eb
permissions
-rw-r--r--

merge

aoqi@0 1 /*
aoqi@0 2 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 4 *
aoqi@0 5 * This code is free software; you can redistribute it and/or modify it
aoqi@0 6 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 7 * published by the Free Software Foundation.
aoqi@0 8 *
aoqi@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 12 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 13 * accompanied this code).
aoqi@0 14 *
aoqi@0 15 * You should have received a copy of the GNU General Public License version
aoqi@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 18 *
aoqi@0 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 20 * or visit www.oracle.com if you need additional information or have any
aoqi@0 21 * questions.
aoqi@0 22 *
aoqi@0 23 */
aoqi@0 24
aoqi@1 25 /*
aoqi@1 26 * This file has been modified by Loongson Technology in 2015. These
aoqi@1 27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
aoqi@1 28 * available on the same license terms set forth above.
aoqi@1 29 */
aoqi@1 30
aoqi@0 31 #ifndef SHARE_VM_CODE_VMREG_HPP
aoqi@0 32 #define SHARE_VM_CODE_VMREG_HPP
aoqi@0 33
aoqi@0 34 #include "memory/allocation.hpp"
aoqi@0 35 #include "utilities/globalDefinitions.hpp"
aoqi@0 36 #include "asm/register.hpp"
aoqi@0 37
aoqi@0 38 #ifdef COMPILER2
aoqi@0 39 #include "opto/adlcVMDeps.hpp"
aoqi@0 40 #include "utilities/ostream.hpp"
aoqi@0 41 #ifdef TARGET_ARCH_MODEL_x86_32
aoqi@0 42 # include "adfiles/adGlobals_x86_32.hpp"
aoqi@0 43 #endif
aoqi@0 44 #ifdef TARGET_ARCH_MODEL_x86_64
aoqi@0 45 # include "adfiles/adGlobals_x86_64.hpp"
aoqi@0 46 #endif
aoqi@0 47 #ifdef TARGET_ARCH_MODEL_sparc
aoqi@0 48 # include "adfiles/adGlobals_sparc.hpp"
aoqi@0 49 #endif
aoqi@0 50 #ifdef TARGET_ARCH_MODEL_zero
aoqi@0 51 # include "adfiles/adGlobals_zero.hpp"
aoqi@0 52 #endif
aoqi@0 53 #ifdef TARGET_ARCH_MODEL_arm
aoqi@0 54 # include "adfiles/adGlobals_arm.hpp"
aoqi@0 55 #endif
aoqi@0 56 #ifdef TARGET_ARCH_MODEL_ppc_32
aoqi@0 57 # include "adfiles/adGlobals_ppc_32.hpp"
aoqi@0 58 #endif
aoqi@0 59 #ifdef TARGET_ARCH_MODEL_ppc_64
aoqi@0 60 # include "adfiles/adGlobals_ppc_64.hpp"
aoqi@0 61 #endif
aoqi@1 62 #ifdef TARGET_ARCH_MODEL_mips_64
aoqi@1 63 # include "adfiles/adGlobals_mips_64.hpp"
aoqi@1 64 #endif
aoqi@0 65 #endif
aoqi@0 66
aoqi@0 67 //------------------------------VMReg------------------------------------------
aoqi@0 68 // The VM uses 'unwarped' stack slots; the compiler uses 'warped' stack slots.
aoqi@0 69 // Register numbers below VMRegImpl::stack0 are the same for both. Register
aoqi@0 70 // numbers above stack0 are either warped (in the compiler) or unwarped
aoqi@0 71 // (in the VM). Unwarped numbers represent stack indices, offsets from
aoqi@0 72 // the current stack pointer. Warped numbers are required during compilation
aoqi@0 73 // when we do not yet know how big the frame will be.
aoqi@0 74
aoqi@0 75 class VMRegImpl;
aoqi@0 76 typedef VMRegImpl* VMReg;
aoqi@0 77
aoqi@0 78 class VMRegImpl {
aoqi@0 79 // friend class OopMap;
aoqi@0 80 friend class VMStructs;
aoqi@0 81 friend class OptoReg;
aoqi@0 82 // friend class Location;
aoqi@0 83 private:
aoqi@0 84 enum {
aoqi@0 85 BAD_REG = -1
aoqi@0 86 };
aoqi@0 87
aoqi@0 88
aoqi@0 89
aoqi@0 90 static VMReg stack0;
aoqi@0 91 // Names for registers
aoqi@0 92 static const char *regName[];
aoqi@0 93 static const int register_count;
aoqi@0 94
aoqi@0 95
aoqi@0 96 public:
aoqi@0 97
aoqi@0 98 static VMReg as_VMReg(int val, bool bad_ok = false) { assert(val > BAD_REG || bad_ok, "invalid"); return (VMReg) (intptr_t) val; }
aoqi@0 99
aoqi@0 100 const char* name() {
aoqi@0 101 if (is_reg()) {
aoqi@0 102 return regName[value()];
aoqi@0 103 } else if (!is_valid()) {
aoqi@0 104 return "BAD";
aoqi@0 105 } else {
aoqi@0 106 // shouldn't really be called with stack
aoqi@0 107 return "STACKED REG";
aoqi@0 108 }
aoqi@0 109 }
aoqi@0 110 static VMReg Bad() { return (VMReg) (intptr_t) BAD_REG; }
aoqi@0 111 bool is_valid() const { return ((intptr_t) this) != BAD_REG; }
aoqi@0 112 bool is_stack() const { return (intptr_t) this >= (intptr_t) stack0; }
aoqi@0 113 bool is_reg() const { return is_valid() && !is_stack(); }
aoqi@0 114
aoqi@0 115 // A concrete register is a value that returns true for is_reg() and is
aoqi@0 116 // also a register you could use in the assembler. On machines with
aoqi@0 117 // 64bit registers only one half of the VMReg (and OptoReg) is considered
aoqi@0 118 // concrete.
aoqi@0 119 bool is_concrete();
aoqi@0 120
aoqi@0 121 // VMRegs are 4 bytes wide on all platforms
aoqi@0 122 static const int stack_slot_size;
aoqi@0 123 static const int slots_per_word;
aoqi@0 124
aoqi@0 125
aoqi@0 126 // This really ought to check that the register is "real" in the sense that
aoqi@0 127 // we don't try and get the VMReg number of a physical register that doesn't
aoqi@0 128 // have an expressible part. That would be pd specific code
aoqi@0 129 VMReg next() {
aoqi@0 130 assert((is_reg() && value() < stack0->value() - 1) || is_stack(), "must be");
aoqi@0 131 return (VMReg)(intptr_t)(value() + 1);
aoqi@0 132 }
aoqi@0 133 VMReg next(int i) {
aoqi@0 134 assert((is_reg() && value() < stack0->value() - i) || is_stack(), "must be");
aoqi@0 135 return (VMReg)(intptr_t)(value() + i);
aoqi@0 136 }
aoqi@0 137 VMReg prev() {
aoqi@0 138 assert((is_stack() && value() > stack0->value()) || (is_reg() && value() != 0), "must be");
aoqi@0 139 return (VMReg)(intptr_t)(value() - 1);
aoqi@0 140 }
aoqi@0 141
aoqi@0 142
aoqi@0 143 intptr_t value() const {return (intptr_t) this; }
aoqi@0 144
aoqi@0 145 void print_on(outputStream* st) const;
aoqi@0 146 void print() const { print_on(tty); }
aoqi@0 147
aoqi@0 148 // bias a stack slot.
aoqi@0 149 // Typically used to adjust a virtual frame slots by amounts that are offset by
aoqi@0 150 // amounts that are part of the native abi. The VMReg must be a stack slot
aoqi@0 151 // and the result must be also.
aoqi@0 152
aoqi@0 153 VMReg bias(int offset) {
aoqi@0 154 assert(is_stack(), "must be");
aoqi@0 155 // VMReg res = VMRegImpl::as_VMReg(value() + offset);
aoqi@0 156 VMReg res = stack2reg(reg2stack() + offset);
aoqi@0 157 assert(res->is_stack(), "must be");
aoqi@0 158 return res;
aoqi@0 159 }
aoqi@0 160
aoqi@0 161 // Convert register numbers to stack slots and vice versa
aoqi@0 162 static VMReg stack2reg( int idx ) {
aoqi@0 163 return (VMReg) (intptr_t) (stack0->value() + idx);
aoqi@0 164 }
aoqi@0 165
aoqi@0 166 uintptr_t reg2stack() {
aoqi@0 167 assert( is_stack(), "Not a stack-based register" );
aoqi@0 168 return value() - stack0->value();
aoqi@0 169 }
aoqi@0 170
aoqi@0 171 static void set_regName();
aoqi@0 172
aoqi@0 173 #ifdef TARGET_ARCH_x86
aoqi@0 174 # include "vmreg_x86.hpp"
aoqi@0 175 #endif
aoqi@1 176 #ifdef TARGET_ARCH_mips
aoqi@1 177 # include "vmreg_mips.hpp"
aoqi@1 178 #endif
aoqi@0 179 #ifdef TARGET_ARCH_sparc
aoqi@0 180 # include "vmreg_sparc.hpp"
aoqi@0 181 #endif
aoqi@0 182 #ifdef TARGET_ARCH_zero
aoqi@0 183 # include "vmreg_zero.hpp"
aoqi@0 184 #endif
aoqi@0 185 #ifdef TARGET_ARCH_arm
aoqi@0 186 # include "vmreg_arm.hpp"
aoqi@0 187 #endif
aoqi@0 188 #ifdef TARGET_ARCH_ppc
aoqi@0 189 # include "vmreg_ppc.hpp"
aoqi@0 190 #endif
aoqi@0 191
aoqi@0 192
aoqi@0 193 };
aoqi@0 194
aoqi@0 195 //---------------------------VMRegPair-------------------------------------------
aoqi@0 196 // Pairs of 32-bit registers for arguments.
aoqi@0 197 // SharedRuntime::java_calling_convention will overwrite the structs with
aoqi@0 198 // the calling convention's registers. VMRegImpl::Bad is returned for any
aoqi@0 199 // unused 32-bit register. This happens for the unused high half of Int
aoqi@0 200 // arguments, or for 32-bit pointers or for longs in the 32-bit sparc build
aoqi@0 201 // (which are passed to natives in low 32-bits of e.g. O0/O1 and the high
aoqi@0 202 // 32-bits of O0/O1 are set to VMRegImpl::Bad). Longs in one register & doubles
aoqi@0 203 // always return a high and a low register, as do 64-bit pointers.
aoqi@0 204 //
aoqi@0 205 class VMRegPair {
aoqi@0 206 private:
aoqi@0 207 VMReg _second;
aoqi@0 208 VMReg _first;
aoqi@0 209 public:
aoqi@0 210 void set_bad ( ) { _second=VMRegImpl::Bad(); _first=VMRegImpl::Bad(); }
aoqi@0 211 void set1 ( VMReg v ) { _second=VMRegImpl::Bad(); _first=v; }
aoqi@0 212 void set2 ( VMReg v ) { _second=v->next(); _first=v; }
aoqi@0 213 void set_pair( VMReg second, VMReg first ) { _second= second; _first= first; }
aoqi@0 214 void set_ptr ( VMReg ptr ) {
aoqi@0 215 #ifdef _LP64
aoqi@0 216 _second = ptr->next();
aoqi@0 217 #else
aoqi@0 218 _second = VMRegImpl::Bad();
aoqi@0 219 #endif
aoqi@0 220 _first = ptr;
aoqi@0 221 }
aoqi@0 222 // Return true if single register, even if the pair is really just adjacent stack slots
aoqi@0 223 bool is_single_reg() const {
aoqi@0 224 return (_first->is_valid()) && (_first->value() + 1 == _second->value());
aoqi@0 225 }
aoqi@0 226
aoqi@0 227 // Return true if single stack based "register" where the slot alignment matches input alignment
aoqi@0 228 bool is_adjacent_on_stack(int alignment) const {
aoqi@0 229 return (_first->is_stack() && (_first->value() + 1 == _second->value()) && ((_first->value() & (alignment-1)) == 0));
aoqi@0 230 }
aoqi@0 231
aoqi@0 232 // Return true if single stack based "register" where the slot alignment matches input alignment
aoqi@0 233 bool is_adjacent_aligned_on_stack(int alignment) const {
aoqi@0 234 return (_first->is_stack() && (_first->value() + 1 == _second->value()) && ((_first->value() & (alignment-1)) == 0));
aoqi@0 235 }
aoqi@0 236
aoqi@0 237 // Return true if single register but adjacent stack slots do not count
aoqi@0 238 bool is_single_phys_reg() const {
aoqi@0 239 return (_first->is_reg() && (_first->value() + 1 == _second->value()));
aoqi@0 240 }
aoqi@0 241
aoqi@0 242 VMReg second() const { return _second; }
aoqi@0 243 VMReg first() const { return _first; }
aoqi@0 244 VMRegPair(VMReg s, VMReg f) { _second = s; _first = f; }
aoqi@0 245 VMRegPair(VMReg f) { _second = VMRegImpl::Bad(); _first = f; }
aoqi@0 246 VMRegPair() { _second = VMRegImpl::Bad(); _first = VMRegImpl::Bad(); }
aoqi@0 247 };
aoqi@0 248
aoqi@0 249 #endif // SHARE_VM_CODE_VMREG_HPP

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