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src/cpu/x86/vm/vm_version_x86.cpp@710a3c8b516e (annotated)

src/cpu/x86/vm/vm_version_x86.cpp

Tue, 08 Aug 2017 15:57:29 +0800

author
aoqi
date
Tue, 08 Aug 2017 15:57:29 +0800
changeset 6876
710a3c8b516e
parent 6680
78bbf4d43a14
parent 0
f90c822e73f8
child 7535
7ae4e26cb1e0
permissions
-rw-r--r--

merge

aoqi@0 1 /*
aoqi@0 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 4 *
aoqi@0 5 * This code is free software; you can redistribute it and/or modify it
aoqi@0 6 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 7 * published by the Free Software Foundation.
aoqi@0 8 *
aoqi@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 12 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 13 * accompanied this code).
aoqi@0 14 *
aoqi@0 15 * You should have received a copy of the GNU General Public License version
aoqi@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 18 *
aoqi@0 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 20 * or visit www.oracle.com if you need additional information or have any
aoqi@0 21 * questions.
aoqi@0 22 *
aoqi@0 23 */
aoqi@0 24
aoqi@0 25 #include "precompiled.hpp"
aoqi@0 26 #include "asm/macroAssembler.hpp"
aoqi@0 27 #include "asm/macroAssembler.inline.hpp"
aoqi@0 28 #include "memory/resourceArea.hpp"
aoqi@0 29 #include "runtime/java.hpp"
aoqi@0 30 #include "runtime/stubCodeGenerator.hpp"
aoqi@0 31 #include "vm_version_x86.hpp"
aoqi@0 32 #ifdef TARGET_OS_FAMILY_linux
aoqi@0 33 # include "os_linux.inline.hpp"
aoqi@0 34 #endif
aoqi@0 35 #ifdef TARGET_OS_FAMILY_solaris
aoqi@0 36 # include "os_solaris.inline.hpp"
aoqi@0 37 #endif
aoqi@0 38 #ifdef TARGET_OS_FAMILY_windows
aoqi@0 39 # include "os_windows.inline.hpp"
aoqi@0 40 #endif
aoqi@0 41 #ifdef TARGET_OS_FAMILY_bsd
aoqi@0 42 # include "os_bsd.inline.hpp"
aoqi@0 43 #endif
aoqi@0 44
aoqi@0 45
aoqi@0 46 int VM_Version::_cpu;
aoqi@0 47 int VM_Version::_model;
aoqi@0 48 int VM_Version::_stepping;
aoqi@0 49 int VM_Version::_cpuFeatures;
aoqi@0 50 const char* VM_Version::_features_str = "";
aoqi@0 51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
aoqi@0 52
aoqi@0 53 // Address of instruction which causes SEGV
aoqi@0 54 address VM_Version::_cpuinfo_segv_addr = 0;
aoqi@0 55 // Address of instruction after the one which causes SEGV
aoqi@0 56 address VM_Version::_cpuinfo_cont_addr = 0;
aoqi@0 57
aoqi@0 58 static BufferBlob* stub_blob;
aoqi@0 59 static const int stub_size = 600;
aoqi@0 60
aoqi@0 61 extern "C" {
aoqi@0 62 typedef void (*get_cpu_info_stub_t)(void*);
aoqi@0 63 }
aoqi@0 64 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
aoqi@0 65
aoqi@0 66
aoqi@0 67 class VM_Version_StubGenerator: public StubCodeGenerator {
aoqi@0 68 public:
aoqi@0 69
aoqi@0 70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
aoqi@0 71
aoqi@0 72 address generate_get_cpu_info() {
aoqi@0 73 // Flags to test CPU type.
aoqi@0 74 const uint32_t HS_EFL_AC = 0x40000;
aoqi@0 75 const uint32_t HS_EFL_ID = 0x200000;
aoqi@0 76 // Values for when we don't have a CPUID instruction.
aoqi@0 77 const int CPU_FAMILY_SHIFT = 8;
aoqi@0 78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
aoqi@0 79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
aoqi@0 80
aoqi@0 81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
aoqi@0 82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
aoqi@0 83
aoqi@0 84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
aoqi@0 85 # define __ _masm->
aoqi@0 86
aoqi@0 87 address start = __ pc();
aoqi@0 88
aoqi@0 89 //
aoqi@0 90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
aoqi@0 91 //
aoqi@0 92 // LP64: rcx and rdx are first and second argument registers on windows
aoqi@0 93
aoqi@0 94 __ push(rbp);
aoqi@0 95 #ifdef _LP64
aoqi@0 96 __ mov(rbp, c_rarg0); // cpuid_info address
aoqi@0 97 #else
aoqi@0 98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
aoqi@0 99 #endif
aoqi@0 100 __ push(rbx);
aoqi@0 101 __ push(rsi);
aoqi@0 102 __ pushf(); // preserve rbx, and flags
aoqi@0 103 __ pop(rax);
aoqi@0 104 __ push(rax);
aoqi@0 105 __ mov(rcx, rax);
aoqi@0 106 //
aoqi@0 107 // if we are unable to change the AC flag, we have a 386
aoqi@0 108 //
aoqi@0 109 __ xorl(rax, HS_EFL_AC);
aoqi@0 110 __ push(rax);
aoqi@0 111 __ popf();
aoqi@0 112 __ pushf();
aoqi@0 113 __ pop(rax);
aoqi@0 114 __ cmpptr(rax, rcx);
aoqi@0 115 __ jccb(Assembler::notEqual, detect_486);
aoqi@0 116
aoqi@0 117 __ movl(rax, CPU_FAMILY_386);
aoqi@0 118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
aoqi@0 119 __ jmp(done);
aoqi@0 120
aoqi@0 121 //
aoqi@0 122 // If we are unable to change the ID flag, we have a 486 which does
aoqi@0 123 // not support the "cpuid" instruction.
aoqi@0 124 //
aoqi@0 125 __ bind(detect_486);
aoqi@0 126 __ mov(rax, rcx);
aoqi@0 127 __ xorl(rax, HS_EFL_ID);
aoqi@0 128 __ push(rax);
aoqi@0 129 __ popf();
aoqi@0 130 __ pushf();
aoqi@0 131 __ pop(rax);
aoqi@0 132 __ cmpptr(rcx, rax);
aoqi@0 133 __ jccb(Assembler::notEqual, detect_586);
aoqi@0 134
aoqi@0 135 __ bind(cpu486);
aoqi@0 136 __ movl(rax, CPU_FAMILY_486);
aoqi@0 137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
aoqi@0 138 __ jmp(done);
aoqi@0 139
aoqi@0 140 //
aoqi@0 141 // At this point, we have a chip which supports the "cpuid" instruction
aoqi@0 142 //
aoqi@0 143 __ bind(detect_586);
aoqi@0 144 __ xorl(rax, rax);
aoqi@0 145 __ cpuid();
aoqi@0 146 __ orl(rax, rax);
aoqi@0 147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
aoqi@0 148 // value of at least 1, we give up and
aoqi@0 149 // assume a 486
aoqi@0 150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
aoqi@0 151 __ movl(Address(rsi, 0), rax);
aoqi@0 152 __ movl(Address(rsi, 4), rbx);
aoqi@0 153 __ movl(Address(rsi, 8), rcx);
aoqi@0 154 __ movl(Address(rsi,12), rdx);
aoqi@0 155
aoqi@0 156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
aoqi@0 157 __ jccb(Assembler::belowEqual, std_cpuid4);
aoqi@0 158
aoqi@0 159 //
aoqi@0 160 // cpuid(0xB) Processor Topology
aoqi@0 161 //
aoqi@0 162 __ movl(rax, 0xb);
aoqi@0 163 __ xorl(rcx, rcx); // Threads level
aoqi@0 164 __ cpuid();
aoqi@0 165
aoqi@0 166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
aoqi@0 167 __ movl(Address(rsi, 0), rax);
aoqi@0 168 __ movl(Address(rsi, 4), rbx);
aoqi@0 169 __ movl(Address(rsi, 8), rcx);
aoqi@0 170 __ movl(Address(rsi,12), rdx);
aoqi@0 171
aoqi@0 172 __ movl(rax, 0xb);
aoqi@0 173 __ movl(rcx, 1); // Cores level
aoqi@0 174 __ cpuid();
aoqi@0 175 __ push(rax);
aoqi@0 176 __ andl(rax, 0x1f); // Determine if valid topology level
aoqi@0 177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
aoqi@0 178 __ andl(rax, 0xffff);
aoqi@0 179 __ pop(rax);
aoqi@0 180 __ jccb(Assembler::equal, std_cpuid4);
aoqi@0 181
aoqi@0 182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
aoqi@0 183 __ movl(Address(rsi, 0), rax);
aoqi@0 184 __ movl(Address(rsi, 4), rbx);
aoqi@0 185 __ movl(Address(rsi, 8), rcx);
aoqi@0 186 __ movl(Address(rsi,12), rdx);
aoqi@0 187
aoqi@0 188 __ movl(rax, 0xb);
aoqi@0 189 __ movl(rcx, 2); // Packages level
aoqi@0 190 __ cpuid();
aoqi@0 191 __ push(rax);
aoqi@0 192 __ andl(rax, 0x1f); // Determine if valid topology level
aoqi@0 193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
aoqi@0 194 __ andl(rax, 0xffff);
aoqi@0 195 __ pop(rax);
aoqi@0 196 __ jccb(Assembler::equal, std_cpuid4);
aoqi@0 197
aoqi@0 198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
aoqi@0 199 __ movl(Address(rsi, 0), rax);
aoqi@0 200 __ movl(Address(rsi, 4), rbx);
aoqi@0 201 __ movl(Address(rsi, 8), rcx);
aoqi@0 202 __ movl(Address(rsi,12), rdx);
aoqi@0 203
aoqi@0 204 //
aoqi@0 205 // cpuid(0x4) Deterministic cache params
aoqi@0 206 //
aoqi@0 207 __ bind(std_cpuid4);
aoqi@0 208 __ movl(rax, 4);
aoqi@0 209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
aoqi@0 210 __ jccb(Assembler::greater, std_cpuid1);
aoqi@0 211
aoqi@0 212 __ xorl(rcx, rcx); // L1 cache
aoqi@0 213 __ cpuid();
aoqi@0 214 __ push(rax);
aoqi@0 215 __ andl(rax, 0x1f); // Determine if valid cache parameters used
aoqi@0 216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
aoqi@0 217 __ pop(rax);
aoqi@0 218 __ jccb(Assembler::equal, std_cpuid1);
aoqi@0 219
aoqi@0 220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
aoqi@0 221 __ movl(Address(rsi, 0), rax);
aoqi@0 222 __ movl(Address(rsi, 4), rbx);
aoqi@0 223 __ movl(Address(rsi, 8), rcx);
aoqi@0 224 __ movl(Address(rsi,12), rdx);
aoqi@0 225
aoqi@0 226 //
aoqi@0 227 // Standard cpuid(0x1)
aoqi@0 228 //
aoqi@0 229 __ bind(std_cpuid1);
aoqi@0 230 __ movl(rax, 1);
aoqi@0 231 __ cpuid();
aoqi@0 232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
aoqi@0 233 __ movl(Address(rsi, 0), rax);
aoqi@0 234 __ movl(Address(rsi, 4), rbx);
aoqi@0 235 __ movl(Address(rsi, 8), rcx);
aoqi@0 236 __ movl(Address(rsi,12), rdx);
aoqi@0 237
aoqi@0 238 //
aoqi@0 239 // Check if OS has enabled XGETBV instruction to access XCR0
aoqi@0 240 // (OSXSAVE feature flag) and CPU supports AVX
aoqi@0 241 //
aoqi@0 242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
aoqi@0 243 __ cmpl(rcx, 0x18000000);
aoqi@0 244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
aoqi@0 245
aoqi@0 246 //
aoqi@0 247 // XCR0, XFEATURE_ENABLED_MASK register
aoqi@0 248 //
aoqi@0 249 __ xorl(rcx, rcx); // zero for XCR0 register
aoqi@0 250 __ xgetbv();
aoqi@0 251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
aoqi@0 252 __ movl(Address(rsi, 0), rax);
aoqi@0 253 __ movl(Address(rsi, 4), rdx);
aoqi@0 254
aoqi@0 255 __ andl(rax, 0x6); // xcr0 bits sse | ymm
aoqi@0 256 __ cmpl(rax, 0x6);
aoqi@0 257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
aoqi@0 258
aoqi@0 259 //
aoqi@0 260 // Some OSs have a bug when upper 128bits of YMM
aoqi@0 261 // registers are not restored after a signal processing.
aoqi@0 262 // Generate SEGV here (reference through NULL)
aoqi@0 263 // and check upper YMM bits after it.
aoqi@0 264 //
aoqi@0 265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
aoqi@0 266 intx saved_useavx = UseAVX;
aoqi@0 267 intx saved_usesse = UseSSE;
aoqi@0 268 UseAVX = 1;
aoqi@0 269 UseSSE = 2;
aoqi@0 270
aoqi@0 271 // load value into all 32 bytes of ymm7 register
aoqi@0 272 __ movl(rcx, VM_Version::ymm_test_value());
aoqi@0 273
aoqi@0 274 __ movdl(xmm0, rcx);
aoqi@0 275 __ pshufd(xmm0, xmm0, 0x00);
aoqi@0 276 __ vinsertf128h(xmm0, xmm0, xmm0);
aoqi@0 277 __ vmovdqu(xmm7, xmm0);
aoqi@0 278 #ifdef _LP64
aoqi@0 279 __ vmovdqu(xmm8, xmm0);
aoqi@0 280 __ vmovdqu(xmm15, xmm0);
aoqi@0 281 #endif
aoqi@0 282
aoqi@0 283 __ xorl(rsi, rsi);
aoqi@0 284 VM_Version::set_cpuinfo_segv_addr( __ pc() );
aoqi@0 285 // Generate SEGV
aoqi@0 286 __ movl(rax, Address(rsi, 0));
aoqi@0 287
aoqi@0 288 VM_Version::set_cpuinfo_cont_addr( __ pc() );
aoqi@0 289 // Returns here after signal. Save xmm0 to check it later.
aoqi@0 290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
aoqi@0 291 __ vmovdqu(Address(rsi, 0), xmm0);
aoqi@0 292 __ vmovdqu(Address(rsi, 32), xmm7);
aoqi@0 293 #ifdef _LP64
aoqi@0 294 __ vmovdqu(Address(rsi, 64), xmm8);
aoqi@0 295 __ vmovdqu(Address(rsi, 96), xmm15);
aoqi@0 296 #endif
aoqi@0 297
aoqi@0 298 VM_Version::clean_cpuFeatures();
aoqi@0 299 UseAVX = saved_useavx;
aoqi@0 300 UseSSE = saved_usesse;
aoqi@0 301
aoqi@0 302 //
aoqi@0 303 // cpuid(0x7) Structured Extended Features
aoqi@0 304 //
aoqi@0 305 __ bind(sef_cpuid);
aoqi@0 306 __ movl(rax, 7);
aoqi@0 307 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
aoqi@0 308 __ jccb(Assembler::greater, ext_cpuid);
aoqi@0 309
aoqi@0 310 __ xorl(rcx, rcx);
aoqi@0 311 __ cpuid();
aoqi@0 312 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
aoqi@0 313 __ movl(Address(rsi, 0), rax);
aoqi@0 314 __ movl(Address(rsi, 4), rbx);
aoqi@0 315
aoqi@0 316 //
aoqi@0 317 // Extended cpuid(0x80000000)
aoqi@0 318 //
aoqi@0 319 __ bind(ext_cpuid);
aoqi@0 320 __ movl(rax, 0x80000000);
aoqi@0 321 __ cpuid();
aoqi@0 322 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
aoqi@0 323 __ jcc(Assembler::belowEqual, done);
aoqi@0 324 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
aoqi@0 325 __ jccb(Assembler::belowEqual, ext_cpuid1);
aoqi@0 326 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
aoqi@0 327 __ jccb(Assembler::belowEqual, ext_cpuid5);
aoqi@0 328 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
aoqi@0 329 __ jccb(Assembler::belowEqual, ext_cpuid7);
aoqi@0 330 //
aoqi@0 331 // Extended cpuid(0x80000008)
aoqi@0 332 //
aoqi@0 333 __ movl(rax, 0x80000008);
aoqi@0 334 __ cpuid();
aoqi@0 335 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
aoqi@0 336 __ movl(Address(rsi, 0), rax);
aoqi@0 337 __ movl(Address(rsi, 4), rbx);
aoqi@0 338 __ movl(Address(rsi, 8), rcx);
aoqi@0 339 __ movl(Address(rsi,12), rdx);
aoqi@0 340
aoqi@0 341 //
aoqi@0 342 // Extended cpuid(0x80000007)
aoqi@0 343 //
aoqi@0 344 __ bind(ext_cpuid7);
aoqi@0 345 __ movl(rax, 0x80000007);
aoqi@0 346 __ cpuid();
aoqi@0 347 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
aoqi@0 348 __ movl(Address(rsi, 0), rax);
aoqi@0 349 __ movl(Address(rsi, 4), rbx);
aoqi@0 350 __ movl(Address(rsi, 8), rcx);
aoqi@0 351 __ movl(Address(rsi,12), rdx);
aoqi@0 352
aoqi@0 353 //
aoqi@0 354 // Extended cpuid(0x80000005)
aoqi@0 355 //
aoqi@0 356 __ bind(ext_cpuid5);
aoqi@0 357 __ movl(rax, 0x80000005);
aoqi@0 358 __ cpuid();
aoqi@0 359 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
aoqi@0 360 __ movl(Address(rsi, 0), rax);
aoqi@0 361 __ movl(Address(rsi, 4), rbx);
aoqi@0 362 __ movl(Address(rsi, 8), rcx);
aoqi@0 363 __ movl(Address(rsi,12), rdx);
aoqi@0 364
aoqi@0 365 //
aoqi@0 366 // Extended cpuid(0x80000001)
aoqi@0 367 //
aoqi@0 368 __ bind(ext_cpuid1);
aoqi@0 369 __ movl(rax, 0x80000001);
aoqi@0 370 __ cpuid();
aoqi@0 371 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
aoqi@0 372 __ movl(Address(rsi, 0), rax);
aoqi@0 373 __ movl(Address(rsi, 4), rbx);
aoqi@0 374 __ movl(Address(rsi, 8), rcx);
aoqi@0 375 __ movl(Address(rsi,12), rdx);
aoqi@0 376
aoqi@0 377 //
aoqi@0 378 // return
aoqi@0 379 //
aoqi@0 380 __ bind(done);
aoqi@0 381 __ popf();
aoqi@0 382 __ pop(rsi);
aoqi@0 383 __ pop(rbx);
aoqi@0 384 __ pop(rbp);
aoqi@0 385 __ ret(0);
aoqi@0 386
aoqi@0 387 # undef __
aoqi@0 388
aoqi@0 389 return start;
aoqi@0 390 };
aoqi@0 391 };
aoqi@0 392
aoqi@0 393
aoqi@0 394 void VM_Version::get_cpu_info_wrapper() {
aoqi@0 395 get_cpu_info_stub(&_cpuid_info);
aoqi@0 396 }
aoqi@0 397
aoqi@0 398 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED
aoqi@0 399 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f()
aoqi@0 400 #endif
aoqi@0 401
aoqi@0 402 void VM_Version::get_processor_features() {
aoqi@0 403
aoqi@0 404 _cpu = 4; // 486 by default
aoqi@0 405 _model = 0;
aoqi@0 406 _stepping = 0;
aoqi@0 407 _cpuFeatures = 0;
aoqi@0 408 _logical_processors_per_package = 1;
aoqi@0 409
aoqi@0 410 if (!Use486InstrsOnly) {
aoqi@0 411 // Get raw processor info
aoqi@0 412
aoqi@0 413 // Some platforms (like Win*) need a wrapper around here
aoqi@0 414 // in order to properly handle SEGV for YMM registers test.
aoqi@0 415 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper);
aoqi@0 416
aoqi@0 417 assert_is_initialized();
aoqi@0 418 _cpu = extended_cpu_family();
aoqi@0 419 _model = extended_cpu_model();
aoqi@0 420 _stepping = cpu_stepping();
aoqi@0 421
aoqi@0 422 if (cpu_family() > 4) { // it supports CPUID
aoqi@0 423 _cpuFeatures = feature_flags();
aoqi@0 424 // Logical processors are only available on P4s and above,
aoqi@0 425 // and only if hyperthreading is available.
aoqi@0 426 _logical_processors_per_package = logical_processor_count();
aoqi@0 427 }
aoqi@0 428 }
aoqi@0 429
aoqi@0 430 _supports_cx8 = supports_cmpxchg8();
aoqi@0 431 // xchg and xadd instructions
aoqi@0 432 _supports_atomic_getset4 = true;
aoqi@0 433 _supports_atomic_getadd4 = true;
aoqi@0 434 LP64_ONLY(_supports_atomic_getset8 = true);
aoqi@0 435 LP64_ONLY(_supports_atomic_getadd8 = true);
aoqi@0 436
aoqi@0 437 #ifdef _LP64
aoqi@0 438 // OS should support SSE for x64 and hardware should support at least SSE2.
aoqi@0 439 if (!VM_Version::supports_sse2()) {
aoqi@0 440 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
aoqi@0 441 }
aoqi@0 442 // in 64 bit the use of SSE2 is the minimum
aoqi@0 443 if (UseSSE < 2) UseSSE = 2;
aoqi@0 444 #endif
aoqi@0 445
aoqi@0 446 #ifdef AMD64
aoqi@0 447 // flush_icache_stub have to be generated first.
aoqi@0 448 // That is why Icache line size is hard coded in ICache class,
aoqi@0 449 // see icache_x86.hpp. It is also the reason why we can't use
aoqi@0 450 // clflush instruction in 32-bit VM since it could be running
aoqi@0 451 // on CPU which does not support it.
aoqi@0 452 //
aoqi@0 453 // The only thing we can do is to verify that flushed
aoqi@0 454 // ICache::line_size has correct value.
aoqi@0 455 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
aoqi@0 456 // clflush_size is size in quadwords (8 bytes).
aoqi@0 457 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
aoqi@0 458 #endif
aoqi@0 459
aoqi@0 460 // If the OS doesn't support SSE, we can't use this feature even if the HW does
aoqi@0 461 if (!os::supports_sse())
aoqi@0 462 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
aoqi@0 463
aoqi@0 464 if (UseSSE < 4) {
aoqi@0 465 _cpuFeatures &= ~CPU_SSE4_1;
aoqi@0 466 _cpuFeatures &= ~CPU_SSE4_2;
aoqi@0 467 }
aoqi@0 468
aoqi@0 469 if (UseSSE < 3) {
aoqi@0 470 _cpuFeatures &= ~CPU_SSE3;
aoqi@0 471 _cpuFeatures &= ~CPU_SSSE3;
aoqi@0 472 _cpuFeatures &= ~CPU_SSE4A;
aoqi@0 473 }
aoqi@0 474
aoqi@0 475 if (UseSSE < 2)
aoqi@0 476 _cpuFeatures &= ~CPU_SSE2;
aoqi@0 477
aoqi@0 478 if (UseSSE < 1)
aoqi@0 479 _cpuFeatures &= ~CPU_SSE;
aoqi@0 480
aoqi@0 481 if (UseAVX < 2)
aoqi@0 482 _cpuFeatures &= ~CPU_AVX2;
aoqi@0 483
aoqi@0 484 if (UseAVX < 1)
aoqi@0 485 _cpuFeatures &= ~CPU_AVX;
aoqi@0 486
aoqi@0 487 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
aoqi@0 488 _cpuFeatures &= ~CPU_AES;
aoqi@0 489
aoqi@0 490 if (logical_processors_per_package() == 1) {
aoqi@0 491 // HT processor could be installed on a system which doesn't support HT.
aoqi@0 492 _cpuFeatures &= ~CPU_HT;
aoqi@0 493 }
aoqi@0 494
aoqi@0 495 char buf[256];
aoqi@0 496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
aoqi@0 497 cores_per_cpu(), threads_per_core(),
aoqi@0 498 cpu_family(), _model, _stepping,
aoqi@0 499 (supports_cmov() ? ", cmov" : ""),
aoqi@0 500 (supports_cmpxchg8() ? ", cx8" : ""),
aoqi@0 501 (supports_fxsr() ? ", fxsr" : ""),
aoqi@0 502 (supports_mmx() ? ", mmx" : ""),
aoqi@0 503 (supports_sse() ? ", sse" : ""),
aoqi@0 504 (supports_sse2() ? ", sse2" : ""),
aoqi@0 505 (supports_sse3() ? ", sse3" : ""),
aoqi@0 506 (supports_ssse3()? ", ssse3": ""),
aoqi@0 507 (supports_sse4_1() ? ", sse4.1" : ""),
aoqi@0 508 (supports_sse4_2() ? ", sse4.2" : ""),
aoqi@0 509 (supports_popcnt() ? ", popcnt" : ""),
aoqi@0 510 (supports_avx() ? ", avx" : ""),
aoqi@0 511 (supports_avx2() ? ", avx2" : ""),
aoqi@0 512 (supports_aes() ? ", aes" : ""),
aoqi@0 513 (supports_clmul() ? ", clmul" : ""),
aoqi@0 514 (supports_erms() ? ", erms" : ""),
aoqi@0 515 (supports_rtm() ? ", rtm" : ""),
aoqi@0 516 (supports_mmx_ext() ? ", mmxext" : ""),
aoqi@0 517 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
aoqi@0 518 (supports_lzcnt() ? ", lzcnt": ""),
aoqi@0 519 (supports_sse4a() ? ", sse4a": ""),
aoqi@0 520 (supports_ht() ? ", ht": ""),
aoqi@0 521 (supports_tsc() ? ", tsc": ""),
aoqi@0 522 (supports_tscinv_bit() ? ", tscinvbit": ""),
aoqi@0 523 (supports_tscinv() ? ", tscinv": ""),
aoqi@0 524 (supports_bmi1() ? ", bmi1" : ""),
aoqi@0 525 (supports_bmi2() ? ", bmi2" : ""));
aoqi@0 526 _features_str = strdup(buf);
aoqi@0 527
aoqi@0 528 // UseSSE is set to the smaller of what hardware supports and what
aoqi@0 529 // the command line requires. I.e., you cannot set UseSSE to 2 on
aoqi@0 530 // older Pentiums which do not support it.
aoqi@0 531 if (UseSSE > 4) UseSSE=4;
aoqi@0 532 if (UseSSE < 0) UseSSE=0;
aoqi@0 533 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
aoqi@0 534 UseSSE = MIN2((intx)3,UseSSE);
aoqi@0 535 if (!supports_sse3()) // Drop to 2 if no SSE3 support
aoqi@0 536 UseSSE = MIN2((intx)2,UseSSE);
aoqi@0 537 if (!supports_sse2()) // Drop to 1 if no SSE2 support
aoqi@0 538 UseSSE = MIN2((intx)1,UseSSE);
aoqi@0 539 if (!supports_sse ()) // Drop to 0 if no SSE support
aoqi@0 540 UseSSE = 0;
aoqi@0 541
aoqi@0 542 if (UseAVX > 2) UseAVX=2;
aoqi@0 543 if (UseAVX < 0) UseAVX=0;
aoqi@0 544 if (!supports_avx2()) // Drop to 1 if no AVX2 support
aoqi@0 545 UseAVX = MIN2((intx)1,UseAVX);
aoqi@0 546 if (!supports_avx ()) // Drop to 0 if no AVX support
aoqi@0 547 UseAVX = 0;
aoqi@0 548
aoqi@0 549 // Use AES instructions if available.
aoqi@0 550 if (supports_aes()) {
aoqi@0 551 if (FLAG_IS_DEFAULT(UseAES)) {
aoqi@0 552 UseAES = true;
aoqi@0 553 }
aoqi@0 554 } else if (UseAES) {
aoqi@0 555 if (!FLAG_IS_DEFAULT(UseAES))
aoqi@0 556 warning("AES instructions are not available on this CPU");
aoqi@0 557 FLAG_SET_DEFAULT(UseAES, false);
aoqi@0 558 }
aoqi@0 559
aoqi@0 560 // Use CLMUL instructions if available.
aoqi@0 561 if (supports_clmul()) {
aoqi@0 562 if (FLAG_IS_DEFAULT(UseCLMUL)) {
aoqi@0 563 UseCLMUL = true;
aoqi@0 564 }
aoqi@0 565 } else if (UseCLMUL) {
aoqi@0 566 if (!FLAG_IS_DEFAULT(UseCLMUL))
aoqi@0 567 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
aoqi@0 568 FLAG_SET_DEFAULT(UseCLMUL, false);
aoqi@0 569 }
aoqi@0 570
aoqi@0 571 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
aoqi@0 572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
aoqi@0 573 UseCRC32Intrinsics = true;
aoqi@0 574 }
aoqi@0 575 } else if (UseCRC32Intrinsics) {
aoqi@0 576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
aoqi@0 577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
aoqi@0 578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
aoqi@0 579 }
aoqi@0 580
aoqi@0 581 // The AES intrinsic stubs require AES instruction support (of course)
aoqi@0 582 // but also require sse3 mode for instructions it use.
aoqi@0 583 if (UseAES && (UseSSE > 2)) {
aoqi@0 584 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
aoqi@0 585 UseAESIntrinsics = true;
aoqi@0 586 }
aoqi@0 587 } else if (UseAESIntrinsics) {
aoqi@0 588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
aoqi@0 589 warning("AES intrinsics are not available on this CPU");
aoqi@0 590 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
aoqi@0 591 }
aoqi@0 592
aoqi@0 593 // Adjust RTM (Restricted Transactional Memory) flags
aoqi@0 594 if (!supports_rtm() && UseRTMLocking) {
aoqi@0 595 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
aoqi@0 596 // setting during arguments processing. See use_biased_locking().
aoqi@0 597 // VM_Version_init() is executed after UseBiasedLocking is used
aoqi@0 598 // in Thread::allocate().
aoqi@0 599 vm_exit_during_initialization("RTM instructions are not available on this CPU");
aoqi@0 600 }
aoqi@0 601
aoqi@0 602 #if INCLUDE_RTM_OPT
aoqi@0 603 if (UseRTMLocking) {
aoqi@0 604 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
aoqi@0 605 // RTM locking should be used only for applications with
aoqi@0 606 // high lock contention. For now we do not use it by default.
aoqi@0 607 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
aoqi@0 608 }
aoqi@0 609 if (!is_power_of_2(RTMTotalCountIncrRate)) {
aoqi@0 610 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
aoqi@0 611 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
aoqi@0 612 }
aoqi@0 613 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
aoqi@0 614 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
aoqi@0 615 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
aoqi@0 616 }
aoqi@0 617 } else { // !UseRTMLocking
aoqi@0 618 if (UseRTMForStackLocks) {
aoqi@0 619 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
aoqi@0 620 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
aoqi@0 621 }
aoqi@0 622 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
aoqi@0 623 }
aoqi@0 624 if (UseRTMDeopt) {
aoqi@0 625 FLAG_SET_DEFAULT(UseRTMDeopt, false);
aoqi@0 626 }
aoqi@0 627 if (PrintPreciseRTMLockingStatistics) {
aoqi@0 628 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
aoqi@0 629 }
aoqi@0 630 }
aoqi@0 631 #else
aoqi@0 632 if (UseRTMLocking) {
aoqi@0 633 // Only C2 does RTM locking optimization.
aoqi@0 634 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
aoqi@0 635 // setting during arguments processing. See use_biased_locking().
aoqi@0 636 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
aoqi@0 637 }
aoqi@0 638 #endif
aoqi@0 639
aoqi@0 640 #ifdef COMPILER2
aoqi@0 641 if (UseFPUForSpilling) {
aoqi@0 642 if (UseSSE < 2) {
aoqi@0 643 // Only supported with SSE2+
aoqi@0 644 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
aoqi@0 645 }
aoqi@0 646 }
aoqi@0 647 if (MaxVectorSize > 0) {
aoqi@0 648 if (!is_power_of_2(MaxVectorSize)) {
aoqi@0 649 warning("MaxVectorSize must be a power of 2");
aoqi@0 650 FLAG_SET_DEFAULT(MaxVectorSize, 32);
aoqi@0 651 }
aoqi@0 652 if (MaxVectorSize > 32) {
aoqi@0 653 FLAG_SET_DEFAULT(MaxVectorSize, 32);
aoqi@0 654 }
aoqi@0 655 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
aoqi@0 656 // 32 bytes vectors (in YMM) are only supported with AVX+
aoqi@0 657 FLAG_SET_DEFAULT(MaxVectorSize, 16);
aoqi@0 658 }
aoqi@0 659 if (UseSSE < 2) {
aoqi@0 660 // Vectors (in XMM) are only supported with SSE2+
aoqi@0 661 FLAG_SET_DEFAULT(MaxVectorSize, 0);
aoqi@0 662 }
aoqi@0 663 #ifdef ASSERT
aoqi@0 664 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
aoqi@0 665 tty->print_cr("State of YMM registers after signal handle:");
aoqi@0 666 int nreg = 2 LP64_ONLY(+2);
aoqi@0 667 const char* ymm_name[4] = {"0", "7", "8", "15"};
aoqi@0 668 for (int i = 0; i < nreg; i++) {
aoqi@0 669 tty->print("YMM%s:", ymm_name[i]);
aoqi@0 670 for (int j = 7; j >=0; j--) {
aoqi@0 671 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
aoqi@0 672 }
aoqi@0 673 tty->cr();
aoqi@0 674 }
aoqi@0 675 }
aoqi@0 676 #endif
aoqi@0 677 }
aoqi@0 678 #endif
aoqi@0 679
aoqi@0 680 // On new cpus instructions which update whole XMM register should be used
aoqi@0 681 // to prevent partial register stall due to dependencies on high half.
aoqi@0 682 //
aoqi@0 683 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
aoqi@0 684 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
aoqi@0 685 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
aoqi@0 686 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
aoqi@0 687
aoqi@0 688 if( is_amd() ) { // AMD cpus specific settings
aoqi@0 689 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
aoqi@0 690 // Use it on new AMD cpus starting from Opteron.
aoqi@0 691 UseAddressNop = true;
aoqi@0 692 }
aoqi@0 693 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
aoqi@0 694 // Use it on new AMD cpus starting from Opteron.
aoqi@0 695 UseNewLongLShift = true;
aoqi@0 696 }
aoqi@0 697 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
aoqi@0 698 if( supports_sse4a() ) {
aoqi@0 699 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
aoqi@0 700 } else {
aoqi@0 701 UseXmmLoadAndClearUpper = false;
aoqi@0 702 }
aoqi@0 703 }
aoqi@0 704 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
aoqi@0 705 if( supports_sse4a() ) {
aoqi@0 706 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
aoqi@0 707 } else {
aoqi@0 708 UseXmmRegToRegMoveAll = false;
aoqi@0 709 }
aoqi@0 710 }
aoqi@0 711 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
aoqi@0 712 if( supports_sse4a() ) {
aoqi@0 713 UseXmmI2F = true;
aoqi@0 714 } else {
aoqi@0 715 UseXmmI2F = false;
aoqi@0 716 }
aoqi@0 717 }
aoqi@0 718 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
aoqi@0 719 if( supports_sse4a() ) {
aoqi@0 720 UseXmmI2D = true;
aoqi@0 721 } else {
aoqi@0 722 UseXmmI2D = false;
aoqi@0 723 }
aoqi@0 724 }
aoqi@0 725 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
aoqi@0 726 if( supports_sse4_2() && UseSSE >= 4 ) {
aoqi@0 727 UseSSE42Intrinsics = true;
aoqi@0 728 }
aoqi@0 729 }
aoqi@0 730
aoqi@0 731 // some defaults for AMD family 15h
aoqi@0 732 if ( cpu_family() == 0x15 ) {
aoqi@0 733 // On family 15h processors default is no sw prefetch
aoqi@0 734 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
aoqi@0 735 AllocatePrefetchStyle = 0;
aoqi@0 736 }
aoqi@0 737 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
aoqi@0 738 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
aoqi@0 739 AllocatePrefetchInstr = 3;
aoqi@0 740 }
aoqi@0 741 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
aoqi@0 742 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
aoqi@0 743 UseXMMForArrayCopy = true;
aoqi@0 744 }
aoqi@0 745 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
aoqi@0 746 UseUnalignedLoadStores = true;
aoqi@0 747 }
aoqi@0 748 }
aoqi@0 749
aoqi@0 750 #ifdef COMPILER2
aoqi@0 751 if (MaxVectorSize > 16) {
aoqi@0 752 // Limit vectors size to 16 bytes on current AMD cpus.
aoqi@0 753 FLAG_SET_DEFAULT(MaxVectorSize, 16);
aoqi@0 754 }
aoqi@0 755 #endif // COMPILER2
aoqi@0 756 }
aoqi@0 757
aoqi@0 758 if( is_intel() ) { // Intel cpus specific settings
aoqi@0 759 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
aoqi@0 760 UseStoreImmI16 = false; // don't use it on Intel cpus
aoqi@0 761 }
aoqi@0 762 if( cpu_family() == 6 || cpu_family() == 15 ) {
aoqi@0 763 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
aoqi@0 764 // Use it on all Intel cpus starting from PentiumPro
aoqi@0 765 UseAddressNop = true;
aoqi@0 766 }
aoqi@0 767 }
aoqi@0 768 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
aoqi@0 769 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
aoqi@0 770 }
aoqi@0 771 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
aoqi@0 772 if( supports_sse3() ) {
aoqi@0 773 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
aoqi@0 774 } else {
aoqi@0 775 UseXmmRegToRegMoveAll = false;
aoqi@0 776 }
aoqi@0 777 }
aoqi@0 778 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
aoqi@0 779 #ifdef COMPILER2
aoqi@0 780 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
aoqi@0 781 // For new Intel cpus do the next optimization:
aoqi@0 782 // don't align the beginning of a loop if there are enough instructions
aoqi@0 783 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
aoqi@0 784 // in current fetch line (OptoLoopAlignment) or the padding
aoqi@0 785 // is big (> MaxLoopPad).
aoqi@0 786 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
aoqi@0 787 // generated NOP instructions. 11 is the largest size of one
aoqi@0 788 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
aoqi@0 789 MaxLoopPad = 11;
aoqi@0 790 }
aoqi@0 791 #endif // COMPILER2
aoqi@0 792 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
aoqi@0 793 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
aoqi@0 794 }
aoqi@0 795 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
aoqi@0 796 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
aoqi@0 797 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
aoqi@0 798 }
aoqi@0 799 }
aoqi@0 800 if (supports_sse4_2() && UseSSE >= 4) {
aoqi@0 801 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
aoqi@0 802 UseSSE42Intrinsics = true;
aoqi@0 803 }
aoqi@0 804 }
aoqi@0 805 }
aoqi@0 806 }
aoqi@0 807
aoqi@0 808 // Use count leading zeros count instruction if available.
aoqi@0 809 if (supports_lzcnt()) {
aoqi@0 810 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
aoqi@0 811 UseCountLeadingZerosInstruction = true;
aoqi@0 812 }
aoqi@0 813 } else if (UseCountLeadingZerosInstruction) {
aoqi@0 814 warning("lzcnt instruction is not available on this CPU");
aoqi@0 815 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
aoqi@0 816 }
aoqi@0 817
aoqi@0 818 if (supports_bmi1()) {
aoqi@0 819 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
aoqi@0 820 UseBMI1Instructions = true;
aoqi@0 821 }
aoqi@0 822 } else if (UseBMI1Instructions) {
aoqi@0 823 warning("BMI1 instructions are not available on this CPU");
aoqi@0 824 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
aoqi@0 825 }
aoqi@0 826
aoqi@0 827 // Use count trailing zeros instruction if available
aoqi@0 828 if (supports_bmi1()) {
aoqi@0 829 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
aoqi@0 830 UseCountTrailingZerosInstruction = UseBMI1Instructions;
aoqi@0 831 }
aoqi@0 832 } else if (UseCountTrailingZerosInstruction) {
aoqi@0 833 warning("tzcnt instruction is not available on this CPU");
aoqi@0 834 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
aoqi@0 835 }
aoqi@0 836
aoqi@0 837 // Use population count instruction if available.
aoqi@0 838 if (supports_popcnt()) {
aoqi@0 839 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
aoqi@0 840 UsePopCountInstruction = true;
aoqi@0 841 }
aoqi@0 842 } else if (UsePopCountInstruction) {
aoqi@0 843 warning("POPCNT instruction is not available on this CPU");
aoqi@0 844 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
aoqi@0 845 }
aoqi@0 846
aoqi@0 847 // Use fast-string operations if available.
aoqi@0 848 if (supports_erms()) {
aoqi@0 849 if (FLAG_IS_DEFAULT(UseFastStosb)) {
aoqi@0 850 UseFastStosb = true;
aoqi@0 851 }
aoqi@0 852 } else if (UseFastStosb) {
aoqi@0 853 warning("fast-string operations are not available on this CPU");
aoqi@0 854 FLAG_SET_DEFAULT(UseFastStosb, false);
aoqi@0 855 }
aoqi@0 856
aoqi@0 857 #ifdef COMPILER2
aoqi@0 858 if (FLAG_IS_DEFAULT(AlignVector)) {
aoqi@0 859 // Modern processors allow misaligned memory operations for vectors.
aoqi@0 860 AlignVector = !UseUnalignedLoadStores;
aoqi@0 861 }
aoqi@0 862 #endif // COMPILER2
aoqi@0 863
aoqi@0 864 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
aoqi@0 865 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
aoqi@0 866
aoqi@0 867 // set valid Prefetch instruction
aoqi@0 868 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
aoqi@0 869 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
aoqi@0 870 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
aoqi@0 871 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
aoqi@0 872
aoqi@0 873 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
aoqi@0 874 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
aoqi@0 875 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
aoqi@0 876 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
aoqi@0 877
aoqi@0 878 // Allocation prefetch settings
aoqi@0 879 intx cache_line_size = prefetch_data_size();
aoqi@0 880 if( cache_line_size > AllocatePrefetchStepSize )
aoqi@0 881 AllocatePrefetchStepSize = cache_line_size;
aoqi@0 882
aoqi@0 883 assert(AllocatePrefetchLines > 0, "invalid value");
aoqi@0 884 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
aoqi@0 885 AllocatePrefetchLines = 3;
aoqi@0 886 assert(AllocateInstancePrefetchLines > 0, "invalid value");
aoqi@0 887 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
aoqi@0 888 AllocateInstancePrefetchLines = 1;
aoqi@0 889
aoqi@0 890 AllocatePrefetchDistance = allocate_prefetch_distance();
aoqi@0 891 AllocatePrefetchStyle = allocate_prefetch_style();
aoqi@0 892
aoqi@0 893 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
aoqi@0 894 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
aoqi@0 895 #ifdef _LP64
aoqi@0 896 AllocatePrefetchDistance = 384;
aoqi@0 897 #else
aoqi@0 898 AllocatePrefetchDistance = 320;
aoqi@0 899 #endif
aoqi@0 900 }
aoqi@0 901 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
aoqi@0 902 AllocatePrefetchDistance = 192;
aoqi@0 903 AllocatePrefetchLines = 4;
aoqi@0 904 #ifdef COMPILER2
aoqi@0 905 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
aoqi@0 906 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
aoqi@0 907 }
aoqi@0 908 #endif
aoqi@0 909 }
aoqi@0 910 }
aoqi@0 911 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
aoqi@0 912
aoqi@0 913 #ifdef _LP64
aoqi@0 914 // Prefetch settings
aoqi@0 915 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
aoqi@0 916 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
aoqi@0 917 PrefetchFieldsAhead = prefetch_fields_ahead();
aoqi@0 918 #endif
aoqi@0 919
aoqi@0 920 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
aoqi@0 921 (cache_line_size > ContendedPaddingWidth))
aoqi@0 922 ContendedPaddingWidth = cache_line_size;
aoqi@0 923
aoqi@0 924 #ifndef PRODUCT
aoqi@0 925 if (PrintMiscellaneous && Verbose) {
aoqi@0 926 tty->print_cr("Logical CPUs per core: %u",
aoqi@0 927 logical_processors_per_package());
aoqi@0 928 tty->print("UseSSE=%d", (int) UseSSE);
aoqi@0 929 if (UseAVX > 0) {
aoqi@0 930 tty->print(" UseAVX=%d", (int) UseAVX);
aoqi@0 931 }
aoqi@0 932 if (UseAES) {
aoqi@0 933 tty->print(" UseAES=1");
aoqi@0 934 }
aoqi@0 935 #ifdef COMPILER2
aoqi@0 936 if (MaxVectorSize > 0) {
aoqi@0 937 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize);
aoqi@0 938 }
aoqi@0 939 #endif
aoqi@0 940 tty->cr();
aoqi@0 941 tty->print("Allocation");
aoqi@0 942 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
aoqi@0 943 tty->print_cr(": no prefetching");
aoqi@0 944 } else {
aoqi@0 945 tty->print(" prefetching: ");
aoqi@0 946 if (UseSSE == 0 && supports_3dnow_prefetch()) {
aoqi@0 947 tty->print("PREFETCHW");
aoqi@0 948 } else if (UseSSE >= 1) {
aoqi@0 949 if (AllocatePrefetchInstr == 0) {
aoqi@0 950 tty->print("PREFETCHNTA");
aoqi@0 951 } else if (AllocatePrefetchInstr == 1) {
aoqi@0 952 tty->print("PREFETCHT0");
aoqi@0 953 } else if (AllocatePrefetchInstr == 2) {
aoqi@0 954 tty->print("PREFETCHT2");
aoqi@0 955 } else if (AllocatePrefetchInstr == 3) {
aoqi@0 956 tty->print("PREFETCHW");
aoqi@0 957 }
aoqi@0 958 }
aoqi@0 959 if (AllocatePrefetchLines > 1) {
aoqi@0 960 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
aoqi@0 961 } else {
aoqi@0 962 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
aoqi@0 963 }
aoqi@0 964 }
aoqi@0 965
aoqi@0 966 if (PrefetchCopyIntervalInBytes > 0) {
aoqi@0 967 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
aoqi@0 968 }
aoqi@0 969 if (PrefetchScanIntervalInBytes > 0) {
aoqi@0 970 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
aoqi@0 971 }
aoqi@0 972 if (PrefetchFieldsAhead > 0) {
aoqi@0 973 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
aoqi@0 974 }
aoqi@0 975 if (ContendedPaddingWidth > 0) {
aoqi@0 976 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
aoqi@0 977 }
aoqi@0 978 }
aoqi@0 979 #endif // !PRODUCT
aoqi@0 980 }
aoqi@0 981
aoqi@0 982 bool VM_Version::use_biased_locking() {
aoqi@0 983 #if INCLUDE_RTM_OPT
aoqi@0 984 // RTM locking is most useful when there is high lock contention and
aoqi@0 985 // low data contention. With high lock contention the lock is usually
aoqi@0 986 // inflated and biased locking is not suitable for that case.
aoqi@0 987 // RTM locking code requires that biased locking is off.
aoqi@0 988 // Note: we can't switch off UseBiasedLocking in get_processor_features()
aoqi@0 989 // because it is used by Thread::allocate() which is called before
aoqi@0 990 // VM_Version::initialize().
aoqi@0 991 if (UseRTMLocking && UseBiasedLocking) {
aoqi@0 992 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
aoqi@0 993 FLAG_SET_DEFAULT(UseBiasedLocking, false);
aoqi@0 994 } else {
aoqi@0 995 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
aoqi@0 996 UseBiasedLocking = false;
aoqi@0 997 }
aoqi@0 998 }
aoqi@0 999 #endif
aoqi@0 1000 return UseBiasedLocking;
aoqi@0 1001 }
aoqi@0 1002
aoqi@0 1003 void VM_Version::initialize() {
aoqi@0 1004 ResourceMark rm;
aoqi@0 1005 // Making this stub must be FIRST use of assembler
aoqi@0 1006
aoqi@0 1007 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
aoqi@0 1008 if (stub_blob == NULL) {
aoqi@0 1009 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
aoqi@0 1010 }
aoqi@0 1011 CodeBuffer c(stub_blob);
aoqi@0 1012 VM_Version_StubGenerator g(&c);
aoqi@0 1013 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
aoqi@0 1014 g.generate_get_cpu_info());
aoqi@0 1015
aoqi@0 1016 get_processor_features();
aoqi@0 1017 }

Mercurial Repository: jdk8-mips64-public/hotspot

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