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src/cpu/x86/vm/vm_version_x86.hpp@70aa912cebe5 (annotated)

src/cpu/x86/vm/vm_version_x86.hpp

Wed, 15 Apr 2020 11:49:55 +0800

author
aoqi
date
Wed, 15 Apr 2020 11:49:55 +0800
changeset 9852
70aa912cebe5
parent 8856
ac27a9c85bea
permissions
-rw-r--r--

Merge

aoqi@0 1 /*
kevinw@8729 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 4 *
aoqi@0 5 * This code is free software; you can redistribute it and/or modify it
aoqi@0 6 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 7 * published by the Free Software Foundation.
aoqi@0 8 *
aoqi@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 12 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 13 * accompanied this code).
aoqi@0 14 *
aoqi@0 15 * You should have received a copy of the GNU General Public License version
aoqi@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 18 *
aoqi@0 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 20 * or visit www.oracle.com if you need additional information or have any
aoqi@0 21 * questions.
aoqi@0 22 *
aoqi@0 23 */
aoqi@0 24
aoqi@0 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
aoqi@0 26 #define CPU_X86_VM_VM_VERSION_X86_HPP
aoqi@0 27
aoqi@0 28 #include "runtime/globals_extension.hpp"
aoqi@0 29 #include "runtime/vm_version.hpp"
aoqi@0 30
aoqi@0 31 class VM_Version : public Abstract_VM_Version {
aoqi@0 32 public:
aoqi@0 33 // cpuid result register layouts. These are all unions of a uint32_t
aoqi@0 34 // (in case anyone wants access to the register as a whole) and a bitfield.
aoqi@0 35
aoqi@0 36 union StdCpuid1Eax {
aoqi@0 37 uint32_t value;
aoqi@0 38 struct {
aoqi@0 39 uint32_t stepping : 4,
aoqi@0 40 model : 4,
aoqi@0 41 family : 4,
aoqi@0 42 proc_type : 2,
aoqi@0 43 : 2,
aoqi@0 44 ext_model : 4,
aoqi@0 45 ext_family : 8,
aoqi@0 46 : 4;
aoqi@0 47 } bits;
aoqi@0 48 };
aoqi@0 49
aoqi@0 50 union StdCpuid1Ebx { // example, unused
aoqi@0 51 uint32_t value;
aoqi@0 52 struct {
aoqi@0 53 uint32_t brand_id : 8,
aoqi@0 54 clflush_size : 8,
aoqi@0 55 threads_per_cpu : 8,
aoqi@0 56 apic_id : 8;
aoqi@0 57 } bits;
aoqi@0 58 };
aoqi@0 59
aoqi@0 60 union StdCpuid1Ecx {
aoqi@0 61 uint32_t value;
aoqi@0 62 struct {
aoqi@0 63 uint32_t sse3 : 1,
aoqi@0 64 clmul : 1,
aoqi@0 65 : 1,
aoqi@0 66 monitor : 1,
aoqi@0 67 : 1,
aoqi@0 68 vmx : 1,
aoqi@0 69 : 1,
aoqi@0 70 est : 1,
aoqi@0 71 : 1,
aoqi@0 72 ssse3 : 1,
aoqi@0 73 cid : 1,
aoqi@0 74 : 2,
aoqi@0 75 cmpxchg16: 1,
aoqi@0 76 : 4,
aoqi@0 77 dca : 1,
aoqi@0 78 sse4_1 : 1,
aoqi@0 79 sse4_2 : 1,
aoqi@0 80 : 2,
aoqi@0 81 popcnt : 1,
aoqi@0 82 : 1,
aoqi@0 83 aes : 1,
aoqi@0 84 : 1,
aoqi@0 85 osxsave : 1,
aoqi@0 86 avx : 1,
aoqi@0 87 : 3;
aoqi@0 88 } bits;
aoqi@0 89 };
aoqi@0 90
aoqi@0 91 union StdCpuid1Edx {
aoqi@0 92 uint32_t value;
aoqi@0 93 struct {
aoqi@0 94 uint32_t : 4,
aoqi@0 95 tsc : 1,
aoqi@0 96 : 3,
aoqi@0 97 cmpxchg8 : 1,
aoqi@0 98 : 6,
aoqi@0 99 cmov : 1,
aoqi@0 100 : 3,
aoqi@0 101 clflush : 1,
aoqi@0 102 : 3,
aoqi@0 103 mmx : 1,
aoqi@0 104 fxsr : 1,
aoqi@0 105 sse : 1,
aoqi@0 106 sse2 : 1,
aoqi@0 107 : 1,
aoqi@0 108 ht : 1,
aoqi@0 109 : 3;
aoqi@0 110 } bits;
aoqi@0 111 };
aoqi@0 112
aoqi@0 113 union DcpCpuid4Eax {
aoqi@0 114 uint32_t value;
aoqi@0 115 struct {
aoqi@0 116 uint32_t cache_type : 5,
aoqi@0 117 : 21,
aoqi@0 118 cores_per_cpu : 6;
aoqi@0 119 } bits;
aoqi@0 120 };
aoqi@0 121
aoqi@0 122 union DcpCpuid4Ebx {
aoqi@0 123 uint32_t value;
aoqi@0 124 struct {
aoqi@0 125 uint32_t L1_line_size : 12,
aoqi@0 126 partitions : 10,
aoqi@0 127 associativity : 10;
aoqi@0 128 } bits;
aoqi@0 129 };
aoqi@0 130
aoqi@0 131 union TplCpuidBEbx {
aoqi@0 132 uint32_t value;
aoqi@0 133 struct {
aoqi@0 134 uint32_t logical_cpus : 16,
aoqi@0 135 : 16;
aoqi@0 136 } bits;
aoqi@0 137 };
aoqi@0 138
aoqi@0 139 union ExtCpuid1Ecx {
aoqi@0 140 uint32_t value;
aoqi@0 141 struct {
aoqi@0 142 uint32_t LahfSahf : 1,
aoqi@0 143 CmpLegacy : 1,
aoqi@0 144 : 3,
aoqi@0 145 lzcnt_intel : 1,
aoqi@0 146 lzcnt : 1,
aoqi@0 147 sse4a : 1,
aoqi@0 148 misalignsse : 1,
aoqi@0 149 prefetchw : 1,
aoqi@0 150 : 22;
aoqi@0 151 } bits;
aoqi@0 152 };
aoqi@0 153
aoqi@0 154 union ExtCpuid1Edx {
aoqi@0 155 uint32_t value;
aoqi@0 156 struct {
aoqi@0 157 uint32_t : 22,
aoqi@0 158 mmx_amd : 1,
aoqi@0 159 mmx : 1,
aoqi@0 160 fxsr : 1,
aoqi@0 161 : 4,
aoqi@0 162 long_mode : 1,
aoqi@0 163 tdnow2 : 1,
aoqi@0 164 tdnow : 1;
aoqi@0 165 } bits;
aoqi@0 166 };
aoqi@0 167
aoqi@0 168 union ExtCpuid5Ex {
aoqi@0 169 uint32_t value;
aoqi@0 170 struct {
aoqi@0 171 uint32_t L1_line_size : 8,
aoqi@0 172 L1_tag_lines : 8,
aoqi@0 173 L1_assoc : 8,
aoqi@0 174 L1_size : 8;
aoqi@0 175 } bits;
aoqi@0 176 };
aoqi@0 177
aoqi@0 178 union ExtCpuid7Edx {
aoqi@0 179 uint32_t value;
aoqi@0 180 struct {
aoqi@0 181 uint32_t : 8,
aoqi@0 182 tsc_invariance : 1,
aoqi@0 183 : 23;
aoqi@0 184 } bits;
aoqi@0 185 };
aoqi@0 186
aoqi@0 187 union ExtCpuid8Ecx {
aoqi@0 188 uint32_t value;
aoqi@0 189 struct {
aoqi@0 190 uint32_t cores_per_cpu : 8,
aoqi@0 191 : 24;
aoqi@0 192 } bits;
aoqi@0 193 };
aoqi@0 194
aoqi@0 195 union SefCpuid7Eax {
aoqi@0 196 uint32_t value;
aoqi@0 197 };
aoqi@0 198
aoqi@0 199 union SefCpuid7Ebx {
aoqi@0 200 uint32_t value;
aoqi@0 201 struct {
aoqi@0 202 uint32_t fsgsbase : 1,
aoqi@0 203 : 2,
aoqi@0 204 bmi1 : 1,
aoqi@0 205 : 1,
aoqi@0 206 avx2 : 1,
aoqi@0 207 : 2,
aoqi@0 208 bmi2 : 1,
aoqi@0 209 erms : 1,
aoqi@0 210 : 1,
aoqi@0 211 rtm : 1,
kvn@7152 212 : 7,
kvn@7152 213 adx : 1,
kvn@7152 214 : 12;
aoqi@0 215 } bits;
aoqi@0 216 };
aoqi@0 217
aoqi@0 218 union XemXcr0Eax {
aoqi@0 219 uint32_t value;
aoqi@0 220 struct {
aoqi@0 221 uint32_t x87 : 1,
aoqi@0 222 sse : 1,
aoqi@0 223 ymm : 1,
aoqi@0 224 : 29;
aoqi@0 225 } bits;
aoqi@0 226 };
aoqi@0 227
aoqi@0 228 protected:
aoqi@0 229 static int _cpu;
aoqi@0 230 static int _model;
aoqi@0 231 static int _stepping;
aoqi@0 232 static int _cpuFeatures; // features returned by the "cpuid" instruction
aoqi@0 233 // 0 if this instruction is not available
aoqi@0 234 static const char* _features_str;
aoqi@0 235
aoqi@0 236 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
aoqi@0 237 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
aoqi@0 238
aoqi@0 239 enum {
aoqi@0 240 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
aoqi@0 241 CPU_CMOV = (1 << 1),
aoqi@0 242 CPU_FXSR = (1 << 2),
aoqi@0 243 CPU_HT = (1 << 3),
aoqi@0 244 CPU_MMX = (1 << 4),
aoqi@0 245 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
aoqi@0 246 // may not necessarily support other 3dnow instructions
aoqi@0 247 CPU_SSE = (1 << 6),
aoqi@0 248 CPU_SSE2 = (1 << 7),
aoqi@0 249 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
aoqi@0 250 CPU_SSSE3 = (1 << 9),
aoqi@0 251 CPU_SSE4A = (1 << 10),
aoqi@0 252 CPU_SSE4_1 = (1 << 11),
aoqi@0 253 CPU_SSE4_2 = (1 << 12),
aoqi@0 254 CPU_POPCNT = (1 << 13),
aoqi@0 255 CPU_LZCNT = (1 << 14),
aoqi@0 256 CPU_TSC = (1 << 15),
aoqi@0 257 CPU_TSCINV = (1 << 16),
aoqi@0 258 CPU_AVX = (1 << 17),
aoqi@0 259 CPU_AVX2 = (1 << 18),
aoqi@0 260 CPU_AES = (1 << 19),
aoqi@0 261 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
aoqi@0 262 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
aoqi@0 263 CPU_BMI1 = (1 << 22),
aoqi@0 264 CPU_BMI2 = (1 << 23),
kvn@7152 265 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
kvn@7152 266 CPU_ADX = (1 << 25)
aoqi@0 267 } cpuFeatureFlags;
aoqi@0 268
aoqi@0 269 enum {
aoqi@0 270 // AMD
aoqi@0 271 CPU_FAMILY_AMD_11H = 0x11,
aoqi@0 272 // Intel
aoqi@0 273 CPU_FAMILY_INTEL_CORE = 6,
aoqi@0 274 CPU_MODEL_NEHALEM = 0x1e,
aoqi@0 275 CPU_MODEL_NEHALEM_EP = 0x1a,
aoqi@0 276 CPU_MODEL_NEHALEM_EX = 0x2e,
aoqi@0 277 CPU_MODEL_WESTMERE = 0x25,
aoqi@0 278 CPU_MODEL_WESTMERE_EP = 0x2c,
aoqi@0 279 CPU_MODEL_WESTMERE_EX = 0x2f,
aoqi@0 280 CPU_MODEL_SANDYBRIDGE = 0x2a,
aoqi@0 281 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
kvn@7088 282 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
kvn@7088 283 CPU_MODEL_HASWELL_E3 = 0x3c,
kvn@7088 284 CPU_MODEL_HASWELL_E7 = 0x3f,
kvn@7088 285 CPU_MODEL_BROADWELL = 0x3d
aoqi@0 286 } cpuExtendedFamily;
aoqi@0 287
aoqi@0 288 // cpuid information block. All info derived from executing cpuid with
aoqi@0 289 // various function numbers is stored here. Intel and AMD info is
aoqi@0 290 // merged in this block: accessor methods disentangle it.
aoqi@0 291 //
aoqi@0 292 // The info block is laid out in subblocks of 4 dwords corresponding to
aoqi@0 293 // eax, ebx, ecx and edx, whether or not they contain anything useful.
aoqi@0 294 struct CpuidInfo {
aoqi@0 295 // cpuid function 0
aoqi@0 296 uint32_t std_max_function;
aoqi@0 297 uint32_t std_vendor_name_0;
aoqi@0 298 uint32_t std_vendor_name_1;
aoqi@0 299 uint32_t std_vendor_name_2;
aoqi@0 300
aoqi@0 301 // cpuid function 1
aoqi@0 302 StdCpuid1Eax std_cpuid1_eax;
aoqi@0 303 StdCpuid1Ebx std_cpuid1_ebx;
aoqi@0 304 StdCpuid1Ecx std_cpuid1_ecx;
aoqi@0 305 StdCpuid1Edx std_cpuid1_edx;
aoqi@0 306
aoqi@0 307 // cpuid function 4 (deterministic cache parameters)
aoqi@0 308 DcpCpuid4Eax dcp_cpuid4_eax;
aoqi@0 309 DcpCpuid4Ebx dcp_cpuid4_ebx;
aoqi@0 310 uint32_t dcp_cpuid4_ecx; // unused currently
aoqi@0 311 uint32_t dcp_cpuid4_edx; // unused currently
aoqi@0 312
aoqi@0 313 // cpuid function 7 (structured extended features)
aoqi@0 314 SefCpuid7Eax sef_cpuid7_eax;
aoqi@0 315 SefCpuid7Ebx sef_cpuid7_ebx;
aoqi@0 316 uint32_t sef_cpuid7_ecx; // unused currently
aoqi@0 317 uint32_t sef_cpuid7_edx; // unused currently
aoqi@0 318
aoqi@0 319 // cpuid function 0xB (processor topology)
aoqi@0 320 // ecx = 0
aoqi@0 321 uint32_t tpl_cpuidB0_eax;
aoqi@0 322 TplCpuidBEbx tpl_cpuidB0_ebx;
aoqi@0 323 uint32_t tpl_cpuidB0_ecx; // unused currently
aoqi@0 324 uint32_t tpl_cpuidB0_edx; // unused currently
aoqi@0 325
aoqi@0 326 // ecx = 1
aoqi@0 327 uint32_t tpl_cpuidB1_eax;
aoqi@0 328 TplCpuidBEbx tpl_cpuidB1_ebx;
aoqi@0 329 uint32_t tpl_cpuidB1_ecx; // unused currently
aoqi@0 330 uint32_t tpl_cpuidB1_edx; // unused currently
aoqi@0 331
aoqi@0 332 // ecx = 2
aoqi@0 333 uint32_t tpl_cpuidB2_eax;
aoqi@0 334 TplCpuidBEbx tpl_cpuidB2_ebx;
aoqi@0 335 uint32_t tpl_cpuidB2_ecx; // unused currently
aoqi@0 336 uint32_t tpl_cpuidB2_edx; // unused currently
aoqi@0 337
aoqi@0 338 // cpuid function 0x80000000 // example, unused
aoqi@0 339 uint32_t ext_max_function;
aoqi@0 340 uint32_t ext_vendor_name_0;
aoqi@0 341 uint32_t ext_vendor_name_1;
aoqi@0 342 uint32_t ext_vendor_name_2;
aoqi@0 343
aoqi@0 344 // cpuid function 0x80000001
aoqi@0 345 uint32_t ext_cpuid1_eax; // reserved
aoqi@0 346 uint32_t ext_cpuid1_ebx; // reserved
aoqi@0 347 ExtCpuid1Ecx ext_cpuid1_ecx;
aoqi@0 348 ExtCpuid1Edx ext_cpuid1_edx;
aoqi@0 349
aoqi@0 350 // cpuid functions 0x80000002 thru 0x80000004: example, unused
aoqi@0 351 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
aoqi@0 352 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
aoqi@0 353 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
aoqi@0 354
aoqi@0 355 // cpuid function 0x80000005 // AMD L1, Intel reserved
aoqi@0 356 uint32_t ext_cpuid5_eax; // unused currently
aoqi@0 357 uint32_t ext_cpuid5_ebx; // reserved
aoqi@0 358 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
aoqi@0 359 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
aoqi@0 360
aoqi@0 361 // cpuid function 0x80000007
aoqi@0 362 uint32_t ext_cpuid7_eax; // reserved
aoqi@0 363 uint32_t ext_cpuid7_ebx; // reserved
aoqi@0 364 uint32_t ext_cpuid7_ecx; // reserved
aoqi@0 365 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
aoqi@0 366
aoqi@0 367 // cpuid function 0x80000008
aoqi@0 368 uint32_t ext_cpuid8_eax; // unused currently
aoqi@0 369 uint32_t ext_cpuid8_ebx; // reserved
aoqi@0 370 ExtCpuid8Ecx ext_cpuid8_ecx;
aoqi@0 371 uint32_t ext_cpuid8_edx; // reserved
aoqi@0 372
aoqi@0 373 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
aoqi@0 374 XemXcr0Eax xem_xcr0_eax;
aoqi@0 375 uint32_t xem_xcr0_edx; // reserved
aoqi@0 376
aoqi@0 377 // Space to save ymm registers after signal handle
aoqi@0 378 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
aoqi@0 379 };
aoqi@0 380
aoqi@0 381 // The actual cpuid info block
aoqi@0 382 static CpuidInfo _cpuid_info;
aoqi@0 383
aoqi@0 384 // Extractors and predicates
aoqi@0 385 static uint32_t extended_cpu_family() {
aoqi@0 386 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
aoqi@0 387 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
aoqi@0 388 return result;
aoqi@0 389 }
aoqi@0 390
aoqi@0 391 static uint32_t extended_cpu_model() {
aoqi@0 392 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
aoqi@0 393 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
aoqi@0 394 return result;
aoqi@0 395 }
aoqi@0 396
aoqi@0 397 static uint32_t cpu_stepping() {
aoqi@0 398 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
aoqi@0 399 return result;
aoqi@0 400 }
aoqi@0 401
aoqi@0 402 static uint logical_processor_count() {
aoqi@0 403 uint result = threads_per_core();
aoqi@0 404 return result;
aoqi@0 405 }
aoqi@0 406
aoqi@0 407 static uint32_t feature_flags() {
aoqi@0 408 uint32_t result = 0;
aoqi@0 409 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
aoqi@0 410 result |= CPU_CX8;
aoqi@0 411 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
aoqi@0 412 result |= CPU_CMOV;
aoqi@0 413 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
aoqi@0 414 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
aoqi@0 415 result |= CPU_FXSR;
aoqi@0 416 // HT flag is set for multi-core processors also.
aoqi@0 417 if (threads_per_core() > 1)
aoqi@0 418 result |= CPU_HT;
aoqi@0 419 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
aoqi@0 420 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
aoqi@0 421 result |= CPU_MMX;
aoqi@0 422 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
aoqi@0 423 result |= CPU_SSE;
aoqi@0 424 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
aoqi@0 425 result |= CPU_SSE2;
aoqi@0 426 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
aoqi@0 427 result |= CPU_SSE3;
aoqi@0 428 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
aoqi@0 429 result |= CPU_SSSE3;
aoqi@0 430 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
aoqi@0 431 result |= CPU_SSE4_1;
aoqi@0 432 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
aoqi@0 433 result |= CPU_SSE4_2;
aoqi@0 434 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
aoqi@0 435 result |= CPU_POPCNT;
aoqi@0 436 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
aoqi@0 437 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
aoqi@0 438 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
aoqi@0 439 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
aoqi@0 440 result |= CPU_AVX;
aoqi@0 441 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
aoqi@0 442 result |= CPU_AVX2;
aoqi@0 443 }
aoqi@0 444 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
aoqi@0 445 result |= CPU_BMI1;
aoqi@0 446 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
aoqi@0 447 result |= CPU_TSC;
aoqi@0 448 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
aoqi@0 449 result |= CPU_TSCINV;
aoqi@0 450 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
aoqi@0 451 result |= CPU_AES;
aoqi@0 452 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
aoqi@0 453 result |= CPU_ERMS;
aoqi@0 454 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
aoqi@0 455 result |= CPU_CLMUL;
aoqi@0 456 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
aoqi@0 457 result |= CPU_RTM;
aoqi@0 458
aoqi@0 459 // AMD features.
aoqi@0 460 if (is_amd()) {
aoqi@0 461 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
aoqi@0 462 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
aoqi@0 463 result |= CPU_3DNOW_PREFETCH;
aoqi@0 464 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
aoqi@0 465 result |= CPU_LZCNT;
aoqi@0 466 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
aoqi@0 467 result |= CPU_SSE4A;
aoqi@0 468 }
aoqi@0 469 // Intel features.
aoqi@0 470 if(is_intel()) {
kvn@7152 471 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
kvn@7152 472 result |= CPU_ADX;
aoqi@0 473 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
aoqi@0 474 result |= CPU_BMI2;
aoqi@0 475 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
aoqi@0 476 result |= CPU_LZCNT;
kvn@7152 477 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
kvn@7152 478 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
kvn@7152 479 result |= CPU_3DNOW_PREFETCH;
kvn@7152 480 }
aoqi@0 481 }
aoqi@0 482
aoqi@0 483 return result;
aoqi@0 484 }
aoqi@0 485
aoqi@0 486 static bool os_supports_avx_vectors() {
aoqi@0 487 if (!supports_avx()) {
aoqi@0 488 return false;
aoqi@0 489 }
aoqi@0 490 // Verify that OS save/restore all bits of AVX registers
aoqi@0 491 // during signal processing.
aoqi@0 492 int nreg = 2 LP64_ONLY(+2);
aoqi@0 493 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
aoqi@0 494 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
aoqi@0 495 return false;
aoqi@0 496 }
aoqi@0 497 }
aoqi@0 498 return true;
aoqi@0 499 }
aoqi@0 500
aoqi@0 501 static void get_processor_features();
aoqi@0 502
aoqi@0 503 public:
aoqi@0 504 // Offsets for cpuid asm stub
aoqi@0 505 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
aoqi@0 506 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
aoqi@0 507 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
aoqi@0 508 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
aoqi@0 509 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
aoqi@0 510 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
aoqi@0 511 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
aoqi@0 512 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
aoqi@0 513 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
aoqi@0 514 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
aoqi@0 515 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
aoqi@0 516 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
aoqi@0 517 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
aoqi@0 518
aoqi@0 519 // The value used to check ymm register after signal handle
aoqi@0 520 static int ymm_test_value() { return 0xCAFEBABE; }
aoqi@0 521
aoqi@0 522 static void get_cpu_info_wrapper();
aoqi@0 523 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
aoqi@0 524 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
aoqi@0 525 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
aoqi@0 526 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
aoqi@0 527
aoqi@0 528 static void clean_cpuFeatures() { _cpuFeatures = 0; }
aoqi@0 529 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
aoqi@0 530
aoqi@0 531
aoqi@0 532 // Initialization
aoqi@0 533 static void initialize();
aoqi@0 534
aoqi@0 535 // Override Abstract_VM_Version implementation
aoqi@0 536 static bool use_biased_locking();
aoqi@0 537
aoqi@0 538 // Asserts
aoqi@0 539 static void assert_is_initialized() {
aoqi@0 540 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
aoqi@0 541 }
aoqi@0 542
aoqi@0 543 //
aoqi@0 544 // Processor family:
aoqi@0 545 // 3 - 386
aoqi@0 546 // 4 - 486
aoqi@0 547 // 5 - Pentium
aoqi@0 548 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
aoqi@0 549 // Pentium M, Core Solo, Core Duo, Core2 Duo
aoqi@0 550 // family 6 model: 9, 13, 14, 15
aoqi@0 551 // 0x0f - Pentium 4, Opteron
aoqi@0 552 //
aoqi@0 553 // Note: The cpu family should be used to select between
aoqi@0 554 // instruction sequences which are valid on all Intel
aoqi@0 555 // processors. Use the feature test functions below to
aoqi@0 556 // determine whether a particular instruction is supported.
aoqi@0 557 //
aoqi@0 558 static int cpu_family() { return _cpu;}
aoqi@0 559 static bool is_P6() { return cpu_family() >= 6; }
aoqi@0 560 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
aoqi@0 561 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
aoqi@0 562
aoqi@0 563 static bool supports_processor_topology() {
aoqi@0 564 return (_cpuid_info.std_max_function >= 0xB) &&
aoqi@0 565 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
aoqi@0 566 // Some cpus have max cpuid >= 0xB but do not support processor topology.
aoqi@0 567 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
aoqi@0 568 }
aoqi@0 569
aoqi@0 570 static uint cores_per_cpu() {
aoqi@0 571 uint result = 1;
aoqi@0 572 if (is_intel()) {
vkempik@7541 573 bool supports_topology = supports_processor_topology();
vkempik@7541 574 if (supports_topology) {
aoqi@0 575 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
aoqi@0 576 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
vkempik@7541 577 }
vkempik@7541 578 if (!supports_topology || result == 0) {
aoqi@0 579 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
aoqi@0 580 }
aoqi@0 581 } else if (is_amd()) {
aoqi@0 582 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
aoqi@0 583 }
aoqi@0 584 return result;
aoqi@0 585 }
aoqi@0 586
aoqi@0 587 static uint threads_per_core() {
aoqi@0 588 uint result = 1;
aoqi@0 589 if (is_intel() && supports_processor_topology()) {
aoqi@0 590 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
aoqi@0 591 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
aoqi@0 592 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
aoqi@0 593 cores_per_cpu();
aoqi@0 594 }
poonam@8175 595 return (result == 0 ? 1 : result);
aoqi@0 596 }
aoqi@0 597
kevinw@8729 598 static intx L1_line_size() {
aoqi@0 599 intx result = 0;
aoqi@0 600 if (is_intel()) {
aoqi@0 601 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
aoqi@0 602 } else if (is_amd()) {
aoqi@0 603 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
aoqi@0 604 }
aoqi@0 605 if (result < 32) // not defined ?
aoqi@0 606 result = 32; // 32 bytes by default on x86 and other x64
aoqi@0 607 return result;
aoqi@0 608 }
aoqi@0 609
kevinw@8729 610 static intx prefetch_data_size() {
kevinw@8729 611 return L1_line_size();
kevinw@8729 612 }
kevinw@8729 613
aoqi@0 614 //
aoqi@0 615 // Feature identification
aoqi@0 616 //
aoqi@0 617 static bool supports_cpuid() { return _cpuFeatures != 0; }
aoqi@0 618 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
aoqi@0 619 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
aoqi@0 620 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
aoqi@0 621 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
aoqi@0 622 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
aoqi@0 623 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
aoqi@0 624 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
aoqi@0 625 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
aoqi@0 626 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
aoqi@0 627 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
aoqi@0 628 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
aoqi@0 629 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
aoqi@0 630 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
aoqi@0 631 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
aoqi@0 632 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
aoqi@0 633 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
aoqi@0 634 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
aoqi@0 635 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
aoqi@0 636 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
aoqi@0 637 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
aoqi@0 638 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
kvn@7152 639 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
aoqi@0 640 // Intel features
aoqi@0 641 static bool is_intel_family_core() { return is_intel() &&
aoqi@0 642 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
aoqi@0 643
aoqi@0 644 static bool is_intel_tsc_synched_at_init() {
aoqi@0 645 if (is_intel_family_core()) {
aoqi@0 646 uint32_t ext_model = extended_cpu_model();
aoqi@0 647 if (ext_model == CPU_MODEL_NEHALEM_EP ||
aoqi@0 648 ext_model == CPU_MODEL_WESTMERE_EP ||
aoqi@0 649 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
aoqi@0 650 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
aoqi@0 651 // <= 2-socket invariant tsc support. EX versions are usually used
aoqi@0 652 // in > 2-socket systems and likely don't synchronize tscs at
aoqi@0 653 // initialization.
aoqi@0 654 // Code that uses tsc values must be prepared for them to arbitrarily
aoqi@0 655 // jump forward or backward.
aoqi@0 656 return true;
aoqi@0 657 }
aoqi@0 658 }
aoqi@0 659 return false;
aoqi@0 660 }
aoqi@0 661
aoqi@0 662 // AMD features
aoqi@0 663 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
aoqi@0 664 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
aoqi@0 665 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
aoqi@0 666 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
aoqi@0 667
aoqi@0 668 static bool is_amd_Barcelona() { return is_amd() &&
aoqi@0 669 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
aoqi@0 670
aoqi@0 671 // Intel and AMD newer cores support fast timestamps well
aoqi@0 672 static bool supports_tscinv_bit() {
aoqi@0 673 return (_cpuFeatures & CPU_TSCINV) != 0;
aoqi@0 674 }
aoqi@0 675 static bool supports_tscinv() {
aoqi@0 676 return supports_tscinv_bit() &&
aoqi@0 677 ( (is_amd() && !is_amd_Barcelona()) ||
aoqi@0 678 is_intel_tsc_synched_at_init() );
aoqi@0 679 }
aoqi@0 680
aoqi@0 681 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
aoqi@0 682 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
aoqi@0 683 supports_sse3() && _model != 0x1C; }
aoqi@0 684
aoqi@0 685 static bool supports_compare_and_exchange() { return true; }
aoqi@0 686
aoqi@0 687 static const char* cpu_features() { return _features_str; }
aoqi@0 688
aoqi@0 689 static intx allocate_prefetch_distance() {
aoqi@0 690 // This method should be called before allocate_prefetch_style().
aoqi@0 691 //
aoqi@0 692 // Hardware prefetching (distance/size in bytes):
aoqi@0 693 // Pentium 3 - 64 / 32
aoqi@0 694 // Pentium 4 - 256 / 128
aoqi@0 695 // Athlon - 64 / 32 ????
aoqi@0 696 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
aoqi@0 697 // Core - 128 / 64
aoqi@0 698 //
aoqi@0 699 // Software prefetching (distance in bytes / instruction with best score):
aoqi@0 700 // Pentium 3 - 128 / prefetchnta
aoqi@0 701 // Pentium 4 - 512 / prefetchnta
aoqi@0 702 // Athlon - 128 / prefetchnta
aoqi@0 703 // Opteron - 256 / prefetchnta
aoqi@0 704 // Core - 256 / prefetchnta
aoqi@0 705 // It will be used only when AllocatePrefetchStyle > 0
aoqi@0 706
aoqi@0 707 intx count = AllocatePrefetchDistance;
aoqi@0 708 if (count < 0) { // default ?
aoqi@0 709 if (is_amd()) { // AMD
aoqi@0 710 if (supports_sse2())
aoqi@0 711 count = 256; // Opteron
aoqi@0 712 else
aoqi@0 713 count = 128; // Athlon
aoqi@0 714 } else { // Intel
aoqi@0 715 if (supports_sse2())
aoqi@0 716 if (cpu_family() == 6) {
aoqi@0 717 count = 256; // Pentium M, Core, Core2
aoqi@0 718 } else {
aoqi@0 719 count = 512; // Pentium 4
aoqi@0 720 }
aoqi@0 721 else
aoqi@0 722 count = 128; // Pentium 3 (and all other old CPUs)
aoqi@0 723 }
aoqi@0 724 }
aoqi@0 725 return count;
aoqi@0 726 }
aoqi@0 727 static intx allocate_prefetch_style() {
aoqi@0 728 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
aoqi@0 729 // Return 0 if AllocatePrefetchDistance was not defined.
aoqi@0 730 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
aoqi@0 731 }
aoqi@0 732
aoqi@0 733 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
aoqi@0 734 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
aoqi@0 735 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
aoqi@0 736 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
aoqi@0 737
aoqi@0 738 // gc copy/scan is disabled if prefetchw isn't supported, because
aoqi@0 739 // Prefetch::write emits an inlined prefetchw on Linux.
aoqi@0 740 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
aoqi@0 741 // The used prefetcht0 instruction works for both amd64 and em64t.
aoqi@0 742 static intx prefetch_copy_interval_in_bytes() {
aoqi@0 743 intx interval = PrefetchCopyIntervalInBytes;
aoqi@0 744 return interval >= 0 ? interval : 576;
aoqi@0 745 }
aoqi@0 746 static intx prefetch_scan_interval_in_bytes() {
aoqi@0 747 intx interval = PrefetchScanIntervalInBytes;
aoqi@0 748 return interval >= 0 ? interval : 576;
aoqi@0 749 }
aoqi@0 750 static intx prefetch_fields_ahead() {
aoqi@0 751 intx count = PrefetchFieldsAhead;
aoqi@0 752 return count >= 0 ? count : 1;
aoqi@0 753 }
aoqi@0 754 };
aoqi@0 755
aoqi@0 756 #endif // CPU_X86_VM_VM_VERSION_X86_HPP

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