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src/cpu/ppc/vm/icache_ppc.hpp@70aa912cebe5 (annotated)
src/cpu/ppc/vm/icache_ppc.hpp
Wed, 15 Apr 2020 11:49:55 +0800
- author
- aoqi
- date
- Wed, 15 Apr 2020 11:49:55 +0800
- changeset 9852
- 70aa912cebe5
- parent 6876
- 710a3c8b516e
- permissions
- -rw-r--r--
Merge
| aoqi@0 | 1 | /* |
| aoqi@0 | 2 | * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. |
| aoqi@0 | 3 | * Copyright 2012, 2013 SAP AG. All rights reserved. |
| aoqi@0 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@0 | 5 | * |
| aoqi@0 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@0 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@0 | 8 | * published by the Free Software Foundation. |
| aoqi@0 | 9 | * |
| aoqi@0 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@0 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@0 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@0 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@0 | 14 | * accompanied this code). |
| aoqi@0 | 15 | * |
| aoqi@0 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@0 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@0 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@0 | 19 | * |
| aoqi@0 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@0 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@0 | 22 | * questions. |
| aoqi@0 | 23 | * |
| aoqi@0 | 24 | */ |
| aoqi@0 | 25 | |
| aoqi@0 | 26 | #ifndef CPU_PPC_VM_ICACHE_PPC_HPP |
| aoqi@0 | 27 | #define CPU_PPC_VM_ICACHE_PPC_HPP |
| aoqi@0 | 28 | |
| aoqi@0 | 29 | // Interface for updating the instruction cache. Whenever the VM modifies |
| aoqi@0 | 30 | // code, part of the processor instruction cache potentially has to be flushed. |
| aoqi@0 | 31 | |
| aoqi@0 | 32 | class ICache : public AbstractICache { |
| aoqi@0 | 33 | friend class ICacheStubGenerator; |
| aoqi@0 | 34 | static int ppc64_flush_icache(address start, int lines, int magic); |
| aoqi@0 | 35 | |
| aoqi@0 | 36 | public: |
| aoqi@0 | 37 | enum { |
| aoqi@0 | 38 | // Actually, cache line size is 64, but keeping it as it is to be |
| aoqi@0 | 39 | // on the safe side on ALL PPC64 implementations. |
| aoqi@0 | 40 | log2_line_size = 5, |
| aoqi@0 | 41 | line_size = 1 << log2_line_size |
| aoqi@0 | 42 | }; |
| aoqi@0 | 43 | |
| aoqi@0 | 44 | static void ppc64_flush_icache_bytes(address start, int bytes) { |
| aoqi@0 | 45 | // Align start address to an icache line boundary and transform |
| aoqi@0 | 46 | // nbytes to an icache line count. |
| aoqi@0 | 47 | const uint line_offset = mask_address_bits(start, line_size - 1); |
| aoqi@0 | 48 | ppc64_flush_icache(start - line_offset, (bytes + line_offset + line_size - 1) >> log2_line_size, 0); |
| aoqi@0 | 49 | } |
| aoqi@0 | 50 | }; |
| aoqi@0 | 51 | |
| aoqi@0 | 52 | #endif // CPU_PPC_VM_ICACHE_PPC_HPP |
