src/cpu/ppc/vm/icache_ppc.cpp

Wed, 15 Apr 2020 11:49:55 +0800

author
aoqi
date
Wed, 15 Apr 2020 11:49:55 +0800
changeset 9852
70aa912cebe5
parent 6876
710a3c8b516e
permissions
-rw-r--r--

Merge

aoqi@0 1 /*
aoqi@0 2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * Copyright 2012, 2013 SAP AG. All rights reserved.
aoqi@0 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 5 *
aoqi@0 6 * This code is free software; you can redistribute it and/or modify it
aoqi@0 7 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 8 * published by the Free Software Foundation.
aoqi@0 9 *
aoqi@0 10 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 13 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 14 * accompanied this code).
aoqi@0 15 *
aoqi@0 16 * You should have received a copy of the GNU General Public License version
aoqi@0 17 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 19 *
aoqi@0 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 21 * or visit www.oracle.com if you need additional information or have any
aoqi@0 22 * questions.
aoqi@0 23 *
aoqi@0 24 */
aoqi@0 25
aoqi@0 26 #include "precompiled.hpp"
aoqi@0 27 #include "assembler_ppc.inline.hpp"
aoqi@0 28 #include "runtime/icache.hpp"
aoqi@0 29
aoqi@0 30 // Use inline assembler to implement icache flush.
aoqi@0 31 int ICache::ppc64_flush_icache(address start, int lines, int magic) {
aoqi@0 32 address end = start + (unsigned int)lines*ICache::line_size;
aoqi@0 33 assert(start <= end, "flush_icache parms");
aoqi@0 34
aoqi@0 35 // store modified cache lines from data cache
aoqi@0 36 for (address a = start; a < end; a += ICache::line_size) {
aoqi@0 37 __asm__ __volatile__(
aoqi@0 38 "dcbst 0, %0 \n"
aoqi@0 39 :
aoqi@0 40 : "r" (a)
aoqi@0 41 : "memory");
aoqi@0 42 }
aoqi@0 43
aoqi@0 44 // sync instruction
aoqi@0 45 __asm__ __volatile__(
aoqi@0 46 "sync \n"
aoqi@0 47 :
aoqi@0 48 :
aoqi@0 49 : "memory");
aoqi@0 50
aoqi@0 51 // invalidate respective cache lines in instruction cache
aoqi@0 52 for (address a = start; a < end; a += ICache::line_size) {
aoqi@0 53 __asm__ __volatile__(
aoqi@0 54 "icbi 0, %0 \n"
aoqi@0 55 :
aoqi@0 56 : "r" (a)
aoqi@0 57 : "memory");
aoqi@0 58 }
aoqi@0 59
aoqi@0 60 // discard fetched instructions
aoqi@0 61 __asm__ __volatile__(
aoqi@0 62 "isync \n"
aoqi@0 63 :
aoqi@0 64 :
aoqi@0 65 : "memory");
aoqi@0 66
aoqi@0 67 return magic;
aoqi@0 68 }
aoqi@0 69
aoqi@0 70 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {
aoqi@0 71 StubCodeMark mark(this, "ICache", "flush_icache_stub");
aoqi@0 72
aoqi@0 73 *flush_icache_stub = (ICache::flush_icache_stub_t)ICache::ppc64_flush_icache;
aoqi@0 74
aoqi@0 75 // First call to flush itself
aoqi@0 76 ICache::invalidate_range((address)(*flush_icache_stub), 0);
aoqi@0 77 }

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