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src/cpu/sparc/vm/vm_version_sparc.hpp@6729bbc1fcd6 (annotated)

src/cpu/sparc/vm/vm_version_sparc.hpp

Wed, 16 Nov 2011 01:39:50 -0800

author

twisti

date

Wed, 16 Nov 2011 01:39:50 -0800

changeset 3310

6729bbc1fcd6

parent 3092

baf763f388e6

child 3972

8cb110fd7627

permissions

-rw-r--r--

7003454: order constants in constant table by number of references in code
Reviewed-by: kvn, never, bdelsart

duke@435	1	/*
kvn@2269	2	* Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
stefank@2314	26	#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
stefank@2314	27
stefank@2314	28	#include "runtime/globals_extension.hpp"
stefank@2314	29	#include "runtime/vm_version.hpp"
stefank@2314	30
duke@435	31	class VM_Version: public Abstract_VM_Version {
duke@435	32	protected:
duke@435	33	enum Feature_Flag {
kvn@3037	34	v8_instructions = 0,
kvn@3037	35	hardware_mul32 = 1,
kvn@3037	36	hardware_div32 = 2,
kvn@3037	37	hardware_fsmuld = 3,
kvn@3037	38	hardware_popc = 4,
kvn@3037	39	v9_instructions = 5,
kvn@3037	40	vis1_instructions = 6,
kvn@3037	41	vis2_instructions = 7,
kvn@3037	42	sun4v_instructions = 8,
kvn@2269	43	blk_init_instructions = 9,
kvn@3037	44	fmaf_instructions = 10,
kvn@3037	45	fmau_instructions = 11,
kvn@3037	46	vis3_instructions = 12,
kvn@3037	47	sparc64_family = 13,
kvn@3037	48	T_family = 14,
kvn@3037	49	T1_model = 15,
kvn@3037	50	cbcond_instructions = 16
duke@435	51	};
duke@435	52
duke@435	53	enum Feature_Flag_Set {
twisti@1076	54	unknown_m = 0,
twisti@1076	55	all_features_m = -1,
duke@435	56
kvn@3037	57	v8_instructions_m = 1 << v8_instructions,
kvn@3037	58	hardware_mul32_m = 1 << hardware_mul32,
kvn@3037	59	hardware_div32_m = 1 << hardware_div32,
kvn@3037	60	hardware_fsmuld_m = 1 << hardware_fsmuld,
kvn@3037	61	hardware_popc_m = 1 << hardware_popc,
kvn@3037	62	v9_instructions_m = 1 << v9_instructions,
kvn@3037	63	vis1_instructions_m = 1 << vis1_instructions,
kvn@3037	64	vis2_instructions_m = 1 << vis2_instructions,
kvn@3037	65	sun4v_m = 1 << sun4v_instructions,
kvn@2269	66	blk_init_instructions_m = 1 << blk_init_instructions,
kvn@3037	67	fmaf_instructions_m = 1 << fmaf_instructions,
kvn@3037	68	fmau_instructions_m = 1 << fmau_instructions,
kvn@3037	69	vis3_instructions_m = 1 << vis3_instructions,
kvn@3037	70	sparc64_family_m = 1 << sparc64_family,
kvn@3037	71	T_family_m = 1 << T_family,
kvn@3037	72	T1_model_m = 1 << T1_model,
kvn@3037	73	cbcond_instructions_m = 1 << cbcond_instructions,
duke@435	74
twisti@1076	75	generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
twisti@1076	76	generic_v9_m = generic_v8_m | v9_instructions_m,
twisti@1076	77	ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
duke@435	78
duke@435	79	// Temporary until we have something more accurate
twisti@1076	80	niagara1_unique_m = sun4v_m,
twisti@1076	81	niagara1_m = generic_v9_m | niagara1_unique_m
duke@435	82	};
duke@435	83
duke@435	84	static int _features;
duke@435	85	static const char* _features_str;
duke@435	86
duke@435	87	static void print_features();
duke@435	88	static int determine_features();
duke@435	89	static int platform_features(int features);
duke@435	90
kvn@2403	91	// Returns true if the platform is in the niagara line (T series)
kvn@2403	92	static bool is_T_family(int features) { return (features & T_family_m) != 0; }
kvn@2403	93	static bool is_niagara() { return is_T_family(_features); }
kvn@2403	94	DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } )
kvn@2403	95
kvn@2403	96	// Returns true if it is niagara1 (T1).
kvn@2403	97	static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
duke@435	98
jmasa@445	99	static int maximum_niagara1_processor_count() { return 32; }
jmasa@445	100
duke@435	101	public:
duke@435	102	// Initialization
duke@435	103	static void initialize();
duke@435	104
duke@435	105	// Instruction support
duke@435	106	static bool has_v8() { return (_features & v8_instructions_m) != 0; }
duke@435	107	static bool has_v9() { return (_features & v9_instructions_m) != 0; }
twisti@1076	108	static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
twisti@1076	109	static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
duke@435	110	static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
twisti@1078	111	static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
duke@435	112	static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
duke@435	113	static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
kvn@2403	114	static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
kvn@2269	115	static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
kvn@3037	116	static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
duke@435	117
duke@435	118	static bool supports_compare_and_exchange()
duke@435	119	{ return has_v9(); }
duke@435	120
kvn@2403	121	// Returns true if the platform is in the niagara line (T series)
kvn@2403	122	// and newer than the niagara1.
kvn@2403	123	static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
kvn@3052	124	static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
kvn@3037	125
kvn@2403	126	// Fujitsu SPARC64
kvn@2403	127	static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
duke@435	128
kvn@3037	129	static bool is_sun4v() { return (_features & sun4v_m) != 0; }
kvn@3037	130	static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
kvn@3037	131
kvn@2403	132	static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
kvn@2403	133	static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
kvn@3052	134
kvn@3037	135	// T4 and newer Sparc have fast RDPC instruction.
kvn@3052	136	static bool has_fast_rdpc() { return is_T4(); }
kvn@3052	137
kvn@3092	138	// On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
kvn@3092	139	static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
duke@435	140
duke@435	141	static const char* cpu_features() { return _features_str; }
duke@435	142
kvn@3052	143	static intx prefetch_data_size() {
kvn@3052	144	return is_T4() ? 32 : 64; // default prefetch block size on sparc
duke@435	145	}
duke@435	146
duke@435	147	// Prefetch
duke@435	148	static intx prefetch_copy_interval_in_bytes() {
duke@435	149	intx interval = PrefetchCopyIntervalInBytes;
duke@435	150	return interval >= 0 ? interval : (has_v9() ? 512 : 0);
duke@435	151	}
duke@435	152	static intx prefetch_scan_interval_in_bytes() {
duke@435	153	intx interval = PrefetchScanIntervalInBytes;
duke@435	154	return interval >= 0 ? interval : (has_v9() ? 512 : 0);
duke@435	155	}
duke@435	156	static intx prefetch_fields_ahead() {
duke@435	157	intx count = PrefetchFieldsAhead;
duke@435	158	return count >= 0 ? count : (is_ultra3() ? 1 : 0);
duke@435	159	}
duke@435	160
duke@435	161	static intx allocate_prefetch_distance() {
duke@435	162	// This method should be called before allocate_prefetch_style().
duke@435	163	intx count = AllocatePrefetchDistance;
duke@435	164	if (count < 0) { // default is not defined ?
duke@435	165	count = 512;
duke@435	166	}
duke@435	167	return count;
duke@435	168	}
duke@435	169	static intx allocate_prefetch_style() {
duke@435	170	assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
duke@435	171	// Return 0 if AllocatePrefetchDistance was not defined.
duke@435	172	return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
duke@435	173	}
duke@435	174
duke@435	175	// Legacy
duke@435	176	static bool v8_instructions_work() { return has_v8() && !has_v9(); }
duke@435	177	static bool v9_instructions_work() { return has_v9(); }
duke@435	178
duke@435	179	// Assembler testing
duke@435	180	static void allow_all();
duke@435	181	static void revert();
duke@435	182
duke@435	183	// Override the Abstract_VM_Version implementation.
duke@435	184	static uint page_size_count() { return is_sun4v() ? 4 : 2; }
jmasa@445	185
jmasa@445	186	// Calculates the number of parallel threads
jmasa@445	187	static unsigned int calc_parallel_worker_threads();
duke@435	188	};
stefank@2314	189
stefank@2314	190	#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP