Thu, 14 Apr 2011 13:45:41 -0700
Merge
twisti@1020 | 1 | /* |
trims@2708 | 2 | * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All Rights Reserved. |
twisti@1020 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
twisti@1020 | 4 | * |
twisti@1020 | 5 | * This code is free software; you can redistribute it and/or modify it |
twisti@1020 | 6 | * under the terms of the GNU General Public License version 2 only, as |
twisti@1020 | 7 | * published by the Free Software Foundation. |
twisti@1020 | 8 | * |
twisti@1020 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
twisti@1020 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
twisti@1020 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
twisti@1020 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
twisti@1020 | 13 | * accompanied this code). |
twisti@1020 | 14 | * |
twisti@1020 | 15 | * You should have received a copy of the GNU General Public License version |
twisti@1020 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
twisti@1020 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
twisti@1020 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
twisti@1020 | 22 | * |
twisti@1020 | 23 | */ |
twisti@1020 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "assembler_x86.inline.hpp" |
stefank@2314 | 27 | #include "memory/resourceArea.hpp" |
stefank@2314 | 28 | #include "runtime/java.hpp" |
stefank@2314 | 29 | #include "runtime/stubCodeGenerator.hpp" |
stefank@2314 | 30 | #include "vm_version_x86.hpp" |
stefank@2314 | 31 | #ifdef TARGET_OS_FAMILY_linux |
stefank@2314 | 32 | # include "os_linux.inline.hpp" |
stefank@2314 | 33 | #endif |
stefank@2314 | 34 | #ifdef TARGET_OS_FAMILY_solaris |
stefank@2314 | 35 | # include "os_solaris.inline.hpp" |
stefank@2314 | 36 | #endif |
stefank@2314 | 37 | #ifdef TARGET_OS_FAMILY_windows |
stefank@2314 | 38 | # include "os_windows.inline.hpp" |
stefank@2314 | 39 | #endif |
twisti@1020 | 40 | |
twisti@1020 | 41 | |
twisti@1020 | 42 | int VM_Version::_cpu; |
twisti@1020 | 43 | int VM_Version::_model; |
twisti@1020 | 44 | int VM_Version::_stepping; |
twisti@1020 | 45 | int VM_Version::_cpuFeatures; |
twisti@1020 | 46 | const char* VM_Version::_features_str = ""; |
twisti@1020 | 47 | VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
twisti@1020 | 48 | |
twisti@1020 | 49 | static BufferBlob* stub_blob; |
kvn@1977 | 50 | static const int stub_size = 400; |
twisti@1020 | 51 | |
twisti@1020 | 52 | extern "C" { |
twisti@1020 | 53 | typedef void (*getPsrInfo_stub_t)(void*); |
twisti@1020 | 54 | } |
twisti@1020 | 55 | static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
twisti@1020 | 56 | |
twisti@1020 | 57 | |
twisti@1020 | 58 | class VM_Version_StubGenerator: public StubCodeGenerator { |
twisti@1020 | 59 | public: |
twisti@1020 | 60 | |
twisti@1020 | 61 | VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
twisti@1020 | 62 | |
twisti@1020 | 63 | address generate_getPsrInfo() { |
twisti@1020 | 64 | // Flags to test CPU type. |
twisti@1020 | 65 | const uint32_t EFL_AC = 0x40000; |
twisti@1020 | 66 | const uint32_t EFL_ID = 0x200000; |
twisti@1020 | 67 | // Values for when we don't have a CPUID instruction. |
twisti@1020 | 68 | const int CPU_FAMILY_SHIFT = 8; |
twisti@1020 | 69 | const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
twisti@1020 | 70 | const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
twisti@1020 | 71 | |
kvn@1977 | 72 | Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
twisti@1020 | 73 | Label ext_cpuid1, ext_cpuid5, done; |
twisti@1020 | 74 | |
twisti@1020 | 75 | StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
twisti@1020 | 76 | # define __ _masm-> |
twisti@1020 | 77 | |
twisti@1020 | 78 | address start = __ pc(); |
twisti@1020 | 79 | |
twisti@1020 | 80 | // |
twisti@1020 | 81 | // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
twisti@1020 | 82 | // |
twisti@1020 | 83 | // LP64: rcx and rdx are first and second argument registers on windows |
twisti@1020 | 84 | |
twisti@1020 | 85 | __ push(rbp); |
twisti@1020 | 86 | #ifdef _LP64 |
twisti@1020 | 87 | __ mov(rbp, c_rarg0); // cpuid_info address |
twisti@1020 | 88 | #else |
twisti@1020 | 89 | __ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
twisti@1020 | 90 | #endif |
twisti@1020 | 91 | __ push(rbx); |
twisti@1020 | 92 | __ push(rsi); |
twisti@1020 | 93 | __ pushf(); // preserve rbx, and flags |
twisti@1020 | 94 | __ pop(rax); |
twisti@1020 | 95 | __ push(rax); |
twisti@1020 | 96 | __ mov(rcx, rax); |
twisti@1020 | 97 | // |
twisti@1020 | 98 | // if we are unable to change the AC flag, we have a 386 |
twisti@1020 | 99 | // |
twisti@1020 | 100 | __ xorl(rax, EFL_AC); |
twisti@1020 | 101 | __ push(rax); |
twisti@1020 | 102 | __ popf(); |
twisti@1020 | 103 | __ pushf(); |
twisti@1020 | 104 | __ pop(rax); |
twisti@1020 | 105 | __ cmpptr(rax, rcx); |
twisti@1020 | 106 | __ jccb(Assembler::notEqual, detect_486); |
twisti@1020 | 107 | |
twisti@1020 | 108 | __ movl(rax, CPU_FAMILY_386); |
twisti@1020 | 109 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 110 | __ jmp(done); |
twisti@1020 | 111 | |
twisti@1020 | 112 | // |
twisti@1020 | 113 | // If we are unable to change the ID flag, we have a 486 which does |
twisti@1020 | 114 | // not support the "cpuid" instruction. |
twisti@1020 | 115 | // |
twisti@1020 | 116 | __ bind(detect_486); |
twisti@1020 | 117 | __ mov(rax, rcx); |
twisti@1020 | 118 | __ xorl(rax, EFL_ID); |
twisti@1020 | 119 | __ push(rax); |
twisti@1020 | 120 | __ popf(); |
twisti@1020 | 121 | __ pushf(); |
twisti@1020 | 122 | __ pop(rax); |
twisti@1020 | 123 | __ cmpptr(rcx, rax); |
twisti@1020 | 124 | __ jccb(Assembler::notEqual, detect_586); |
twisti@1020 | 125 | |
twisti@1020 | 126 | __ bind(cpu486); |
twisti@1020 | 127 | __ movl(rax, CPU_FAMILY_486); |
twisti@1020 | 128 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
twisti@1020 | 129 | __ jmp(done); |
twisti@1020 | 130 | |
twisti@1020 | 131 | // |
twisti@1020 | 132 | // At this point, we have a chip which supports the "cpuid" instruction |
twisti@1020 | 133 | // |
twisti@1020 | 134 | __ bind(detect_586); |
twisti@1020 | 135 | __ xorl(rax, rax); |
twisti@1020 | 136 | __ cpuid(); |
twisti@1020 | 137 | __ orl(rax, rax); |
twisti@1020 | 138 | __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
twisti@1020 | 139 | // value of at least 1, we give up and |
twisti@1020 | 140 | // assume a 486 |
twisti@1020 | 141 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
twisti@1020 | 142 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 143 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 144 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 145 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 146 | |
kvn@1977 | 147 | __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
kvn@1977 | 148 | __ jccb(Assembler::belowEqual, std_cpuid4); |
kvn@1977 | 149 | |
kvn@1977 | 150 | // |
kvn@1977 | 151 | // cpuid(0xB) Processor Topology |
kvn@1977 | 152 | // |
kvn@1977 | 153 | __ movl(rax, 0xb); |
kvn@1977 | 154 | __ xorl(rcx, rcx); // Threads level |
kvn@1977 | 155 | __ cpuid(); |
kvn@1977 | 156 | |
kvn@1977 | 157 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
kvn@1977 | 158 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 159 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 160 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 161 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 162 | |
kvn@1977 | 163 | __ movl(rax, 0xb); |
kvn@1977 | 164 | __ movl(rcx, 1); // Cores level |
kvn@1977 | 165 | __ cpuid(); |
kvn@1977 | 166 | __ push(rax); |
kvn@1977 | 167 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 168 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 169 | __ andl(rax, 0xffff); |
kvn@1977 | 170 | __ pop(rax); |
kvn@1977 | 171 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 172 | |
kvn@1977 | 173 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
kvn@1977 | 174 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 175 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 176 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 177 | __ movl(Address(rsi,12), rdx); |
kvn@1977 | 178 | |
kvn@1977 | 179 | __ movl(rax, 0xb); |
kvn@1977 | 180 | __ movl(rcx, 2); // Packages level |
kvn@1977 | 181 | __ cpuid(); |
kvn@1977 | 182 | __ push(rax); |
kvn@1977 | 183 | __ andl(rax, 0x1f); // Determine if valid topology level |
kvn@1977 | 184 | __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
kvn@1977 | 185 | __ andl(rax, 0xffff); |
kvn@1977 | 186 | __ pop(rax); |
kvn@1977 | 187 | __ jccb(Assembler::equal, std_cpuid4); |
kvn@1977 | 188 | |
kvn@1977 | 189 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
kvn@1977 | 190 | __ movl(Address(rsi, 0), rax); |
kvn@1977 | 191 | __ movl(Address(rsi, 4), rbx); |
kvn@1977 | 192 | __ movl(Address(rsi, 8), rcx); |
kvn@1977 | 193 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 194 | |
twisti@1020 | 195 | // |
twisti@1020 | 196 | // cpuid(0x4) Deterministic cache params |
twisti@1020 | 197 | // |
kvn@1977 | 198 | __ bind(std_cpuid4); |
twisti@1020 | 199 | __ movl(rax, 4); |
kvn@1977 | 200 | __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
kvn@1977 | 201 | __ jccb(Assembler::greater, std_cpuid1); |
kvn@1977 | 202 | |
twisti@1020 | 203 | __ xorl(rcx, rcx); // L1 cache |
twisti@1020 | 204 | __ cpuid(); |
twisti@1020 | 205 | __ push(rax); |
twisti@1020 | 206 | __ andl(rax, 0x1f); // Determine if valid cache parameters used |
twisti@1020 | 207 | __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
twisti@1020 | 208 | __ pop(rax); |
twisti@1020 | 209 | __ jccb(Assembler::equal, std_cpuid1); |
twisti@1020 | 210 | |
twisti@1020 | 211 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
twisti@1020 | 212 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 213 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 214 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 215 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 216 | |
twisti@1020 | 217 | // |
twisti@1020 | 218 | // Standard cpuid(0x1) |
twisti@1020 | 219 | // |
twisti@1020 | 220 | __ bind(std_cpuid1); |
twisti@1020 | 221 | __ movl(rax, 1); |
twisti@1020 | 222 | __ cpuid(); |
twisti@1020 | 223 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
twisti@1020 | 224 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 225 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 226 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 227 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 228 | |
twisti@1020 | 229 | __ movl(rax, 0x80000000); |
twisti@1020 | 230 | __ cpuid(); |
twisti@1020 | 231 | __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
twisti@1020 | 232 | __ jcc(Assembler::belowEqual, done); |
twisti@1020 | 233 | __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
twisti@1020 | 234 | __ jccb(Assembler::belowEqual, ext_cpuid1); |
twisti@1020 | 235 | __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
twisti@1020 | 236 | __ jccb(Assembler::belowEqual, ext_cpuid5); |
twisti@1020 | 237 | // |
twisti@1020 | 238 | // Extended cpuid(0x80000008) |
twisti@1020 | 239 | // |
twisti@1020 | 240 | __ movl(rax, 0x80000008); |
twisti@1020 | 241 | __ cpuid(); |
twisti@1020 | 242 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
twisti@1020 | 243 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 244 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 245 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 246 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 247 | |
twisti@1020 | 248 | // |
twisti@1020 | 249 | // Extended cpuid(0x80000005) |
twisti@1020 | 250 | // |
twisti@1020 | 251 | __ bind(ext_cpuid5); |
twisti@1020 | 252 | __ movl(rax, 0x80000005); |
twisti@1020 | 253 | __ cpuid(); |
twisti@1020 | 254 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
twisti@1020 | 255 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 256 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 257 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 258 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 259 | |
twisti@1020 | 260 | // |
twisti@1020 | 261 | // Extended cpuid(0x80000001) |
twisti@1020 | 262 | // |
twisti@1020 | 263 | __ bind(ext_cpuid1); |
twisti@1020 | 264 | __ movl(rax, 0x80000001); |
twisti@1020 | 265 | __ cpuid(); |
twisti@1020 | 266 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
twisti@1020 | 267 | __ movl(Address(rsi, 0), rax); |
twisti@1020 | 268 | __ movl(Address(rsi, 4), rbx); |
twisti@1020 | 269 | __ movl(Address(rsi, 8), rcx); |
twisti@1020 | 270 | __ movl(Address(rsi,12), rdx); |
twisti@1020 | 271 | |
twisti@1020 | 272 | // |
twisti@1020 | 273 | // return |
twisti@1020 | 274 | // |
twisti@1020 | 275 | __ bind(done); |
twisti@1020 | 276 | __ popf(); |
twisti@1020 | 277 | __ pop(rsi); |
twisti@1020 | 278 | __ pop(rbx); |
twisti@1020 | 279 | __ pop(rbp); |
twisti@1020 | 280 | __ ret(0); |
twisti@1020 | 281 | |
twisti@1020 | 282 | # undef __ |
twisti@1020 | 283 | |
twisti@1020 | 284 | return start; |
twisti@1020 | 285 | }; |
twisti@1020 | 286 | }; |
twisti@1020 | 287 | |
twisti@1020 | 288 | |
twisti@1020 | 289 | void VM_Version::get_processor_features() { |
twisti@1020 | 290 | |
twisti@1020 | 291 | _cpu = 4; // 486 by default |
twisti@1020 | 292 | _model = 0; |
twisti@1020 | 293 | _stepping = 0; |
twisti@1020 | 294 | _cpuFeatures = 0; |
twisti@1020 | 295 | _logical_processors_per_package = 1; |
twisti@1020 | 296 | |
twisti@1020 | 297 | if (!Use486InstrsOnly) { |
twisti@1020 | 298 | // Get raw processor info |
twisti@1020 | 299 | getPsrInfo_stub(&_cpuid_info); |
twisti@1020 | 300 | assert_is_initialized(); |
twisti@1020 | 301 | _cpu = extended_cpu_family(); |
twisti@1020 | 302 | _model = extended_cpu_model(); |
twisti@1020 | 303 | _stepping = cpu_stepping(); |
twisti@1020 | 304 | |
twisti@1020 | 305 | if (cpu_family() > 4) { // it supports CPUID |
twisti@1020 | 306 | _cpuFeatures = feature_flags(); |
twisti@1020 | 307 | // Logical processors are only available on P4s and above, |
twisti@1020 | 308 | // and only if hyperthreading is available. |
twisti@1020 | 309 | _logical_processors_per_package = logical_processor_count(); |
twisti@1020 | 310 | } |
twisti@1020 | 311 | } |
twisti@1020 | 312 | |
twisti@1020 | 313 | _supports_cx8 = supports_cmpxchg8(); |
twisti@1020 | 314 | |
twisti@1020 | 315 | #ifdef _LP64 |
twisti@1020 | 316 | // OS should support SSE for x64 and hardware should support at least SSE2. |
twisti@1020 | 317 | if (!VM_Version::supports_sse2()) { |
twisti@1020 | 318 | vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
twisti@1020 | 319 | } |
roland@1495 | 320 | // in 64 bit the use of SSE2 is the minimum |
roland@1495 | 321 | if (UseSSE < 2) UseSSE = 2; |
twisti@1020 | 322 | #endif |
twisti@1020 | 323 | |
twisti@1020 | 324 | // If the OS doesn't support SSE, we can't use this feature even if the HW does |
twisti@1020 | 325 | if (!os::supports_sse()) |
twisti@1020 | 326 | _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
twisti@1020 | 327 | |
twisti@1020 | 328 | if (UseSSE < 4) { |
twisti@1020 | 329 | _cpuFeatures &= ~CPU_SSE4_1; |
twisti@1020 | 330 | _cpuFeatures &= ~CPU_SSE4_2; |
twisti@1020 | 331 | } |
twisti@1020 | 332 | |
twisti@1020 | 333 | if (UseSSE < 3) { |
twisti@1020 | 334 | _cpuFeatures &= ~CPU_SSE3; |
twisti@1020 | 335 | _cpuFeatures &= ~CPU_SSSE3; |
twisti@1020 | 336 | _cpuFeatures &= ~CPU_SSE4A; |
twisti@1020 | 337 | } |
twisti@1020 | 338 | |
twisti@1020 | 339 | if (UseSSE < 2) |
twisti@1020 | 340 | _cpuFeatures &= ~CPU_SSE2; |
twisti@1020 | 341 | |
twisti@1020 | 342 | if (UseSSE < 1) |
twisti@1020 | 343 | _cpuFeatures &= ~CPU_SSE; |
twisti@1020 | 344 | |
twisti@1020 | 345 | if (logical_processors_per_package() == 1) { |
twisti@1020 | 346 | // HT processor could be installed on a system which doesn't support HT. |
twisti@1020 | 347 | _cpuFeatures &= ~CPU_HT; |
twisti@1020 | 348 | } |
twisti@1020 | 349 | |
twisti@1020 | 350 | char buf[256]; |
twisti@1210 | 351 | jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
twisti@1020 | 352 | cores_per_cpu(), threads_per_core(), |
twisti@1020 | 353 | cpu_family(), _model, _stepping, |
twisti@1020 | 354 | (supports_cmov() ? ", cmov" : ""), |
twisti@1020 | 355 | (supports_cmpxchg8() ? ", cx8" : ""), |
twisti@1020 | 356 | (supports_fxsr() ? ", fxsr" : ""), |
twisti@1020 | 357 | (supports_mmx() ? ", mmx" : ""), |
twisti@1020 | 358 | (supports_sse() ? ", sse" : ""), |
twisti@1020 | 359 | (supports_sse2() ? ", sse2" : ""), |
twisti@1020 | 360 | (supports_sse3() ? ", sse3" : ""), |
twisti@1020 | 361 | (supports_ssse3()? ", ssse3": ""), |
twisti@1020 | 362 | (supports_sse4_1() ? ", sse4.1" : ""), |
twisti@1020 | 363 | (supports_sse4_2() ? ", sse4.2" : ""), |
twisti@1078 | 364 | (supports_popcnt() ? ", popcnt" : ""), |
twisti@1020 | 365 | (supports_mmx_ext() ? ", mmxext" : ""), |
twisti@1020 | 366 | (supports_3dnow() ? ", 3dnow" : ""), |
twisti@1020 | 367 | (supports_3dnow2() ? ", 3dnowext" : ""), |
twisti@1210 | 368 | (supports_lzcnt() ? ", lzcnt": ""), |
twisti@1020 | 369 | (supports_sse4a() ? ", sse4a": ""), |
twisti@1020 | 370 | (supports_ht() ? ", ht": "")); |
twisti@1020 | 371 | _features_str = strdup(buf); |
twisti@1020 | 372 | |
twisti@1020 | 373 | // UseSSE is set to the smaller of what hardware supports and what |
twisti@1020 | 374 | // the command line requires. I.e., you cannot set UseSSE to 2 on |
twisti@1020 | 375 | // older Pentiums which do not support it. |
twisti@1020 | 376 | if( UseSSE > 4 ) UseSSE=4; |
twisti@1020 | 377 | if( UseSSE < 0 ) UseSSE=0; |
twisti@1020 | 378 | if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support |
twisti@1020 | 379 | UseSSE = MIN2((intx)3,UseSSE); |
twisti@1020 | 380 | if( !supports_sse3() ) // Drop to 2 if no SSE3 support |
twisti@1020 | 381 | UseSSE = MIN2((intx)2,UseSSE); |
twisti@1020 | 382 | if( !supports_sse2() ) // Drop to 1 if no SSE2 support |
twisti@1020 | 383 | UseSSE = MIN2((intx)1,UseSSE); |
twisti@1020 | 384 | if( !supports_sse () ) // Drop to 0 if no SSE support |
twisti@1020 | 385 | UseSSE = 0; |
twisti@1020 | 386 | |
twisti@1020 | 387 | // On new cpus instructions which update whole XMM register should be used |
twisti@1020 | 388 | // to prevent partial register stall due to dependencies on high half. |
twisti@1020 | 389 | // |
twisti@1020 | 390 | // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
twisti@1020 | 391 | // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
twisti@1020 | 392 | // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
twisti@1020 | 393 | // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
twisti@1020 | 394 | |
twisti@1020 | 395 | if( is_amd() ) { // AMD cpus specific settings |
twisti@1020 | 396 | if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 397 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 398 | UseAddressNop = true; |
twisti@1020 | 399 | } |
twisti@1020 | 400 | if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
twisti@1020 | 401 | // Use it on new AMD cpus starting from Opteron. |
twisti@1020 | 402 | UseNewLongLShift = true; |
twisti@1020 | 403 | } |
twisti@1020 | 404 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 405 | if( supports_sse4a() ) { |
twisti@1020 | 406 | UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
twisti@1020 | 407 | } else { |
twisti@1020 | 408 | UseXmmLoadAndClearUpper = false; |
twisti@1020 | 409 | } |
twisti@1020 | 410 | } |
twisti@1020 | 411 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 412 | if( supports_sse4a() ) { |
twisti@1020 | 413 | UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
twisti@1020 | 414 | } else { |
twisti@1020 | 415 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 416 | } |
twisti@1020 | 417 | } |
twisti@1020 | 418 | if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
twisti@1020 | 419 | if( supports_sse4a() ) { |
twisti@1020 | 420 | UseXmmI2F = true; |
twisti@1020 | 421 | } else { |
twisti@1020 | 422 | UseXmmI2F = false; |
twisti@1020 | 423 | } |
twisti@1020 | 424 | } |
twisti@1020 | 425 | if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
twisti@1020 | 426 | if( supports_sse4a() ) { |
twisti@1020 | 427 | UseXmmI2D = true; |
twisti@1020 | 428 | } else { |
twisti@1020 | 429 | UseXmmI2D = false; |
twisti@1020 | 430 | } |
twisti@1020 | 431 | } |
kvn@2688 | 432 | if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
kvn@2688 | 433 | if( supports_sse4_2() && UseSSE >= 4 ) { |
kvn@2688 | 434 | UseSSE42Intrinsics = true; |
kvn@2688 | 435 | } |
kvn@2688 | 436 | } |
twisti@1210 | 437 | |
twisti@1210 | 438 | // Use count leading zeros count instruction if available. |
twisti@1210 | 439 | if (supports_lzcnt()) { |
twisti@1210 | 440 | if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
twisti@1210 | 441 | UseCountLeadingZerosInstruction = true; |
twisti@1210 | 442 | } |
twisti@1210 | 443 | } |
kvn@2640 | 444 | |
kvn@2640 | 445 | // On family 21 processors default is no sw prefetch |
kvn@2640 | 446 | if ( cpu_family() == 21 ) { |
kvn@2640 | 447 | if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
kvn@2640 | 448 | AllocatePrefetchStyle = 0; |
kvn@2640 | 449 | } |
kvn@2640 | 450 | } |
twisti@1020 | 451 | } |
twisti@1020 | 452 | |
twisti@1020 | 453 | if( is_intel() ) { // Intel cpus specific settings |
twisti@1020 | 454 | if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
twisti@1020 | 455 | UseStoreImmI16 = false; // don't use it on Intel cpus |
twisti@1020 | 456 | } |
twisti@1020 | 457 | if( cpu_family() == 6 || cpu_family() == 15 ) { |
twisti@1020 | 458 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
twisti@1020 | 459 | // Use it on all Intel cpus starting from PentiumPro |
twisti@1020 | 460 | UseAddressNop = true; |
twisti@1020 | 461 | } |
twisti@1020 | 462 | } |
twisti@1020 | 463 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
twisti@1020 | 464 | UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
twisti@1020 | 465 | } |
twisti@1020 | 466 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
twisti@1020 | 467 | if( supports_sse3() ) { |
twisti@1020 | 468 | UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
twisti@1020 | 469 | } else { |
twisti@1020 | 470 | UseXmmRegToRegMoveAll = false; |
twisti@1020 | 471 | } |
twisti@1020 | 472 | } |
twisti@1020 | 473 | if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
twisti@1020 | 474 | #ifdef COMPILER2 |
twisti@1020 | 475 | if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
twisti@1020 | 476 | // For new Intel cpus do the next optimization: |
twisti@1020 | 477 | // don't align the beginning of a loop if there are enough instructions |
twisti@1020 | 478 | // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
twisti@1020 | 479 | // in current fetch line (OptoLoopAlignment) or the padding |
twisti@1020 | 480 | // is big (> MaxLoopPad). |
twisti@1020 | 481 | // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
twisti@1020 | 482 | // generated NOP instructions. 11 is the largest size of one |
twisti@1020 | 483 | // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
twisti@1020 | 484 | MaxLoopPad = 11; |
twisti@1020 | 485 | } |
twisti@1020 | 486 | #endif // COMPILER2 |
twisti@1020 | 487 | if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
twisti@1020 | 488 | UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
twisti@1020 | 489 | } |
twisti@1020 | 490 | if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus |
twisti@1020 | 491 | if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
twisti@1020 | 492 | UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
twisti@1020 | 493 | } |
twisti@1020 | 494 | } |
cfang@1116 | 495 | if( supports_sse4_2() && UseSSE >= 4 ) { |
cfang@1116 | 496 | if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
cfang@1116 | 497 | UseSSE42Intrinsics = true; |
cfang@1116 | 498 | } |
cfang@1116 | 499 | } |
twisti@1020 | 500 | } |
twisti@1020 | 501 | } |
twisti@1020 | 502 | |
twisti@1078 | 503 | // Use population count instruction if available. |
twisti@1078 | 504 | if (supports_popcnt()) { |
twisti@1078 | 505 | if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
twisti@1078 | 506 | UsePopCountInstruction = true; |
twisti@1078 | 507 | } |
twisti@1078 | 508 | } |
twisti@1078 | 509 | |
never@2085 | 510 | #ifdef COMPILER2 |
never@2085 | 511 | if (UseFPUForSpilling) { |
never@2085 | 512 | if (UseSSE < 2) { |
never@2085 | 513 | // Only supported with SSE2+ |
never@2085 | 514 | FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
never@2085 | 515 | } |
never@2085 | 516 | } |
never@2085 | 517 | #endif |
never@2085 | 518 | |
twisti@1020 | 519 | assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 520 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
twisti@1020 | 521 | |
twisti@1020 | 522 | // set valid Prefetch instruction |
twisti@1020 | 523 | if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
twisti@1020 | 524 | if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
twisti@1020 | 525 | if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; |
twisti@1020 | 526 | if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3; |
twisti@1020 | 527 | |
twisti@1020 | 528 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
twisti@1020 | 529 | if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
twisti@1020 | 530 | if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; |
twisti@1020 | 531 | if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3; |
twisti@1020 | 532 | |
twisti@1020 | 533 | // Allocation prefetch settings |
twisti@1020 | 534 | intx cache_line_size = L1_data_cache_line_size(); |
twisti@1020 | 535 | if( cache_line_size > AllocatePrefetchStepSize ) |
twisti@1020 | 536 | AllocatePrefetchStepSize = cache_line_size; |
twisti@1020 | 537 | if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) |
twisti@1020 | 538 | AllocatePrefetchLines = 3; // Optimistic value |
twisti@1020 | 539 | assert(AllocatePrefetchLines > 0, "invalid value"); |
twisti@1020 | 540 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
twisti@1020 | 541 | AllocatePrefetchLines = 1; // Conservative value |
twisti@1020 | 542 | |
twisti@1020 | 543 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
twisti@1020 | 544 | AllocatePrefetchStyle = allocate_prefetch_style(); |
twisti@1020 | 545 | |
kvn@1977 | 546 | if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
kvn@1977 | 547 | if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core |
twisti@1020 | 548 | #ifdef _LP64 |
kvn@1977 | 549 | AllocatePrefetchDistance = 384; |
twisti@1020 | 550 | #else |
kvn@1977 | 551 | AllocatePrefetchDistance = 320; |
twisti@1020 | 552 | #endif |
kvn@1977 | 553 | } |
kvn@1977 | 554 | if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus |
kvn@1977 | 555 | AllocatePrefetchDistance = 192; |
kvn@1977 | 556 | AllocatePrefetchLines = 4; |
never@2085 | 557 | #ifdef COMPILER2 |
never@2085 | 558 | if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
never@2085 | 559 | FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
never@2085 | 560 | } |
never@2085 | 561 | #endif |
kvn@1977 | 562 | } |
twisti@1020 | 563 | } |
twisti@1020 | 564 | assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
twisti@1020 | 565 | |
twisti@1020 | 566 | #ifdef _LP64 |
twisti@1020 | 567 | // Prefetch settings |
twisti@1020 | 568 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
twisti@1020 | 569 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
twisti@1020 | 570 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
twisti@1020 | 571 | #endif |
twisti@1020 | 572 | |
twisti@1020 | 573 | #ifndef PRODUCT |
twisti@1020 | 574 | if (PrintMiscellaneous && Verbose) { |
twisti@1020 | 575 | tty->print_cr("Logical CPUs per core: %u", |
twisti@1020 | 576 | logical_processors_per_package()); |
twisti@1020 | 577 | tty->print_cr("UseSSE=%d",UseSSE); |
twisti@1020 | 578 | tty->print("Allocation: "); |
twisti@1020 | 579 | if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) { |
twisti@1020 | 580 | tty->print_cr("no prefetching"); |
twisti@1020 | 581 | } else { |
twisti@1020 | 582 | if (UseSSE == 0 && supports_3dnow()) { |
twisti@1020 | 583 | tty->print("PREFETCHW"); |
twisti@1020 | 584 | } else if (UseSSE >= 1) { |
twisti@1020 | 585 | if (AllocatePrefetchInstr == 0) { |
twisti@1020 | 586 | tty->print("PREFETCHNTA"); |
twisti@1020 | 587 | } else if (AllocatePrefetchInstr == 1) { |
twisti@1020 | 588 | tty->print("PREFETCHT0"); |
twisti@1020 | 589 | } else if (AllocatePrefetchInstr == 2) { |
twisti@1020 | 590 | tty->print("PREFETCHT2"); |
twisti@1020 | 591 | } else if (AllocatePrefetchInstr == 3) { |
twisti@1020 | 592 | tty->print("PREFETCHW"); |
twisti@1020 | 593 | } |
twisti@1020 | 594 | } |
twisti@1020 | 595 | if (AllocatePrefetchLines > 1) { |
twisti@1020 | 596 | tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
twisti@1020 | 597 | } else { |
twisti@1020 | 598 | tty->print_cr(" %d, one line", AllocatePrefetchDistance); |
twisti@1020 | 599 | } |
twisti@1020 | 600 | } |
twisti@1020 | 601 | |
twisti@1020 | 602 | if (PrefetchCopyIntervalInBytes > 0) { |
twisti@1020 | 603 | tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); |
twisti@1020 | 604 | } |
twisti@1020 | 605 | if (PrefetchScanIntervalInBytes > 0) { |
twisti@1020 | 606 | tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); |
twisti@1020 | 607 | } |
twisti@1020 | 608 | if (PrefetchFieldsAhead > 0) { |
twisti@1020 | 609 | tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); |
twisti@1020 | 610 | } |
twisti@1020 | 611 | } |
twisti@1020 | 612 | #endif // !PRODUCT |
twisti@1020 | 613 | } |
twisti@1020 | 614 | |
twisti@1020 | 615 | void VM_Version::initialize() { |
twisti@1020 | 616 | ResourceMark rm; |
twisti@1020 | 617 | // Making this stub must be FIRST use of assembler |
twisti@1020 | 618 | |
twisti@1020 | 619 | stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
twisti@1020 | 620 | if (stub_blob == NULL) { |
twisti@1020 | 621 | vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
twisti@1020 | 622 | } |
twisti@2103 | 623 | CodeBuffer c(stub_blob); |
twisti@1020 | 624 | VM_Version_StubGenerator g(&c); |
twisti@1020 | 625 | getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
twisti@1020 | 626 | g.generate_getPsrInfo()); |
twisti@1020 | 627 | |
twisti@1020 | 628 | get_processor_features(); |
twisti@1020 | 629 | } |