src/share/vm/c1/c1_LIRAssembler.cpp

Thu, 10 Oct 2013 15:44:12 +0200

author
anoll
date
Thu, 10 Oct 2013 15:44:12 +0200
changeset 5919
469216acdb28
parent 5628
f98f5d48f511
child 6198
55fb97c4c58d
permissions
-rw-r--r--

8023014: CodeSweeperSweepNoFlushTest.java fails with HS crash
Summary: Ensure ensure correct initialization of compiler runtime
Reviewed-by: kvn, twisti

duke@435 1 /*
coleenp@4037 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #include "precompiled.hpp"
stefank@2314 26 #include "c1/c1_Compilation.hpp"
stefank@2314 27 #include "c1/c1_Instruction.hpp"
stefank@2314 28 #include "c1/c1_InstructionPrinter.hpp"
stefank@2314 29 #include "c1/c1_LIRAssembler.hpp"
stefank@2314 30 #include "c1/c1_MacroAssembler.hpp"
stefank@2314 31 #include "c1/c1_ValueStack.hpp"
stefank@2314 32 #include "ci/ciInstance.hpp"
stefank@2314 33 #ifdef TARGET_ARCH_x86
stefank@2314 34 # include "nativeInst_x86.hpp"
stefank@2314 35 # include "vmreg_x86.inline.hpp"
stefank@2314 36 #endif
stefank@2314 37 #ifdef TARGET_ARCH_sparc
stefank@2314 38 # include "nativeInst_sparc.hpp"
stefank@2314 39 # include "vmreg_sparc.inline.hpp"
stefank@2314 40 #endif
stefank@2314 41 #ifdef TARGET_ARCH_zero
stefank@2314 42 # include "nativeInst_zero.hpp"
stefank@2314 43 # include "vmreg_zero.inline.hpp"
stefank@2314 44 #endif
bobv@2508 45 #ifdef TARGET_ARCH_arm
bobv@2508 46 # include "nativeInst_arm.hpp"
bobv@2508 47 # include "vmreg_arm.inline.hpp"
bobv@2508 48 #endif
bobv@2508 49 #ifdef TARGET_ARCH_ppc
bobv@2508 50 # include "nativeInst_ppc.hpp"
bobv@2508 51 # include "vmreg_ppc.inline.hpp"
bobv@2508 52 #endif
duke@435 53
duke@435 54
duke@435 55 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
duke@435 56 // we must have enough patching space so that call can be inserted
duke@435 57 while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeCall::instruction_size) {
duke@435 58 _masm->nop();
duke@435 59 }
duke@435 60 patch->install(_masm, patch_code, obj, info);
duke@435 61 append_patching_stub(patch);
duke@435 62
duke@435 63 #ifdef ASSERT
roland@2174 64 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
duke@435 65 if (patch->id() == PatchingStub::access_field_id) {
duke@435 66 switch (code) {
duke@435 67 case Bytecodes::_putstatic:
duke@435 68 case Bytecodes::_getstatic:
duke@435 69 case Bytecodes::_putfield:
duke@435 70 case Bytecodes::_getfield:
duke@435 71 break;
duke@435 72 default:
duke@435 73 ShouldNotReachHere();
duke@435 74 }
duke@435 75 } else if (patch->id() == PatchingStub::load_klass_id) {
duke@435 76 switch (code) {
duke@435 77 case Bytecodes::_new:
duke@435 78 case Bytecodes::_anewarray:
duke@435 79 case Bytecodes::_multianewarray:
duke@435 80 case Bytecodes::_instanceof:
duke@435 81 case Bytecodes::_checkcast:
coleenp@4037 82 break;
coleenp@4037 83 default:
coleenp@4037 84 ShouldNotReachHere();
coleenp@4037 85 }
coleenp@4037 86 } else if (patch->id() == PatchingStub::load_mirror_id) {
coleenp@4037 87 switch (code) {
coleenp@4037 88 case Bytecodes::_putstatic:
coleenp@4037 89 case Bytecodes::_getstatic:
duke@435 90 case Bytecodes::_ldc:
duke@435 91 case Bytecodes::_ldc_w:
duke@435 92 break;
duke@435 93 default:
duke@435 94 ShouldNotReachHere();
duke@435 95 }
roland@5628 96 } else if (patch->id() == PatchingStub::load_appendix_id) {
roland@5628 97 Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
roland@5628 98 assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
duke@435 99 } else {
duke@435 100 ShouldNotReachHere();
duke@435 101 }
duke@435 102 #endif
duke@435 103 }
duke@435 104
roland@5628 105 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
roland@5628 106 IRScope* scope = info->scope();
roland@5628 107 Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
roland@5628 108 if (Bytecodes::has_optional_appendix(bc_raw)) {
roland@5628 109 return PatchingStub::load_appendix_id;
roland@5628 110 }
roland@5628 111 return PatchingStub::load_mirror_id;
roland@5628 112 }
duke@435 113
duke@435 114 //---------------------------------------------------------------
duke@435 115
duke@435 116
duke@435 117 LIR_Assembler::LIR_Assembler(Compilation* c):
duke@435 118 _compilation(c)
duke@435 119 , _masm(c->masm())
ysr@777 120 , _bs(Universe::heap()->barrier_set())
duke@435 121 , _frame_map(c->frame_map())
duke@435 122 , _current_block(NULL)
duke@435 123 , _pending_non_safepoint(NULL)
duke@435 124 , _pending_non_safepoint_offset(0)
duke@435 125 {
duke@435 126 _slow_case_stubs = new CodeStubList();
duke@435 127 }
duke@435 128
duke@435 129
duke@435 130 LIR_Assembler::~LIR_Assembler() {
duke@435 131 }
duke@435 132
duke@435 133
duke@435 134 void LIR_Assembler::append_patching_stub(PatchingStub* stub) {
duke@435 135 _slow_case_stubs->append(stub);
duke@435 136 }
duke@435 137
duke@435 138
duke@435 139 void LIR_Assembler::check_codespace() {
duke@435 140 CodeSection* cs = _masm->code_section();
iveresov@3096 141 if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
duke@435 142 BAILOUT("CodeBuffer overflow");
duke@435 143 }
duke@435 144 }
duke@435 145
duke@435 146
duke@435 147 void LIR_Assembler::emit_code_stub(CodeStub* stub) {
duke@435 148 _slow_case_stubs->append(stub);
duke@435 149 }
duke@435 150
duke@435 151 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
duke@435 152 for (int m = 0; m < stub_list->length(); m++) {
duke@435 153 CodeStub* s = (*stub_list)[m];
duke@435 154
duke@435 155 check_codespace();
duke@435 156 CHECK_BAILOUT();
duke@435 157
duke@435 158 #ifndef PRODUCT
duke@435 159 if (CommentedAssembly) {
duke@435 160 stringStream st;
duke@435 161 s->print_name(&st);
duke@435 162 st.print(" slow case");
duke@435 163 _masm->block_comment(st.as_string());
duke@435 164 }
duke@435 165 #endif
duke@435 166 s->emit_code(this);
duke@435 167 #ifdef ASSERT
duke@435 168 s->assert_no_unbound_labels();
duke@435 169 #endif
duke@435 170 }
duke@435 171 }
duke@435 172
duke@435 173
duke@435 174 void LIR_Assembler::emit_slow_case_stubs() {
duke@435 175 emit_stubs(_slow_case_stubs);
duke@435 176 }
duke@435 177
duke@435 178
duke@435 179 bool LIR_Assembler::needs_icache(ciMethod* method) const {
duke@435 180 return !method->is_static();
duke@435 181 }
duke@435 182
duke@435 183
duke@435 184 int LIR_Assembler::code_offset() const {
duke@435 185 return _masm->offset();
duke@435 186 }
duke@435 187
duke@435 188
duke@435 189 address LIR_Assembler::pc() const {
duke@435 190 return _masm->pc();
duke@435 191 }
duke@435 192
duke@435 193
duke@435 194 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
duke@435 195 for (int i = 0; i < info_list->length(); i++) {
duke@435 196 XHandlers* handlers = info_list->at(i)->exception_handlers();
duke@435 197
duke@435 198 for (int j = 0; j < handlers->length(); j++) {
duke@435 199 XHandler* handler = handlers->handler_at(j);
duke@435 200 assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
duke@435 201 assert(handler->entry_code() == NULL ||
duke@435 202 handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
duke@435 203 handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
duke@435 204
duke@435 205 if (handler->entry_pco() == -1) {
duke@435 206 // entry code not emitted yet
duke@435 207 if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) {
duke@435 208 handler->set_entry_pco(code_offset());
duke@435 209 if (CommentedAssembly) {
duke@435 210 _masm->block_comment("Exception adapter block");
duke@435 211 }
duke@435 212 emit_lir_list(handler->entry_code());
duke@435 213 } else {
duke@435 214 handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
duke@435 215 }
duke@435 216
duke@435 217 assert(handler->entry_pco() != -1, "must be set now");
duke@435 218 }
duke@435 219 }
duke@435 220 }
duke@435 221 }
duke@435 222
duke@435 223
duke@435 224 void LIR_Assembler::emit_code(BlockList* hir) {
duke@435 225 if (PrintLIR) {
duke@435 226 print_LIR(hir);
duke@435 227 }
duke@435 228
duke@435 229 int n = hir->length();
duke@435 230 for (int i = 0; i < n; i++) {
duke@435 231 emit_block(hir->at(i));
duke@435 232 CHECK_BAILOUT();
duke@435 233 }
duke@435 234
duke@435 235 flush_debug_info(code_offset());
duke@435 236
duke@435 237 DEBUG_ONLY(check_no_unbound_labels());
duke@435 238 }
duke@435 239
duke@435 240
duke@435 241 void LIR_Assembler::emit_block(BlockBegin* block) {
duke@435 242 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
duke@435 243 align_backward_branch_target();
duke@435 244 }
duke@435 245
duke@435 246 // if this block is the start of an exception handler, record the
duke@435 247 // PC offset of the first instruction for later construction of
duke@435 248 // the ExceptionHandlerTable
duke@435 249 if (block->is_set(BlockBegin::exception_entry_flag)) {
duke@435 250 block->set_exception_handler_pco(code_offset());
duke@435 251 }
duke@435 252
duke@435 253 #ifndef PRODUCT
duke@435 254 if (PrintLIRWithAssembly) {
duke@435 255 // don't print Phi's
duke@435 256 InstructionPrinter ip(false);
duke@435 257 block->print(ip);
duke@435 258 }
duke@435 259 #endif /* PRODUCT */
duke@435 260
duke@435 261 assert(block->lir() != NULL, "must have LIR");
never@739 262 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
duke@435 263
duke@435 264 #ifndef PRODUCT
duke@435 265 if (CommentedAssembly) {
duke@435 266 stringStream st;
roland@2174 267 st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
duke@435 268 _masm->block_comment(st.as_string());
duke@435 269 }
duke@435 270 #endif
duke@435 271
duke@435 272 emit_lir_list(block->lir());
duke@435 273
never@739 274 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
duke@435 275 }
duke@435 276
duke@435 277
duke@435 278 void LIR_Assembler::emit_lir_list(LIR_List* list) {
duke@435 279 peephole(list);
duke@435 280
duke@435 281 int n = list->length();
duke@435 282 for (int i = 0; i < n; i++) {
duke@435 283 LIR_Op* op = list->at(i);
duke@435 284
duke@435 285 check_codespace();
duke@435 286 CHECK_BAILOUT();
duke@435 287
duke@435 288 #ifndef PRODUCT
duke@435 289 if (CommentedAssembly) {
duke@435 290 // Don't record out every op since that's too verbose. Print
duke@435 291 // branches since they include block and stub names. Also print
duke@435 292 // patching moves since they generate funny looking code.
duke@435 293 if (op->code() == lir_branch ||
duke@435 294 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) {
duke@435 295 stringStream st;
duke@435 296 op->print_on(&st);
duke@435 297 _masm->block_comment(st.as_string());
duke@435 298 }
duke@435 299 }
duke@435 300 if (PrintLIRWithAssembly) {
duke@435 301 // print out the LIR operation followed by the resulting assembly
duke@435 302 list->at(i)->print(); tty->cr();
duke@435 303 }
duke@435 304 #endif /* PRODUCT */
duke@435 305
duke@435 306 op->emit_code(this);
duke@435 307
duke@435 308 if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
duke@435 309 process_debug_info(op);
duke@435 310 }
duke@435 311
duke@435 312 #ifndef PRODUCT
duke@435 313 if (PrintLIRWithAssembly) {
duke@435 314 _masm->code()->decode();
duke@435 315 }
duke@435 316 #endif /* PRODUCT */
duke@435 317 }
duke@435 318 }
duke@435 319
duke@435 320 #ifdef ASSERT
duke@435 321 void LIR_Assembler::check_no_unbound_labels() {
duke@435 322 CHECK_BAILOUT();
duke@435 323
duke@435 324 for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
duke@435 325 if (!_branch_target_blocks.at(i)->label()->is_bound()) {
duke@435 326 tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
duke@435 327 assert(false, "unbound label");
duke@435 328 }
duke@435 329 }
duke@435 330 }
duke@435 331 #endif
duke@435 332
duke@435 333 //----------------------------------debug info--------------------------------
duke@435 334
duke@435 335
duke@435 336 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
duke@435 337 _masm->code_section()->relocate(pc(), relocInfo::poll_type);
duke@435 338 int pc_offset = code_offset();
duke@435 339 flush_debug_info(pc_offset);
duke@435 340 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
duke@435 341 if (info->exception_handlers() != NULL) {
duke@435 342 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
duke@435 343 }
duke@435 344 }
duke@435 345
duke@435 346
twisti@1919 347 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
duke@435 348 flush_debug_info(pc_offset);
twisti@1919 349 cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
duke@435 350 if (cinfo->exception_handlers() != NULL) {
duke@435 351 compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
duke@435 352 }
duke@435 353 }
duke@435 354
duke@435 355 static ValueStack* debug_info(Instruction* ins) {
duke@435 356 StateSplit* ss = ins->as_StateSplit();
duke@435 357 if (ss != NULL) return ss->state();
roland@2174 358 return ins->state_before();
duke@435 359 }
duke@435 360
duke@435 361 void LIR_Assembler::process_debug_info(LIR_Op* op) {
duke@435 362 Instruction* src = op->source();
duke@435 363 if (src == NULL) return;
duke@435 364 int pc_offset = code_offset();
duke@435 365 if (_pending_non_safepoint == src) {
duke@435 366 _pending_non_safepoint_offset = pc_offset;
duke@435 367 return;
duke@435 368 }
duke@435 369 ValueStack* vstack = debug_info(src);
duke@435 370 if (vstack == NULL) return;
duke@435 371 if (_pending_non_safepoint != NULL) {
duke@435 372 // Got some old debug info. Get rid of it.
roland@2174 373 if (debug_info(_pending_non_safepoint) == vstack) {
duke@435 374 _pending_non_safepoint_offset = pc_offset;
duke@435 375 return;
duke@435 376 }
duke@435 377 if (_pending_non_safepoint_offset < pc_offset) {
duke@435 378 record_non_safepoint_debug_info();
duke@435 379 }
duke@435 380 _pending_non_safepoint = NULL;
duke@435 381 }
duke@435 382 // Remember the debug info.
duke@435 383 if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
duke@435 384 _pending_non_safepoint = src;
duke@435 385 _pending_non_safepoint_offset = pc_offset;
duke@435 386 }
duke@435 387 }
duke@435 388
duke@435 389 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
duke@435 390 // Return NULL if n is too large.
duke@435 391 // Returns the caller_bci for the next-younger state, also.
duke@435 392 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
duke@435 393 ValueStack* t = s;
duke@435 394 for (int i = 0; i < n; i++) {
duke@435 395 if (t == NULL) break;
duke@435 396 t = t->caller_state();
duke@435 397 }
duke@435 398 if (t == NULL) return NULL;
duke@435 399 for (;;) {
duke@435 400 ValueStack* tc = t->caller_state();
duke@435 401 if (tc == NULL) return s;
duke@435 402 t = tc;
roland@2174 403 bci_result = tc->bci();
duke@435 404 s = s->caller_state();
duke@435 405 }
duke@435 406 }
duke@435 407
duke@435 408 void LIR_Assembler::record_non_safepoint_debug_info() {
duke@435 409 int pc_offset = _pending_non_safepoint_offset;
duke@435 410 ValueStack* vstack = debug_info(_pending_non_safepoint);
roland@2174 411 int bci = vstack->bci();
duke@435 412
duke@435 413 DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
duke@435 414 assert(debug_info->recording_non_safepoints(), "sanity");
duke@435 415
duke@435 416 debug_info->add_non_safepoint(pc_offset);
duke@435 417
duke@435 418 // Visit scopes from oldest to youngest.
duke@435 419 for (int n = 0; ; n++) {
duke@435 420 int s_bci = bci;
duke@435 421 ValueStack* s = nth_oldest(vstack, n, s_bci);
duke@435 422 if (s == NULL) break;
duke@435 423 IRScope* scope = s->scope();
cfang@1335 424 //Always pass false for reexecute since these ScopeDescs are never used for deopt
roland@2174 425 debug_info->describe_scope(pc_offset, scope->method(), s->bci(), false/*reexecute*/);
duke@435 426 }
duke@435 427
duke@435 428 debug_info->end_non_safepoint(pc_offset);
duke@435 429 }
duke@435 430
duke@435 431
duke@435 432 void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
duke@435 433 add_debug_info_for_null_check(code_offset(), cinfo);
duke@435 434 }
duke@435 435
duke@435 436 void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
duke@435 437 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
duke@435 438 emit_code_stub(stub);
duke@435 439 }
duke@435 440
duke@435 441 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
duke@435 442 add_debug_info_for_div0(code_offset(), info);
duke@435 443 }
duke@435 444
duke@435 445 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
duke@435 446 DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
duke@435 447 emit_code_stub(stub);
duke@435 448 }
duke@435 449
duke@435 450 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
duke@435 451 rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
duke@435 452 }
duke@435 453
duke@435 454
duke@435 455 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
duke@435 456 verify_oop_map(op->info());
duke@435 457
duke@435 458 if (os::is_MP()) {
duke@435 459 // must align calls sites, otherwise they can't be updated atomically on MP hardware
duke@435 460 align_call(op->code());
duke@435 461 }
duke@435 462
duke@435 463 // emit the static call stub stuff out of line
duke@435 464 emit_static_call_stub();
duke@435 465
duke@435 466 switch (op->code()) {
duke@435 467 case lir_static_call:
twisti@4003 468 case lir_dynamic_call:
twisti@1730 469 call(op, relocInfo::static_call_type);
duke@435 470 break;
duke@435 471 case lir_optvirtual_call:
twisti@1730 472 call(op, relocInfo::opt_virtual_call_type);
duke@435 473 break;
duke@435 474 case lir_icvirtual_call:
twisti@1730 475 ic_call(op);
duke@435 476 break;
duke@435 477 case lir_virtual_call:
twisti@1730 478 vtable_call(op);
duke@435 479 break;
twisti@4003 480 default:
twisti@4003 481 fatal(err_msg_res("unexpected op code: %s", op->name()));
twisti@4003 482 break;
duke@435 483 }
twisti@1730 484
twisti@2046 485 // JSR 292
twisti@2046 486 // Record if this method has MethodHandle invokes.
twisti@2046 487 if (op->is_method_handle_invoke()) {
twisti@2046 488 compilation()->set_has_method_handle_invokes(true);
twisti@2046 489 }
twisti@2046 490
never@739 491 #if defined(X86) && defined(TIERED)
duke@435 492 // C2 leave fpu stack dirty clean it
duke@435 493 if (UseSSE < 2) {
duke@435 494 int i;
duke@435 495 for ( i = 1; i <= 7 ; i++ ) {
duke@435 496 ffree(i);
duke@435 497 }
duke@435 498 if (!op->result_opr()->is_float_kind()) {
duke@435 499 ffree(0);
duke@435 500 }
duke@435 501 }
never@739 502 #endif // X86 && TIERED
duke@435 503 }
duke@435 504
duke@435 505
duke@435 506 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
duke@435 507 _masm->bind (*(op->label()));
duke@435 508 }
duke@435 509
duke@435 510
duke@435 511 void LIR_Assembler::emit_op1(LIR_Op1* op) {
duke@435 512 switch (op->code()) {
duke@435 513 case lir_move:
duke@435 514 if (op->move_kind() == lir_move_volatile) {
duke@435 515 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
duke@435 516 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
duke@435 517 } else {
duke@435 518 move_op(op->in_opr(), op->result_opr(), op->type(),
iveresov@2344 519 op->patch_code(), op->info(), op->pop_fpu_stack(),
iveresov@2344 520 op->move_kind() == lir_move_unaligned,
iveresov@2344 521 op->move_kind() == lir_move_wide);
duke@435 522 }
duke@435 523 break;
duke@435 524
duke@435 525 case lir_prefetchr:
duke@435 526 prefetchr(op->in_opr());
duke@435 527 break;
duke@435 528
duke@435 529 case lir_prefetchw:
duke@435 530 prefetchw(op->in_opr());
duke@435 531 break;
duke@435 532
duke@435 533 case lir_roundfp: {
duke@435 534 LIR_OpRoundFP* round_op = op->as_OpRoundFP();
duke@435 535 roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
duke@435 536 break;
duke@435 537 }
duke@435 538
duke@435 539 case lir_return:
duke@435 540 return_op(op->in_opr());
duke@435 541 break;
duke@435 542
duke@435 543 case lir_safepoint:
duke@435 544 if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
duke@435 545 _masm->nop();
duke@435 546 }
duke@435 547 safepoint_poll(op->in_opr(), op->info());
duke@435 548 break;
duke@435 549
duke@435 550 case lir_fxch:
duke@435 551 fxch(op->in_opr()->as_jint());
duke@435 552 break;
duke@435 553
duke@435 554 case lir_fld:
duke@435 555 fld(op->in_opr()->as_jint());
duke@435 556 break;
duke@435 557
duke@435 558 case lir_ffree:
duke@435 559 ffree(op->in_opr()->as_jint());
duke@435 560 break;
duke@435 561
duke@435 562 case lir_branch:
duke@435 563 break;
duke@435 564
duke@435 565 case lir_push:
duke@435 566 push(op->in_opr());
duke@435 567 break;
duke@435 568
duke@435 569 case lir_pop:
duke@435 570 pop(op->in_opr());
duke@435 571 break;
duke@435 572
duke@435 573 case lir_neg:
duke@435 574 negate(op->in_opr(), op->result_opr());
duke@435 575 break;
duke@435 576
duke@435 577 case lir_leal:
duke@435 578 leal(op->in_opr(), op->result_opr());
duke@435 579 break;
duke@435 580
duke@435 581 case lir_null_check:
duke@435 582 if (GenerateCompilerNullChecks) {
duke@435 583 add_debug_info_for_null_check_here(op->info());
duke@435 584
duke@435 585 if (op->in_opr()->is_single_cpu()) {
duke@435 586 _masm->null_check(op->in_opr()->as_register());
duke@435 587 } else {
duke@435 588 Unimplemented();
duke@435 589 }
duke@435 590 }
duke@435 591 break;
duke@435 592
duke@435 593 case lir_monaddr:
duke@435 594 monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
duke@435 595 break;
duke@435 596
iveresov@2138 597 #ifdef SPARC
iveresov@2138 598 case lir_pack64:
iveresov@2138 599 pack64(op->in_opr(), op->result_opr());
iveresov@2138 600 break;
iveresov@2138 601
iveresov@2138 602 case lir_unpack64:
iveresov@2138 603 unpack64(op->in_opr(), op->result_opr());
iveresov@2138 604 break;
iveresov@2138 605 #endif
iveresov@2138 606
never@1813 607 case lir_unwind:
never@1813 608 unwind_op(op->in_opr());
never@1813 609 break;
never@1813 610
duke@435 611 default:
duke@435 612 Unimplemented();
duke@435 613 break;
duke@435 614 }
duke@435 615 }
duke@435 616
duke@435 617
duke@435 618 void LIR_Assembler::emit_op0(LIR_Op0* op) {
duke@435 619 switch (op->code()) {
duke@435 620 case lir_word_align: {
duke@435 621 while (code_offset() % BytesPerWord != 0) {
duke@435 622 _masm->nop();
duke@435 623 }
duke@435 624 break;
duke@435 625 }
duke@435 626
duke@435 627 case lir_nop:
duke@435 628 assert(op->info() == NULL, "not supported");
duke@435 629 _masm->nop();
duke@435 630 break;
duke@435 631
duke@435 632 case lir_label:
duke@435 633 Unimplemented();
duke@435 634 break;
duke@435 635
duke@435 636 case lir_build_frame:
duke@435 637 build_frame();
duke@435 638 break;
duke@435 639
duke@435 640 case lir_std_entry:
duke@435 641 // init offsets
duke@435 642 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
duke@435 643 _masm->align(CodeEntryAlignment);
duke@435 644 if (needs_icache(compilation()->method())) {
duke@435 645 check_icache();
duke@435 646 }
duke@435 647 offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
duke@435 648 _masm->verified_entry();
duke@435 649 build_frame();
duke@435 650 offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
duke@435 651 break;
duke@435 652
duke@435 653 case lir_osr_entry:
duke@435 654 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
duke@435 655 osr_entry();
duke@435 656 break;
duke@435 657
duke@435 658 case lir_24bit_FPU:
duke@435 659 set_24bit_FPU();
duke@435 660 break;
duke@435 661
duke@435 662 case lir_reset_FPU:
duke@435 663 reset_FPU();
duke@435 664 break;
duke@435 665
duke@435 666 case lir_breakpoint:
duke@435 667 breakpoint();
duke@435 668 break;
duke@435 669
duke@435 670 case lir_fpop_raw:
duke@435 671 fpop();
duke@435 672 break;
duke@435 673
duke@435 674 case lir_membar:
duke@435 675 membar();
duke@435 676 break;
duke@435 677
duke@435 678 case lir_membar_acquire:
duke@435 679 membar_acquire();
duke@435 680 break;
duke@435 681
duke@435 682 case lir_membar_release:
duke@435 683 membar_release();
duke@435 684 break;
duke@435 685
jiangli@3592 686 case lir_membar_loadload:
jiangli@3592 687 membar_loadload();
jiangli@3592 688 break;
jiangli@3592 689
jiangli@3592 690 case lir_membar_storestore:
jiangli@3592 691 membar_storestore();
jiangli@3592 692 break;
jiangli@3592 693
jiangli@3592 694 case lir_membar_loadstore:
jiangli@3592 695 membar_loadstore();
jiangli@3592 696 break;
jiangli@3592 697
jiangli@3592 698 case lir_membar_storeload:
jiangli@3592 699 membar_storeload();
jiangli@3592 700 break;
jiangli@3592 701
duke@435 702 case lir_get_thread:
duke@435 703 get_thread(op->result_opr());
duke@435 704 break;
duke@435 705
duke@435 706 default:
duke@435 707 ShouldNotReachHere();
duke@435 708 break;
duke@435 709 }
duke@435 710 }
duke@435 711
duke@435 712
duke@435 713 void LIR_Assembler::emit_op2(LIR_Op2* op) {
duke@435 714 switch (op->code()) {
duke@435 715 case lir_cmp:
duke@435 716 if (op->info() != NULL) {
duke@435 717 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
duke@435 718 "shouldn't be codeemitinfo for non-address operands");
duke@435 719 add_debug_info_for_null_check_here(op->info()); // exception possible
duke@435 720 }
duke@435 721 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
duke@435 722 break;
duke@435 723
duke@435 724 case lir_cmp_l2i:
duke@435 725 case lir_cmp_fd2i:
duke@435 726 case lir_ucmp_fd2i:
duke@435 727 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
duke@435 728 break;
duke@435 729
duke@435 730 case lir_cmove:
iveresov@2412 731 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
duke@435 732 break;
duke@435 733
duke@435 734 case lir_shl:
duke@435 735 case lir_shr:
duke@435 736 case lir_ushr:
duke@435 737 if (op->in_opr2()->is_constant()) {
duke@435 738 shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
duke@435 739 } else {
roland@3787 740 shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
duke@435 741 }
duke@435 742 break;
duke@435 743
duke@435 744 case lir_add:
duke@435 745 case lir_sub:
duke@435 746 case lir_mul:
duke@435 747 case lir_mul_strictfp:
duke@435 748 case lir_div:
duke@435 749 case lir_div_strictfp:
duke@435 750 case lir_rem:
duke@435 751 assert(op->fpu_pop_count() < 2, "");
duke@435 752 arith_op(
duke@435 753 op->code(),
duke@435 754 op->in_opr1(),
duke@435 755 op->in_opr2(),
duke@435 756 op->result_opr(),
duke@435 757 op->info(),
duke@435 758 op->fpu_pop_count() == 1);
duke@435 759 break;
duke@435 760
duke@435 761 case lir_abs:
duke@435 762 case lir_sqrt:
duke@435 763 case lir_sin:
duke@435 764 case lir_tan:
duke@435 765 case lir_cos:
duke@435 766 case lir_log:
duke@435 767 case lir_log10:
roland@3787 768 case lir_exp:
roland@3787 769 case lir_pow:
duke@435 770 intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
duke@435 771 break;
duke@435 772
duke@435 773 case lir_logic_and:
duke@435 774 case lir_logic_or:
duke@435 775 case lir_logic_xor:
duke@435 776 logic_op(
duke@435 777 op->code(),
duke@435 778 op->in_opr1(),
duke@435 779 op->in_opr2(),
duke@435 780 op->result_opr());
duke@435 781 break;
duke@435 782
duke@435 783 case lir_throw:
never@1813 784 throw_op(op->in_opr1(), op->in_opr2(), op->info());
duke@435 785 break;
duke@435 786
roland@4106 787 case lir_xadd:
roland@4106 788 case lir_xchg:
roland@4106 789 atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
roland@4106 790 break;
roland@4106 791
duke@435 792 default:
duke@435 793 Unimplemented();
duke@435 794 break;
duke@435 795 }
duke@435 796 }
duke@435 797
duke@435 798
duke@435 799 void LIR_Assembler::build_frame() {
duke@435 800 _masm->build_frame(initial_frame_size_in_bytes());
duke@435 801 }
duke@435 802
duke@435 803
duke@435 804 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
duke@435 805 assert((src->is_single_fpu() && dest->is_single_stack()) ||
duke@435 806 (src->is_double_fpu() && dest->is_double_stack()),
duke@435 807 "round_fp: rounds register -> stack location");
duke@435 808
duke@435 809 reg2stack (src, dest, src->type(), pop_fpu_stack);
duke@435 810 }
duke@435 811
duke@435 812
iveresov@2344 813 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
duke@435 814 if (src->is_register()) {
duke@435 815 if (dest->is_register()) {
duke@435 816 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
duke@435 817 reg2reg(src, dest);
duke@435 818 } else if (dest->is_stack()) {
duke@435 819 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
duke@435 820 reg2stack(src, dest, type, pop_fpu_stack);
duke@435 821 } else if (dest->is_address()) {
iveresov@2344 822 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
duke@435 823 } else {
duke@435 824 ShouldNotReachHere();
duke@435 825 }
duke@435 826
duke@435 827 } else if (src->is_stack()) {
duke@435 828 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
duke@435 829 if (dest->is_register()) {
duke@435 830 stack2reg(src, dest, type);
duke@435 831 } else if (dest->is_stack()) {
duke@435 832 stack2stack(src, dest, type);
duke@435 833 } else {
duke@435 834 ShouldNotReachHere();
duke@435 835 }
duke@435 836
duke@435 837 } else if (src->is_constant()) {
duke@435 838 if (dest->is_register()) {
duke@435 839 const2reg(src, dest, patch_code, info); // patching is possible
duke@435 840 } else if (dest->is_stack()) {
duke@435 841 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
duke@435 842 const2stack(src, dest);
duke@435 843 } else if (dest->is_address()) {
duke@435 844 assert(patch_code == lir_patch_none, "no patching allowed here");
iveresov@2344 845 const2mem(src, dest, type, info, wide);
duke@435 846 } else {
duke@435 847 ShouldNotReachHere();
duke@435 848 }
duke@435 849
duke@435 850 } else if (src->is_address()) {
iveresov@2344 851 mem2reg(src, dest, type, patch_code, info, wide, unaligned);
duke@435 852
duke@435 853 } else {
duke@435 854 ShouldNotReachHere();
duke@435 855 }
duke@435 856 }
duke@435 857
duke@435 858
duke@435 859 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
duke@435 860 #ifndef PRODUCT
duke@435 861 if (VerifyOopMaps || VerifyOops) {
duke@435 862 bool v = VerifyOops;
duke@435 863 VerifyOops = true;
duke@435 864 OopMapStream s(info->oop_map());
duke@435 865 while (!s.is_done()) {
duke@435 866 OopMapValue v = s.current();
duke@435 867 if (v.is_oop()) {
duke@435 868 VMReg r = v.reg();
duke@435 869 if (!r->is_stack()) {
duke@435 870 stringStream st;
duke@435 871 st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset());
duke@435 872 #ifdef SPARC
duke@435 873 _masm->_verify_oop(r->as_Register(), strdup(st.as_string()), __FILE__, __LINE__);
duke@435 874 #else
duke@435 875 _masm->verify_oop(r->as_Register());
duke@435 876 #endif
duke@435 877 } else {
duke@435 878 _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
duke@435 879 }
duke@435 880 }
never@2733 881 check_codespace();
never@2733 882 CHECK_BAILOUT();
never@2733 883
duke@435 884 s.next();
duke@435 885 }
duke@435 886 VerifyOops = v;
duke@435 887 }
duke@435 888 #endif
duke@435 889 }

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