src/cpu/x86/vm/vmreg_x86.inline.hpp

Thu, 03 Nov 2011 04:12:49 -0700

author
twisti
date
Thu, 03 Nov 2011 04:12:49 -0700
changeset 3252
448691f285a5
parent 2314
f95d63e2154a
child 3882
8c92982cbbc4
permissions
-rw-r--r--

7106944: assert(_pc == *pc_addr) failed may be too strong
Reviewed-by: kvn, never

duke@435 1 /*
stefank@2314 2 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef CPU_X86_VM_VMREG_X86_INLINE_HPP
stefank@2314 26 #define CPU_X86_VM_VMREG_X86_INLINE_HPP
stefank@2314 27
duke@435 28 inline VMReg RegisterImpl::as_VMReg() {
duke@435 29 if( this==noreg ) return VMRegImpl::Bad();
duke@435 30 #ifdef AMD64
duke@435 31 return VMRegImpl::as_VMReg(encoding() << 1 );
duke@435 32 #else
duke@435 33 return VMRegImpl::as_VMReg(encoding() );
duke@435 34 #endif // AMD64
duke@435 35 }
duke@435 36
duke@435 37 inline VMReg FloatRegisterImpl::as_VMReg() {
duke@435 38 return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
duke@435 39 }
duke@435 40
duke@435 41 inline VMReg XMMRegisterImpl::as_VMReg() {
duke@435 42 return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_fpr);
duke@435 43 }
duke@435 44
duke@435 45
duke@435 46 inline bool VMRegImpl::is_Register() {
duke@435 47 return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
duke@435 48 }
duke@435 49
duke@435 50 inline bool VMRegImpl::is_FloatRegister() {
duke@435 51 return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
duke@435 52 }
duke@435 53
duke@435 54 inline bool VMRegImpl::is_XMMRegister() {
duke@435 55 return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_xmm;
duke@435 56 }
duke@435 57
duke@435 58 inline Register VMRegImpl::as_Register() {
duke@435 59
duke@435 60 assert( is_Register(), "must be");
duke@435 61 // Yuk
duke@435 62 #ifdef AMD64
duke@435 63 return ::as_Register(value() >> 1);
duke@435 64 #else
duke@435 65 return ::as_Register(value());
duke@435 66 #endif // AMD64
duke@435 67 }
duke@435 68
duke@435 69 inline FloatRegister VMRegImpl::as_FloatRegister() {
duke@435 70 assert( is_FloatRegister() && is_even(value()), "must be" );
duke@435 71 // Yuk
duke@435 72 return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
duke@435 73 }
duke@435 74
duke@435 75 inline XMMRegister VMRegImpl::as_XMMRegister() {
duke@435 76 assert( is_XMMRegister() && is_even(value()), "must be" );
duke@435 77 // Yuk
duke@435 78 return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 1);
duke@435 79 }
duke@435 80
duke@435 81 inline bool VMRegImpl::is_concrete() {
duke@435 82 assert(is_reg(), "must be");
duke@435 83 #ifndef AMD64
duke@435 84 if (is_Register()) return true;
duke@435 85 #endif // AMD64
duke@435 86 return is_even(value());
duke@435 87 }
stefank@2314 88
stefank@2314 89 #endif // CPU_X86_VM_VMREG_X86_INLINE_HPP

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