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src/cpu/x86/vm/register_x86.hpp@437d03ea40b1 (annotated)

src/cpu/x86/vm/register_x86.hpp

Wed, 21 May 2008 16:31:35 -0700

author

kvn

date

Wed, 21 May 2008 16:31:35 -0700

changeset 600

437d03ea40b1

parent 435

a61af66fc99e

child 1907

c18cbe5936b8

permissions

-rw-r--r--

6703888: Compressed Oops: use the 32-bits gap after klass in a object
Summary: Use the gap also for a narrow oop field and a boxing object value.
Reviewed-by: coleenp, never

duke@435	1	/*
duke@435	2	* Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	class VMRegImpl;
duke@435	26	typedef VMRegImpl* VMReg;
duke@435	27
duke@435	28	// Use Register as shortcut
duke@435	29	class RegisterImpl;
duke@435	30	typedef RegisterImpl* Register;
duke@435	31
duke@435	32
duke@435	33	// The implementation of integer registers for the ia32 architecture
duke@435	34	inline Register as_Register(int encoding) {
duke@435	35	return (Register)(intptr_t) encoding;
duke@435	36	}
duke@435	37
duke@435	38	class RegisterImpl: public AbstractRegisterImpl {
duke@435	39	public:
duke@435	40	enum {
duke@435	41	#ifndef AMD64
duke@435	42	number_of_registers = 8,
duke@435	43	number_of_byte_registers = 4
duke@435	44	#else
duke@435	45	number_of_registers = 16,
duke@435	46	number_of_byte_registers = 16
duke@435	47	#endif // AMD64
duke@435	48	};
duke@435	49
duke@435	50	// derived registers, offsets, and addresses
duke@435	51	Register successor() const { return as_Register(encoding() + 1); }
duke@435	52
duke@435	53	// construction
duke@435	54	inline friend Register as_Register(int encoding);
duke@435	55
duke@435	56	VMReg as_VMReg();
duke@435	57
duke@435	58	// accessors
duke@435	59	int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
duke@435	60	bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
duke@435	61	bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
duke@435	62	const char* name() const;
duke@435	63	};
duke@435	64
duke@435	65	// The integer registers of the ia32/amd64 architecture
duke@435	66
duke@435	67	CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
duke@435	68
duke@435	69
duke@435	70	CONSTANT_REGISTER_DECLARATION(Register, rax, (0));
duke@435	71	CONSTANT_REGISTER_DECLARATION(Register, rcx, (1));
duke@435	72	CONSTANT_REGISTER_DECLARATION(Register, rdx, (2));
duke@435	73	CONSTANT_REGISTER_DECLARATION(Register, rbx, (3));
duke@435	74	CONSTANT_REGISTER_DECLARATION(Register, rsp, (4));
duke@435	75	CONSTANT_REGISTER_DECLARATION(Register, rbp, (5));
duke@435	76	CONSTANT_REGISTER_DECLARATION(Register, rsi, (6));
duke@435	77	CONSTANT_REGISTER_DECLARATION(Register, rdi, (7));
duke@435	78	#ifdef AMD64
duke@435	79	CONSTANT_REGISTER_DECLARATION(Register, r8, (8));
duke@435	80	CONSTANT_REGISTER_DECLARATION(Register, r9, (9));
duke@435	81	CONSTANT_REGISTER_DECLARATION(Register, r10, (10));
duke@435	82	CONSTANT_REGISTER_DECLARATION(Register, r11, (11));
duke@435	83	CONSTANT_REGISTER_DECLARATION(Register, r12, (12));
duke@435	84	CONSTANT_REGISTER_DECLARATION(Register, r13, (13));
duke@435	85	CONSTANT_REGISTER_DECLARATION(Register, r14, (14));
duke@435	86	CONSTANT_REGISTER_DECLARATION(Register, r15, (15));
duke@435	87	#endif // AMD64
duke@435	88
duke@435	89	// Use FloatRegister as shortcut
duke@435	90	class FloatRegisterImpl;
duke@435	91	typedef FloatRegisterImpl* FloatRegister;
duke@435	92
duke@435	93	inline FloatRegister as_FloatRegister(int encoding) {
duke@435	94	return (FloatRegister)(intptr_t) encoding;
duke@435	95	}
duke@435	96
duke@435	97	// The implementation of floating point registers for the ia32 architecture
duke@435	98	class FloatRegisterImpl: public AbstractRegisterImpl {
duke@435	99	public:
duke@435	100	enum {
duke@435	101	number_of_registers = 8
duke@435	102	};
duke@435	103
duke@435	104	// construction
duke@435	105	inline friend FloatRegister as_FloatRegister(int encoding);
duke@435	106
duke@435	107	VMReg as_VMReg();
duke@435	108
duke@435	109	// derived registers, offsets, and addresses
duke@435	110	FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
duke@435	111
duke@435	112	// accessors
duke@435	113	int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
duke@435	114	bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
duke@435	115	const char* name() const;
duke@435	116
duke@435	117	};
duke@435	118
duke@435	119	// Use XMMRegister as shortcut
duke@435	120	class XMMRegisterImpl;
duke@435	121	typedef XMMRegisterImpl* XMMRegister;
duke@435	122
duke@435	123	// Use MMXRegister as shortcut
duke@435	124	class MMXRegisterImpl;
duke@435	125	typedef MMXRegisterImpl* MMXRegister;
duke@435	126
duke@435	127	inline XMMRegister as_XMMRegister(int encoding) {
duke@435	128	return (XMMRegister)(intptr_t)encoding;
duke@435	129	}
duke@435	130
duke@435	131	inline MMXRegister as_MMXRegister(int encoding) {
duke@435	132	return (MMXRegister)(intptr_t)encoding;
duke@435	133	}
duke@435	134
duke@435	135	// The implementation of XMM registers for the IA32 architecture
duke@435	136	class XMMRegisterImpl: public AbstractRegisterImpl {
duke@435	137	public:
duke@435	138	enum {
duke@435	139	#ifndef AMD64
duke@435	140	number_of_registers = 8
duke@435	141	#else
duke@435	142	number_of_registers = 16
duke@435	143	#endif // AMD64
duke@435	144	};
duke@435	145
duke@435	146	// construction
duke@435	147	friend XMMRegister as_XMMRegister(int encoding);
duke@435	148
duke@435	149	VMReg as_VMReg();
duke@435	150
duke@435	151	// derived registers, offsets, and addresses
duke@435	152	XMMRegister successor() const { return as_XMMRegister(encoding() + 1); }
duke@435	153
duke@435	154	// accessors
duke@435	155	int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
duke@435	156	bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
duke@435	157	const char* name() const;
duke@435	158	};
duke@435	159
duke@435	160
duke@435	161	// The XMM registers, for P3 and up chips
duke@435	162	CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
duke@435	163	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
duke@435	164	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
duke@435	165	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
duke@435	166	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
duke@435	167	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
duke@435	168	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
duke@435	169	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
duke@435	170	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
duke@435	171	#ifdef AMD64
duke@435	172	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8));
duke@435	173	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9));
duke@435	174	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10));
duke@435	175	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11));
duke@435	176	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12));
duke@435	177	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13));
duke@435	178	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14));
duke@435	179	CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15));
duke@435	180	#endif // AMD64
duke@435	181
duke@435	182	// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence
duke@435	183	// can't be described in oopMaps and therefore can't be used by the compilers (at least
duke@435	184	// were deopt might wan't to see them).
duke@435	185
duke@435	186	// The MMX registers, for P3 and up chips
duke@435	187	CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1));
duke@435	188	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0));
duke@435	189	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1));
duke@435	190	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2));
duke@435	191	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3));
duke@435	192	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4));
duke@435	193	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
duke@435	194	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
duke@435	195	CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
duke@435	196
duke@435	197
duke@435	198	// Need to know the total number of registers of all sorts for SharedInfo.
duke@435	199	// Define a class that exports it.
duke@435	200	class ConcreteRegisterImpl : public AbstractRegisterImpl {
duke@435	201	public:
duke@435	202	enum {
duke@435	203	// A big enough number for C2: all the registers plus flags
duke@435	204	// This number must be large enough to cover REG_COUNT (defined by c2) registers.
duke@435	205	// There is no requirement that any ordering here matches any ordering c2 gives
duke@435	206	// it's optoregs.
duke@435	207
duke@435	208	number_of_registers = RegisterImpl::number_of_registers +
duke@435	209	#ifdef AMD64
duke@435	210	RegisterImpl::number_of_registers + // "H" half of a 64bit register
duke@435	211	#endif // AMD64
duke@435	212	2 * FloatRegisterImpl::number_of_registers +
duke@435	213	2 * XMMRegisterImpl::number_of_registers +
duke@435	214	1 // eflags
duke@435	215	};
duke@435	216
duke@435	217	static const int max_gpr;
duke@435	218	static const int max_fpr;
duke@435	219	static const int max_xmm;
duke@435	220
duke@435	221	};