src/cpu/ppc/vm/icache_ppc.hpp

Wed, 27 Nov 2013 16:16:21 -0800

author
goetz
date
Wed, 27 Nov 2013 16:16:21 -0800
changeset 6490
41b780b43b74
parent 6458
ec28f9c041ff
child 6495
67fa91961822
permissions
-rw-r--r--

8029015: PPC64 (part 216): opto: trap based null and range checks
Summary: On PPC64 use tdi instruction that does a compare and raises SIGTRAP for NULL and range checks.
Reviewed-by: kvn

goetz@6458 1 /*
goetz@6458 2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
goetz@6458 3 * Copyright 2012, 2013 SAP AG. All rights reserved.
goetz@6458 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
goetz@6458 5 *
goetz@6458 6 * This code is free software; you can redistribute it and/or modify it
goetz@6458 7 * under the terms of the GNU General Public License version 2 only, as
goetz@6458 8 * published by the Free Software Foundation.
goetz@6458 9 *
goetz@6458 10 * This code is distributed in the hope that it will be useful, but WITHOUT
goetz@6458 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
goetz@6458 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
goetz@6458 13 * version 2 for more details (a copy is included in the LICENSE file that
goetz@6458 14 * accompanied this code).
goetz@6458 15 *
goetz@6458 16 * You should have received a copy of the GNU General Public License version
goetz@6458 17 * 2 along with this work; if not, write to the Free Software Foundation,
goetz@6458 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
goetz@6458 19 *
goetz@6458 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
goetz@6458 21 * or visit www.oracle.com if you need additional information or have any
goetz@6458 22 * questions.
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goetz@6458 24 */
goetz@6458 25
goetz@6458 26 #ifndef CPU_PPC_VM_ICACHE_PPC_HPP
goetz@6458 27 #define CPU_PPC_VM_ICACHE_PPC_HPP
goetz@6458 28
goetz@6458 29 // Interface for updating the instruction cache. Whenever the VM modifies
goetz@6458 30 // code, part of the processor instruction cache potentially has to be flushed.
goetz@6458 31
goetz@6458 32 class ICache : public AbstractICache {
goetz@6458 33 public:
goetz@6458 34 enum {
goetz@6458 35 // On PowerPC the cache line size is 32 bytes.
goetz@6458 36 stub_size = 160, // Size of the icache flush stub in bytes.
goetz@6458 37 line_size = 32, // Flush instruction affects 32 bytes.
goetz@6458 38 log2_line_size = 5 // log2(line_size)
goetz@6458 39 };
goetz@6458 40
goetz@6458 41 // Use default implementation
goetz@6458 42 };
goetz@6458 43
goetz@6458 44 #endif // CPU_PPC_VM_ICACHE_PPC_HPP

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