Tue, 09 Mar 2010 20:16:19 +0100
6919934: JSR 292 needs to support x86 C1
Summary: This implements JSR 292 support for C1 x86.
Reviewed-by: never, jrose, kvn
duke@435 | 1 | /* |
xdono@1279 | 2 | * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | class Compile; |
duke@435 | 26 | class Node; |
duke@435 | 27 | class MachNode; |
duke@435 | 28 | class MachTypeNode; |
duke@435 | 29 | class MachOper; |
duke@435 | 30 | |
duke@435 | 31 | //---------------------------Matcher------------------------------------------- |
duke@435 | 32 | class Matcher : public PhaseTransform { |
duke@435 | 33 | friend class VMStructs; |
duke@435 | 34 | // Private arena of State objects |
duke@435 | 35 | ResourceArea _states_arena; |
duke@435 | 36 | |
duke@435 | 37 | VectorSet _visited; // Visit bits |
duke@435 | 38 | |
duke@435 | 39 | // Used to control the Label pass |
duke@435 | 40 | VectorSet _shared; // Shared Ideal Node |
duke@435 | 41 | VectorSet _dontcare; // Nothing the matcher cares about |
duke@435 | 42 | |
duke@435 | 43 | // Private methods which perform the actual matching and reduction |
duke@435 | 44 | // Walks the label tree, generating machine nodes |
duke@435 | 45 | MachNode *ReduceInst( State *s, int rule, Node *&mem); |
duke@435 | 46 | void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); |
duke@435 | 47 | uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); |
duke@435 | 48 | void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); |
duke@435 | 49 | |
duke@435 | 50 | // If this node already matched using "rule", return the MachNode for it. |
kvn@603 | 51 | MachNode* find_shared_node(Node* n, uint rule); |
duke@435 | 52 | |
duke@435 | 53 | // Convert a dense opcode number to an expanded rule number |
duke@435 | 54 | const int *_reduceOp; |
duke@435 | 55 | const int *_leftOp; |
duke@435 | 56 | const int *_rightOp; |
duke@435 | 57 | |
duke@435 | 58 | // Map dense opcode number to info on when rule is swallowed constant. |
duke@435 | 59 | const bool *_swallowed; |
duke@435 | 60 | |
duke@435 | 61 | // Map dense rule number to determine if this is an instruction chain rule |
duke@435 | 62 | const uint _begin_inst_chain_rule; |
duke@435 | 63 | const uint _end_inst_chain_rule; |
duke@435 | 64 | |
duke@435 | 65 | // We want to clone constants and possible CmpI-variants. |
duke@435 | 66 | // If we do not clone CmpI, then we can have many instances of |
duke@435 | 67 | // condition codes alive at once. This is OK on some chips and |
duke@435 | 68 | // bad on others. Hence the machine-dependent table lookup. |
duke@435 | 69 | const char *_must_clone; |
duke@435 | 70 | |
duke@435 | 71 | // Find shared Nodes, or Nodes that otherwise are Matcher roots |
duke@435 | 72 | void find_shared( Node *n ); |
duke@435 | 73 | |
duke@435 | 74 | // Debug and profile information for nodes in old space: |
duke@435 | 75 | GrowableArray<Node_Notes*>* _old_node_note_array; |
duke@435 | 76 | |
duke@435 | 77 | // Node labeling iterator for instruction selection |
duke@435 | 78 | Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); |
duke@435 | 79 | |
duke@435 | 80 | Node *transform( Node *dummy ); |
duke@435 | 81 | |
duke@435 | 82 | Node_List &_proj_list; // For Machine nodes killing many values |
duke@435 | 83 | |
kvn@603 | 84 | Node_Array _shared_nodes; |
duke@435 | 85 | |
duke@435 | 86 | debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots |
never@657 | 87 | debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal |
duke@435 | 88 | |
duke@435 | 89 | // Accessors for the inherited field PhaseTransform::_nodes: |
duke@435 | 90 | void grow_new_node_array(uint idx_limit) { |
duke@435 | 91 | _nodes.map(idx_limit-1, NULL); |
duke@435 | 92 | } |
duke@435 | 93 | bool has_new_node(const Node* n) const { |
duke@435 | 94 | return _nodes.at(n->_idx) != NULL; |
duke@435 | 95 | } |
duke@435 | 96 | Node* new_node(const Node* n) const { |
duke@435 | 97 | assert(has_new_node(n), "set before get"); |
duke@435 | 98 | return _nodes.at(n->_idx); |
duke@435 | 99 | } |
duke@435 | 100 | void set_new_node(const Node* n, Node *nn) { |
duke@435 | 101 | assert(!has_new_node(n), "set only once"); |
duke@435 | 102 | _nodes.map(n->_idx, nn); |
duke@435 | 103 | } |
duke@435 | 104 | |
duke@435 | 105 | #ifdef ASSERT |
duke@435 | 106 | // Make sure only new nodes are reachable from this node |
duke@435 | 107 | void verify_new_nodes_only(Node* root); |
kvn@651 | 108 | |
kvn@651 | 109 | Node* _mem_node; // Ideal memory node consumed by mach node |
duke@435 | 110 | #endif |
duke@435 | 111 | |
kvn@1164 | 112 | // Mach node for ConP #NULL |
kvn@1164 | 113 | MachNode* _mach_null; |
kvn@1164 | 114 | |
duke@435 | 115 | public: |
duke@435 | 116 | int LabelRootDepth; |
duke@435 | 117 | static const int base2reg[]; // Map Types to machine register types |
duke@435 | 118 | // Convert ideal machine register to a register mask for spill-loads |
duke@435 | 119 | static const RegMask *idealreg2regmask[]; |
twisti@1572 | 120 | RegMask *idealreg2spillmask [_last_machine_leaf]; |
twisti@1572 | 121 | RegMask *idealreg2debugmask [_last_machine_leaf]; |
twisti@1572 | 122 | RegMask *idealreg2mhdebugmask[_last_machine_leaf]; |
duke@435 | 123 | void init_spill_mask( Node *ret ); |
duke@435 | 124 | // Convert machine register number to register mask |
duke@435 | 125 | static uint mreg2regmask_max; |
duke@435 | 126 | static RegMask mreg2regmask[]; |
duke@435 | 127 | static RegMask STACK_ONLY_mask; |
duke@435 | 128 | |
kvn@1164 | 129 | MachNode* mach_null() const { return _mach_null; } |
kvn@1164 | 130 | |
duke@435 | 131 | bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } |
duke@435 | 132 | void set_shared( Node *n ) { _shared.set(n->_idx); } |
duke@435 | 133 | bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } |
duke@435 | 134 | void set_visited( Node *n ) { _visited.set(n->_idx); } |
duke@435 | 135 | bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } |
duke@435 | 136 | void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } |
duke@435 | 137 | |
duke@435 | 138 | // Mode bit to tell DFA and expand rules whether we are running after |
duke@435 | 139 | // (or during) register selection. Usually, the matcher runs before, |
duke@435 | 140 | // but it will also get called to generate post-allocation spill code. |
duke@435 | 141 | // In this situation, it is a deadly error to attempt to allocate more |
duke@435 | 142 | // temporary registers. |
duke@435 | 143 | bool _allocation_started; |
duke@435 | 144 | |
duke@435 | 145 | // Machine register names |
duke@435 | 146 | static const char *regName[]; |
duke@435 | 147 | // Machine register encodings |
duke@435 | 148 | static const unsigned char _regEncode[]; |
duke@435 | 149 | // Machine Node names |
duke@435 | 150 | const char **_ruleName; |
duke@435 | 151 | // Rules that are cheaper to rematerialize than to spill |
duke@435 | 152 | static const uint _begin_rematerialize; |
duke@435 | 153 | static const uint _end_rematerialize; |
duke@435 | 154 | |
duke@435 | 155 | // An array of chars, from 0 to _last_Mach_Reg. |
duke@435 | 156 | // No Save = 'N' (for register windows) |
duke@435 | 157 | // Save on Entry = 'E' |
duke@435 | 158 | // Save on Call = 'C' |
duke@435 | 159 | // Always Save = 'A' (same as SOE + SOC) |
duke@435 | 160 | const char *_register_save_policy; |
duke@435 | 161 | const char *_c_reg_save_policy; |
duke@435 | 162 | // Convert a machine register to a machine register type, so-as to |
duke@435 | 163 | // properly match spill code. |
duke@435 | 164 | const int *_register_save_type; |
duke@435 | 165 | // Maps from machine register to boolean; true if machine register can |
duke@435 | 166 | // be holding a call argument in some signature. |
duke@435 | 167 | static bool can_be_java_arg( int reg ); |
duke@435 | 168 | // Maps from machine register to boolean; true if machine register holds |
duke@435 | 169 | // a spillable argument. |
duke@435 | 170 | static bool is_spillable_arg( int reg ); |
duke@435 | 171 | |
duke@435 | 172 | // List of IfFalse or IfTrue Nodes that indicate a taken null test. |
duke@435 | 173 | // List is valid in the post-matching space. |
duke@435 | 174 | Node_List _null_check_tests; |
kvn@803 | 175 | void collect_null_checks( Node *proj, Node *orig_proj ); |
duke@435 | 176 | void validate_null_checks( ); |
duke@435 | 177 | |
duke@435 | 178 | Matcher( Node_List &proj_list ); |
duke@435 | 179 | |
duke@435 | 180 | // Select instructions for entire method |
duke@435 | 181 | void match( ); |
duke@435 | 182 | // Helper for match |
duke@435 | 183 | OptoReg::Name warp_incoming_stk_arg( VMReg reg ); |
duke@435 | 184 | |
duke@435 | 185 | // Transform, then walk. Does implicit DCE while walking. |
duke@435 | 186 | // Name changed from "transform" to avoid it being virtual. |
duke@435 | 187 | Node *xform( Node *old_space_node, int Nodes ); |
duke@435 | 188 | |
duke@435 | 189 | // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. |
duke@435 | 190 | MachNode *match_tree( const Node *n ); |
duke@435 | 191 | MachNode *match_sfpt( SafePointNode *sfpt ); |
duke@435 | 192 | // Helper for match_sfpt |
duke@435 | 193 | OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); |
duke@435 | 194 | |
duke@435 | 195 | // Initialize first stack mask and related masks. |
duke@435 | 196 | void init_first_stack_mask(); |
duke@435 | 197 | |
duke@435 | 198 | // If we should save-on-entry this register |
duke@435 | 199 | bool is_save_on_entry( int reg ); |
duke@435 | 200 | |
duke@435 | 201 | // Fixup the save-on-entry registers |
duke@435 | 202 | void Fixup_Save_On_Entry( ); |
duke@435 | 203 | |
duke@435 | 204 | // --- Frame handling --- |
duke@435 | 205 | |
duke@435 | 206 | // Register number of the stack slot corresponding to the incoming SP. |
duke@435 | 207 | // Per the Big Picture in the AD file, it is: |
duke@435 | 208 | // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. |
duke@435 | 209 | OptoReg::Name _old_SP; |
duke@435 | 210 | |
duke@435 | 211 | // Register number of the stack slot corresponding to the highest incoming |
duke@435 | 212 | // argument on the stack. Per the Big Picture in the AD file, it is: |
duke@435 | 213 | // _old_SP + out_preserve_stack_slots + incoming argument size. |
duke@435 | 214 | OptoReg::Name _in_arg_limit; |
duke@435 | 215 | |
duke@435 | 216 | // Register number of the stack slot corresponding to the new SP. |
duke@435 | 217 | // Per the Big Picture in the AD file, it is: |
duke@435 | 218 | // _in_arg_limit + pad0 |
duke@435 | 219 | OptoReg::Name _new_SP; |
duke@435 | 220 | |
duke@435 | 221 | // Register number of the stack slot corresponding to the highest outgoing |
duke@435 | 222 | // argument on the stack. Per the Big Picture in the AD file, it is: |
duke@435 | 223 | // _new_SP + max outgoing arguments of all calls |
duke@435 | 224 | OptoReg::Name _out_arg_limit; |
duke@435 | 225 | |
duke@435 | 226 | OptoRegPair *_parm_regs; // Array of machine registers per argument |
duke@435 | 227 | RegMask *_calling_convention_mask; // Array of RegMasks per argument |
duke@435 | 228 | |
twisti@1210 | 229 | // Does matcher have a match rule for this ideal node? |
duke@435 | 230 | static const bool has_match_rule(int opcode); |
duke@435 | 231 | static const bool _hasMatchRule[_last_opcode]; |
duke@435 | 232 | |
twisti@1210 | 233 | // Does matcher have a match rule for this ideal node and is the |
twisti@1210 | 234 | // predicate (if there is one) true? |
twisti@1210 | 235 | // NOTE: If this function is used more commonly in the future, ADLC |
twisti@1210 | 236 | // should generate this one. |
twisti@1210 | 237 | static const bool match_rule_supported(int opcode); |
twisti@1210 | 238 | |
duke@435 | 239 | // Used to determine if we have fast l2f conversion |
duke@435 | 240 | // USII has it, USIII doesn't |
duke@435 | 241 | static const bool convL2FSupported(void); |
duke@435 | 242 | |
duke@435 | 243 | // Vector width in bytes |
duke@435 | 244 | static const uint vector_width_in_bytes(void); |
duke@435 | 245 | |
duke@435 | 246 | // Vector ideal reg |
duke@435 | 247 | static const uint vector_ideal_reg(void); |
duke@435 | 248 | |
duke@435 | 249 | // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) |
duke@435 | 250 | // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). |
duke@435 | 251 | // Depends on the details of 64-bit constant generation on the CPU. |
duke@435 | 252 | static const bool isSimpleConstant64(jlong con); |
duke@435 | 253 | |
duke@435 | 254 | // These calls are all generated by the ADLC |
duke@435 | 255 | |
duke@435 | 256 | // TRUE - grows up, FALSE - grows down (Intel) |
duke@435 | 257 | virtual bool stack_direction() const; |
duke@435 | 258 | |
duke@435 | 259 | // Java-Java calling convention |
duke@435 | 260 | // (what you use when Java calls Java) |
duke@435 | 261 | |
duke@435 | 262 | // Alignment of stack in bytes, standard Intel word alignment is 4. |
duke@435 | 263 | // Sparc probably wants at least double-word (8). |
duke@435 | 264 | static uint stack_alignment_in_bytes(); |
duke@435 | 265 | // Alignment of stack, measured in stack slots. |
duke@435 | 266 | // The size of stack slots is defined by VMRegImpl::stack_slot_size. |
duke@435 | 267 | static uint stack_alignment_in_slots() { |
duke@435 | 268 | return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); |
duke@435 | 269 | } |
duke@435 | 270 | |
duke@435 | 271 | // Array mapping arguments to registers. Argument 0 is usually the 'this' |
duke@435 | 272 | // pointer. Registers can include stack-slots and regular registers. |
duke@435 | 273 | static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); |
duke@435 | 274 | |
duke@435 | 275 | // Convert a sig into a calling convention register layout |
duke@435 | 276 | // and find interesting things about it. |
duke@435 | 277 | static OptoReg::Name find_receiver( bool is_outgoing ); |
duke@435 | 278 | // Return address register. On Intel it is a stack-slot. On PowerPC |
duke@435 | 279 | // it is the Link register. On Sparc it is r31? |
duke@435 | 280 | virtual OptoReg::Name return_addr() const; |
duke@435 | 281 | RegMask _return_addr_mask; |
duke@435 | 282 | // Return value register. On Intel it is EAX. On Sparc i0/o0. |
duke@435 | 283 | static OptoRegPair return_value(int ideal_reg, bool is_outgoing); |
duke@435 | 284 | static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); |
duke@435 | 285 | RegMask _return_value_mask; |
duke@435 | 286 | // Inline Cache Register |
duke@435 | 287 | static OptoReg::Name inline_cache_reg(); |
duke@435 | 288 | static const RegMask &inline_cache_reg_mask(); |
duke@435 | 289 | static int inline_cache_reg_encode(); |
duke@435 | 290 | |
duke@435 | 291 | // Register for DIVI projection of divmodI |
duke@435 | 292 | static RegMask divI_proj_mask(); |
duke@435 | 293 | // Register for MODI projection of divmodI |
duke@435 | 294 | static RegMask modI_proj_mask(); |
duke@435 | 295 | |
duke@435 | 296 | // Register for DIVL projection of divmodL |
duke@435 | 297 | static RegMask divL_proj_mask(); |
duke@435 | 298 | // Register for MODL projection of divmodL |
duke@435 | 299 | static RegMask modL_proj_mask(); |
duke@435 | 300 | |
twisti@1572 | 301 | static const RegMask method_handle_invoke_SP_save_mask(); |
twisti@1572 | 302 | |
duke@435 | 303 | // Java-Interpreter calling convention |
duke@435 | 304 | // (what you use when calling between compiled-Java and Interpreted-Java |
duke@435 | 305 | |
duke@435 | 306 | // Number of callee-save + always-save registers |
duke@435 | 307 | // Ignores frame pointer and "special" registers |
duke@435 | 308 | static int number_of_saved_registers(); |
duke@435 | 309 | |
duke@435 | 310 | // The Method-klass-holder may be passed in the inline_cache_reg |
duke@435 | 311 | // and then expanded into the inline_cache_reg and a method_oop register |
duke@435 | 312 | |
duke@435 | 313 | static OptoReg::Name interpreter_method_oop_reg(); |
duke@435 | 314 | static const RegMask &interpreter_method_oop_reg_mask(); |
duke@435 | 315 | static int interpreter_method_oop_reg_encode(); |
duke@435 | 316 | |
duke@435 | 317 | static OptoReg::Name compiler_method_oop_reg(); |
duke@435 | 318 | static const RegMask &compiler_method_oop_reg_mask(); |
duke@435 | 319 | static int compiler_method_oop_reg_encode(); |
duke@435 | 320 | |
duke@435 | 321 | // Interpreter's Frame Pointer Register |
duke@435 | 322 | static OptoReg::Name interpreter_frame_pointer_reg(); |
duke@435 | 323 | static const RegMask &interpreter_frame_pointer_reg_mask(); |
duke@435 | 324 | |
duke@435 | 325 | // Java-Native calling convention |
duke@435 | 326 | // (what you use when intercalling between Java and C++ code) |
duke@435 | 327 | |
duke@435 | 328 | // Array mapping arguments to registers. Argument 0 is usually the 'this' |
duke@435 | 329 | // pointer. Registers can include stack-slots and regular registers. |
duke@435 | 330 | static void c_calling_convention( BasicType*, VMRegPair *, uint ); |
duke@435 | 331 | // Frame pointer. The frame pointer is kept at the base of the stack |
duke@435 | 332 | // and so is probably the stack pointer for most machines. On Intel |
duke@435 | 333 | // it is ESP. On the PowerPC it is R1. On Sparc it is SP. |
duke@435 | 334 | OptoReg::Name c_frame_pointer() const; |
duke@435 | 335 | static RegMask c_frame_ptr_mask; |
duke@435 | 336 | |
duke@435 | 337 | // !!!!! Special stuff for building ScopeDescs |
duke@435 | 338 | virtual int regnum_to_fpu_offset(int regnum); |
duke@435 | 339 | |
duke@435 | 340 | // Is this branch offset small enough to be addressed by a short branch? |
never@850 | 341 | bool is_short_branch_offset(int rule, int offset); |
duke@435 | 342 | |
duke@435 | 343 | // Optional scaling for the parameter to the ClearArray/CopyArray node. |
duke@435 | 344 | static const bool init_array_count_is_in_bytes; |
duke@435 | 345 | |
duke@435 | 346 | // Threshold small size (in bytes) for a ClearArray/CopyArray node. |
duke@435 | 347 | // Anything this size or smaller may get converted to discrete scalar stores. |
duke@435 | 348 | static const int init_array_short_size; |
duke@435 | 349 | |
duke@435 | 350 | // Should the Matcher clone shifts on addressing modes, expecting them to |
duke@435 | 351 | // be subsumed into complex addressing expressions or compute them into |
duke@435 | 352 | // registers? True for Intel but false for most RISCs |
duke@435 | 353 | static const bool clone_shift_expressions; |
duke@435 | 354 | |
duke@435 | 355 | // Is it better to copy float constants, or load them directly from memory? |
duke@435 | 356 | // Intel can load a float constant from a direct address, requiring no |
duke@435 | 357 | // extra registers. Most RISCs will have to materialize an address into a |
duke@435 | 358 | // register first, so they may as well materialize the constant immediately. |
duke@435 | 359 | static const bool rematerialize_float_constants; |
duke@435 | 360 | |
duke@435 | 361 | // If CPU can load and store mis-aligned doubles directly then no fixup is |
duke@435 | 362 | // needed. Else we split the double into 2 integer pieces and move it |
duke@435 | 363 | // piece-by-piece. Only happens when passing doubles into C code or when |
duke@435 | 364 | // calling i2c adapters as the Java calling convention forces doubles to be |
duke@435 | 365 | // aligned. |
duke@435 | 366 | static const bool misaligned_doubles_ok; |
duke@435 | 367 | |
duke@435 | 368 | // Perform a platform dependent implicit null fixup. This is needed |
duke@435 | 369 | // on windows95 to take care of some unusual register constraints. |
duke@435 | 370 | void pd_implicit_null_fixup(MachNode *load, uint idx); |
duke@435 | 371 | |
duke@435 | 372 | // Advertise here if the CPU requires explicit rounding operations |
duke@435 | 373 | // to implement the UseStrictFP mode. |
duke@435 | 374 | static const bool strict_fp_requires_explicit_rounding; |
duke@435 | 375 | |
kvn@1709 | 376 | // Are floats conerted to double when stored to stack during deoptimization? |
kvn@1709 | 377 | static bool float_in_double(); |
duke@435 | 378 | // Do ints take an entire long register or just half? |
duke@435 | 379 | static const bool int_in_long; |
duke@435 | 380 | |
duke@435 | 381 | // This routine is run whenever a graph fails to match. |
duke@435 | 382 | // If it returns, the compiler should bailout to interpreter without error. |
duke@435 | 383 | // In non-product mode, SoftMatchFailure is false to detect non-canonical |
duke@435 | 384 | // graphs. Print a message and exit. |
duke@435 | 385 | static void soft_match_failure() { |
duke@435 | 386 | if( SoftMatchFailure ) return; |
duke@435 | 387 | else { fatal("SoftMatchFailure is not allowed except in product"); } |
duke@435 | 388 | } |
duke@435 | 389 | |
duke@435 | 390 | // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock |
duke@435 | 391 | // acting as an Acquire and thus we don't need an Acquire here. We |
duke@435 | 392 | // retain the Node to act as a compiler ordering barrier. |
duke@435 | 393 | static bool prior_fast_lock( const Node *acq ); |
duke@435 | 394 | |
duke@435 | 395 | // Used by the DFA in dfa_sparc.cpp. Check for a following |
duke@435 | 396 | // FastUnLock acting as a Release and thus we don't need a Release |
duke@435 | 397 | // here. We retain the Node to act as a compiler ordering barrier. |
duke@435 | 398 | static bool post_fast_unlock( const Node *rel ); |
duke@435 | 399 | |
duke@435 | 400 | // Check for a following volatile memory barrier without an |
duke@435 | 401 | // intervening load and thus we don't need a barrier here. We |
duke@435 | 402 | // retain the Node to act as a compiler ordering barrier. |
duke@435 | 403 | static bool post_store_load_barrier(const Node* mb); |
duke@435 | 404 | |
duke@435 | 405 | |
duke@435 | 406 | #ifdef ASSERT |
duke@435 | 407 | void dump_old2new_map(); // machine-independent to machine-dependent |
never@657 | 408 | |
never@657 | 409 | Node* find_old_node(Node* new_node) { |
never@657 | 410 | return _new2old_map[new_node->_idx]; |
never@657 | 411 | } |
duke@435 | 412 | #endif |
duke@435 | 413 | }; |