Tue, 10 Mar 2009 08:52:16 -0700
Merge
duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 1997-2004 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | // Interface for updating the instruction cache. Whenever the VM modifies |
duke@435 | 26 | // code, part of the processor instruction cache potentially has to be flushed. |
duke@435 | 27 | |
duke@435 | 28 | // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent |
duke@435 | 29 | // after the next jump, and the VM never modifies instructions directly ahead |
duke@435 | 30 | // of the instruction fetch path. |
duke@435 | 31 | |
duke@435 | 32 | // [phh] It's not clear that the above comment is correct, because on an MP |
duke@435 | 33 | // system where the dcaches are not snooped, only the thread doing the invalidate |
duke@435 | 34 | // will see the update. Even in the snooped case, a memory fence would be |
duke@435 | 35 | // necessary if stores weren't ordered. Fortunately, they are on all known |
duke@435 | 36 | // x86 implementations. |
duke@435 | 37 | |
duke@435 | 38 | class ICache : public AbstractICache { |
duke@435 | 39 | public: |
duke@435 | 40 | #ifdef AMD64 |
duke@435 | 41 | enum { |
duke@435 | 42 | stub_size = 64, // Size of the icache flush stub in bytes |
duke@435 | 43 | line_size = 32, // Icache line size in bytes |
duke@435 | 44 | log2_line_size = 5 // log2(line_size) |
duke@435 | 45 | }; |
duke@435 | 46 | |
duke@435 | 47 | // Use default implementation |
duke@435 | 48 | #else |
duke@435 | 49 | enum { |
duke@435 | 50 | stub_size = 16, // Size of the icache flush stub in bytes |
duke@435 | 51 | line_size = BytesPerWord, // conservative |
duke@435 | 52 | log2_line_size = LogBytesPerWord // log2(line_size) |
duke@435 | 53 | }; |
duke@435 | 54 | #endif // AMD64 |
duke@435 | 55 | }; |