Tue, 10 Mar 2009 08:52:16 -0700
Merge
duke@435 | 1 | /* |
xdono@631 | 2 | * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_c1_LIRAssembler_x86.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | |
duke@435 | 29 | // These masks are used to provide 128-bit aligned bitmasks to the XMM |
duke@435 | 30 | // instructions, to allow sign-masking or sign-bit flipping. They allow |
duke@435 | 31 | // fast versions of NegF/NegD and AbsF/AbsD. |
duke@435 | 32 | |
duke@435 | 33 | // Note: 'double' and 'long long' have 32-bits alignment on x86. |
duke@435 | 34 | static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { |
duke@435 | 35 | // Use the expression (adr)&(~0xF) to provide 128-bits aligned address |
duke@435 | 36 | // of 128-bits operands for SSE instructions. |
duke@435 | 37 | jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); |
duke@435 | 38 | // Store the value to a 128-bits operand. |
duke@435 | 39 | operand[0] = lo; |
duke@435 | 40 | operand[1] = hi; |
duke@435 | 41 | return operand; |
duke@435 | 42 | } |
duke@435 | 43 | |
duke@435 | 44 | // Buffer for 128-bits masks used by SSE instructions. |
duke@435 | 45 | static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) |
duke@435 | 46 | |
duke@435 | 47 | // Static initialization during VM startup. |
duke@435 | 48 | static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); |
duke@435 | 49 | static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); |
duke@435 | 50 | static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); |
duke@435 | 51 | static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); |
duke@435 | 52 | |
duke@435 | 53 | |
duke@435 | 54 | |
duke@435 | 55 | NEEDS_CLEANUP // remove this definitions ? |
duke@435 | 56 | const Register IC_Klass = rax; // where the IC klass is cached |
duke@435 | 57 | const Register SYNC_header = rax; // synchronization header |
duke@435 | 58 | const Register SHIFT_count = rcx; // where count for shift operations must be |
duke@435 | 59 | |
duke@435 | 60 | #define __ _masm-> |
duke@435 | 61 | |
duke@435 | 62 | |
duke@435 | 63 | static void select_different_registers(Register preserve, |
duke@435 | 64 | Register extra, |
duke@435 | 65 | Register &tmp1, |
duke@435 | 66 | Register &tmp2) { |
duke@435 | 67 | if (tmp1 == preserve) { |
duke@435 | 68 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 69 | tmp1 = extra; |
duke@435 | 70 | } else if (tmp2 == preserve) { |
duke@435 | 71 | assert_different_registers(tmp1, tmp2, extra); |
duke@435 | 72 | tmp2 = extra; |
duke@435 | 73 | } |
duke@435 | 74 | assert_different_registers(preserve, tmp1, tmp2); |
duke@435 | 75 | } |
duke@435 | 76 | |
duke@435 | 77 | |
duke@435 | 78 | |
duke@435 | 79 | static void select_different_registers(Register preserve, |
duke@435 | 80 | Register extra, |
duke@435 | 81 | Register &tmp1, |
duke@435 | 82 | Register &tmp2, |
duke@435 | 83 | Register &tmp3) { |
duke@435 | 84 | if (tmp1 == preserve) { |
duke@435 | 85 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 86 | tmp1 = extra; |
duke@435 | 87 | } else if (tmp2 == preserve) { |
duke@435 | 88 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 89 | tmp2 = extra; |
duke@435 | 90 | } else if (tmp3 == preserve) { |
duke@435 | 91 | assert_different_registers(tmp1, tmp2, tmp3, extra); |
duke@435 | 92 | tmp3 = extra; |
duke@435 | 93 | } |
duke@435 | 94 | assert_different_registers(preserve, tmp1, tmp2, tmp3); |
duke@435 | 95 | } |
duke@435 | 96 | |
duke@435 | 97 | |
duke@435 | 98 | |
duke@435 | 99 | bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
duke@435 | 100 | if (opr->is_constant()) { |
duke@435 | 101 | LIR_Const* constant = opr->as_constant_ptr(); |
duke@435 | 102 | switch (constant->type()) { |
duke@435 | 103 | case T_INT: { |
duke@435 | 104 | return true; |
duke@435 | 105 | } |
duke@435 | 106 | |
duke@435 | 107 | default: |
duke@435 | 108 | return false; |
duke@435 | 109 | } |
duke@435 | 110 | } |
duke@435 | 111 | return false; |
duke@435 | 112 | } |
duke@435 | 113 | |
duke@435 | 114 | |
duke@435 | 115 | LIR_Opr LIR_Assembler::receiverOpr() { |
never@739 | 116 | return FrameMap::receiver_opr; |
duke@435 | 117 | } |
duke@435 | 118 | |
duke@435 | 119 | LIR_Opr LIR_Assembler::incomingReceiverOpr() { |
duke@435 | 120 | return receiverOpr(); |
duke@435 | 121 | } |
duke@435 | 122 | |
duke@435 | 123 | LIR_Opr LIR_Assembler::osrBufferPointer() { |
never@739 | 124 | return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
duke@435 | 125 | } |
duke@435 | 126 | |
duke@435 | 127 | //--------------fpu register translations----------------------- |
duke@435 | 128 | |
duke@435 | 129 | |
duke@435 | 130 | address LIR_Assembler::float_constant(float f) { |
duke@435 | 131 | address const_addr = __ float_constant(f); |
duke@435 | 132 | if (const_addr == NULL) { |
duke@435 | 133 | bailout("const section overflow"); |
duke@435 | 134 | return __ code()->consts()->start(); |
duke@435 | 135 | } else { |
duke@435 | 136 | return const_addr; |
duke@435 | 137 | } |
duke@435 | 138 | } |
duke@435 | 139 | |
duke@435 | 140 | |
duke@435 | 141 | address LIR_Assembler::double_constant(double d) { |
duke@435 | 142 | address const_addr = __ double_constant(d); |
duke@435 | 143 | if (const_addr == NULL) { |
duke@435 | 144 | bailout("const section overflow"); |
duke@435 | 145 | return __ code()->consts()->start(); |
duke@435 | 146 | } else { |
duke@435 | 147 | return const_addr; |
duke@435 | 148 | } |
duke@435 | 149 | } |
duke@435 | 150 | |
duke@435 | 151 | |
duke@435 | 152 | void LIR_Assembler::set_24bit_FPU() { |
duke@435 | 153 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
duke@435 | 154 | } |
duke@435 | 155 | |
duke@435 | 156 | void LIR_Assembler::reset_FPU() { |
duke@435 | 157 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 158 | } |
duke@435 | 159 | |
duke@435 | 160 | void LIR_Assembler::fpop() { |
duke@435 | 161 | __ fpop(); |
duke@435 | 162 | } |
duke@435 | 163 | |
duke@435 | 164 | void LIR_Assembler::fxch(int i) { |
duke@435 | 165 | __ fxch(i); |
duke@435 | 166 | } |
duke@435 | 167 | |
duke@435 | 168 | void LIR_Assembler::fld(int i) { |
duke@435 | 169 | __ fld_s(i); |
duke@435 | 170 | } |
duke@435 | 171 | |
duke@435 | 172 | void LIR_Assembler::ffree(int i) { |
duke@435 | 173 | __ ffree(i); |
duke@435 | 174 | } |
duke@435 | 175 | |
duke@435 | 176 | void LIR_Assembler::breakpoint() { |
duke@435 | 177 | __ int3(); |
duke@435 | 178 | } |
duke@435 | 179 | |
duke@435 | 180 | void LIR_Assembler::push(LIR_Opr opr) { |
duke@435 | 181 | if (opr->is_single_cpu()) { |
duke@435 | 182 | __ push_reg(opr->as_register()); |
duke@435 | 183 | } else if (opr->is_double_cpu()) { |
never@739 | 184 | NOT_LP64(__ push_reg(opr->as_register_hi())); |
duke@435 | 185 | __ push_reg(opr->as_register_lo()); |
duke@435 | 186 | } else if (opr->is_stack()) { |
duke@435 | 187 | __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); |
duke@435 | 188 | } else if (opr->is_constant()) { |
duke@435 | 189 | LIR_Const* const_opr = opr->as_constant_ptr(); |
duke@435 | 190 | if (const_opr->type() == T_OBJECT) { |
duke@435 | 191 | __ push_oop(const_opr->as_jobject()); |
duke@435 | 192 | } else if (const_opr->type() == T_INT) { |
duke@435 | 193 | __ push_jint(const_opr->as_jint()); |
duke@435 | 194 | } else { |
duke@435 | 195 | ShouldNotReachHere(); |
duke@435 | 196 | } |
duke@435 | 197 | |
duke@435 | 198 | } else { |
duke@435 | 199 | ShouldNotReachHere(); |
duke@435 | 200 | } |
duke@435 | 201 | } |
duke@435 | 202 | |
duke@435 | 203 | void LIR_Assembler::pop(LIR_Opr opr) { |
duke@435 | 204 | if (opr->is_single_cpu()) { |
never@739 | 205 | __ pop_reg(opr->as_register()); |
duke@435 | 206 | } else { |
duke@435 | 207 | ShouldNotReachHere(); |
duke@435 | 208 | } |
duke@435 | 209 | } |
duke@435 | 210 | |
never@739 | 211 | bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
never@739 | 212 | return addr->base()->is_illegal() && addr->index()->is_illegal(); |
never@739 | 213 | } |
never@739 | 214 | |
duke@435 | 215 | //------------------------------------------- |
never@739 | 216 | |
duke@435 | 217 | Address LIR_Assembler::as_Address(LIR_Address* addr) { |
never@739 | 218 | return as_Address(addr, rscratch1); |
never@739 | 219 | } |
never@739 | 220 | |
never@739 | 221 | Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { |
duke@435 | 222 | if (addr->base()->is_illegal()) { |
duke@435 | 223 | assert(addr->index()->is_illegal(), "must be illegal too"); |
never@739 | 224 | AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
never@739 | 225 | if (! __ reachable(laddr)) { |
never@739 | 226 | __ movptr(tmp, laddr.addr()); |
never@739 | 227 | Address res(tmp, 0); |
never@739 | 228 | return res; |
never@739 | 229 | } else { |
never@739 | 230 | return __ as_Address(laddr); |
never@739 | 231 | } |
duke@435 | 232 | } |
duke@435 | 233 | |
never@739 | 234 | Register base = addr->base()->as_pointer_register(); |
duke@435 | 235 | |
duke@435 | 236 | if (addr->index()->is_illegal()) { |
duke@435 | 237 | return Address( base, addr->disp()); |
never@739 | 238 | } else if (addr->index()->is_cpu_register()) { |
never@739 | 239 | Register index = addr->index()->as_pointer_register(); |
duke@435 | 240 | return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
duke@435 | 241 | } else if (addr->index()->is_constant()) { |
never@739 | 242 | intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
never@739 | 243 | assert(Assembler::is_simm32(addr_offset), "must be"); |
duke@435 | 244 | |
duke@435 | 245 | return Address(base, addr_offset); |
duke@435 | 246 | } else { |
duke@435 | 247 | Unimplemented(); |
duke@435 | 248 | return Address(); |
duke@435 | 249 | } |
duke@435 | 250 | } |
duke@435 | 251 | |
duke@435 | 252 | |
duke@435 | 253 | Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
duke@435 | 254 | Address base = as_Address(addr); |
duke@435 | 255 | return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); |
duke@435 | 256 | } |
duke@435 | 257 | |
duke@435 | 258 | |
duke@435 | 259 | Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
duke@435 | 260 | return as_Address(addr); |
duke@435 | 261 | } |
duke@435 | 262 | |
duke@435 | 263 | |
duke@435 | 264 | void LIR_Assembler::osr_entry() { |
duke@435 | 265 | offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
duke@435 | 266 | BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
duke@435 | 267 | ValueStack* entry_state = osr_entry->state(); |
duke@435 | 268 | int number_of_locks = entry_state->locks_size(); |
duke@435 | 269 | |
duke@435 | 270 | // we jump here if osr happens with the interpreter |
duke@435 | 271 | // state set up to continue at the beginning of the |
duke@435 | 272 | // loop that triggered osr - in particular, we have |
duke@435 | 273 | // the following registers setup: |
duke@435 | 274 | // |
duke@435 | 275 | // rcx: osr buffer |
duke@435 | 276 | // |
duke@435 | 277 | |
duke@435 | 278 | // build frame |
duke@435 | 279 | ciMethod* m = compilation()->method(); |
duke@435 | 280 | __ build_frame(initial_frame_size_in_bytes()); |
duke@435 | 281 | |
duke@435 | 282 | // OSR buffer is |
duke@435 | 283 | // |
duke@435 | 284 | // locals[nlocals-1..0] |
duke@435 | 285 | // monitors[0..number_of_locks] |
duke@435 | 286 | // |
duke@435 | 287 | // locals is a direct copy of the interpreter frame so in the osr buffer |
duke@435 | 288 | // so first slot in the local array is the last local from the interpreter |
duke@435 | 289 | // and last slot is local[0] (receiver) from the interpreter |
duke@435 | 290 | // |
duke@435 | 291 | // Similarly with locks. The first lock slot in the osr buffer is the nth lock |
duke@435 | 292 | // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
duke@435 | 293 | // in the interpreter frame (the method lock if a sync method) |
duke@435 | 294 | |
duke@435 | 295 | // Initialize monitors in the compiled activation. |
duke@435 | 296 | // rcx: pointer to osr buffer |
duke@435 | 297 | // |
duke@435 | 298 | // All other registers are dead at this point and the locals will be |
duke@435 | 299 | // copied into place by code emitted in the IR. |
duke@435 | 300 | |
never@739 | 301 | Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
duke@435 | 302 | { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
duke@435 | 303 | int monitor_offset = BytesPerWord * method()->max_locals() + |
duke@435 | 304 | (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); |
duke@435 | 305 | for (int i = 0; i < number_of_locks; i++) { |
duke@435 | 306 | int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); |
duke@435 | 307 | #ifdef ASSERT |
duke@435 | 308 | // verify the interpreter's monitor has a non-null object |
duke@435 | 309 | { |
duke@435 | 310 | Label L; |
never@739 | 311 | __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD); |
duke@435 | 312 | __ jcc(Assembler::notZero, L); |
duke@435 | 313 | __ stop("locked object is NULL"); |
duke@435 | 314 | __ bind(L); |
duke@435 | 315 | } |
duke@435 | 316 | #endif |
never@739 | 317 | __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes())); |
never@739 | 318 | __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
never@739 | 319 | __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes())); |
never@739 | 320 | __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
duke@435 | 321 | } |
duke@435 | 322 | } |
duke@435 | 323 | } |
duke@435 | 324 | |
duke@435 | 325 | |
duke@435 | 326 | // inline cache check; done before the frame is built. |
duke@435 | 327 | int LIR_Assembler::check_icache() { |
duke@435 | 328 | Register receiver = FrameMap::receiver_opr->as_register(); |
duke@435 | 329 | Register ic_klass = IC_Klass; |
never@739 | 330 | const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
duke@435 | 331 | |
duke@435 | 332 | if (!VerifyOops) { |
duke@435 | 333 | // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
never@739 | 334 | while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
duke@435 | 335 | __ nop(); |
duke@435 | 336 | } |
duke@435 | 337 | } |
duke@435 | 338 | int offset = __ offset(); |
duke@435 | 339 | __ inline_cache_check(receiver, IC_Klass); |
duke@435 | 340 | assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); |
duke@435 | 341 | if (VerifyOops) { |
duke@435 | 342 | // force alignment after the cache check. |
duke@435 | 343 | // It's been verified to be aligned if !VerifyOops |
duke@435 | 344 | __ align(CodeEntryAlignment); |
duke@435 | 345 | } |
duke@435 | 346 | return offset; |
duke@435 | 347 | } |
duke@435 | 348 | |
duke@435 | 349 | |
duke@435 | 350 | void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { |
duke@435 | 351 | jobject o = NULL; |
duke@435 | 352 | PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
duke@435 | 353 | __ movoop(reg, o); |
duke@435 | 354 | patching_epilog(patch, lir_patch_normal, reg, info); |
duke@435 | 355 | } |
duke@435 | 356 | |
duke@435 | 357 | |
duke@435 | 358 | void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { |
duke@435 | 359 | if (exception->is_valid()) { |
duke@435 | 360 | // preserve exception |
duke@435 | 361 | // note: the monitor_exit runtime call is a leaf routine |
duke@435 | 362 | // and cannot block => no GC can happen |
duke@435 | 363 | // The slow case (MonitorAccessStub) uses the first two stack slots |
duke@435 | 364 | // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] |
never@739 | 365 | __ movptr (Address(rsp, 2*wordSize), exception); |
duke@435 | 366 | } |
duke@435 | 367 | |
duke@435 | 368 | Register obj_reg = obj_opr->as_register(); |
duke@435 | 369 | Register lock_reg = lock_opr->as_register(); |
duke@435 | 370 | |
duke@435 | 371 | // setup registers (lock_reg must be rax, for lock_object) |
duke@435 | 372 | assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); |
duke@435 | 373 | Register hdr = lock_reg; |
duke@435 | 374 | assert(new_hdr == SYNC_header, "wrong register"); |
duke@435 | 375 | lock_reg = new_hdr; |
duke@435 | 376 | // compute pointer to BasicLock |
duke@435 | 377 | Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); |
never@739 | 378 | __ lea(lock_reg, lock_addr); |
duke@435 | 379 | // unlock object |
duke@435 | 380 | MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); |
duke@435 | 381 | // _slow_case_stubs->append(slow_case); |
duke@435 | 382 | // temporary fix: must be created after exceptionhandler, therefore as call stub |
duke@435 | 383 | _slow_case_stubs->append(slow_case); |
duke@435 | 384 | if (UseFastLocking) { |
duke@435 | 385 | // try inlined fast unlocking first, revert to slow locking if it fails |
duke@435 | 386 | // note: lock_reg points to the displaced header since the displaced header offset is 0! |
duke@435 | 387 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 388 | __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); |
duke@435 | 389 | } else { |
duke@435 | 390 | // always do slow unlocking |
duke@435 | 391 | // note: the slow unlocking code could be inlined here, however if we use |
duke@435 | 392 | // slow unlocking, speed doesn't matter anyway and this solution is |
duke@435 | 393 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 394 | // slow unlocking code is the same in either case which simplifies |
duke@435 | 395 | // debugging |
duke@435 | 396 | __ jmp(*slow_case->entry()); |
duke@435 | 397 | } |
duke@435 | 398 | // done |
duke@435 | 399 | __ bind(*slow_case->continuation()); |
duke@435 | 400 | |
duke@435 | 401 | if (exception->is_valid()) { |
duke@435 | 402 | // restore exception |
never@739 | 403 | __ movptr (exception, Address(rsp, 2 * wordSize)); |
duke@435 | 404 | } |
duke@435 | 405 | } |
duke@435 | 406 | |
duke@435 | 407 | // This specifies the rsp decrement needed to build the frame |
duke@435 | 408 | int LIR_Assembler::initial_frame_size_in_bytes() { |
duke@435 | 409 | // if rounding, must let FrameMap know! |
never@739 | 410 | |
never@739 | 411 | // The frame_map records size in slots (32bit word) |
never@739 | 412 | |
never@739 | 413 | // subtract two words to account for return address and link |
never@739 | 414 | return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; |
duke@435 | 415 | } |
duke@435 | 416 | |
duke@435 | 417 | |
duke@435 | 418 | void LIR_Assembler::emit_exception_handler() { |
duke@435 | 419 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 420 | // is coming at the end after block reordering) the return address |
duke@435 | 421 | // must still point into the code area in order to avoid assertion |
duke@435 | 422 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 423 | // (was bug 5/14/1999 - gri) |
duke@435 | 424 | |
duke@435 | 425 | __ nop(); |
duke@435 | 426 | |
duke@435 | 427 | // generate code for exception handler |
duke@435 | 428 | address handler_base = __ start_a_stub(exception_handler_size); |
duke@435 | 429 | if (handler_base == NULL) { |
duke@435 | 430 | // not enough space left for the handler |
duke@435 | 431 | bailout("exception handler overflow"); |
duke@435 | 432 | return; |
duke@435 | 433 | } |
duke@435 | 434 | #ifdef ASSERT |
duke@435 | 435 | int offset = code_offset(); |
duke@435 | 436 | #endif // ASSERT |
duke@435 | 437 | |
duke@435 | 438 | compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); |
duke@435 | 439 | |
duke@435 | 440 | // if the method does not have an exception handler, then there is |
duke@435 | 441 | // no reason to search for one |
duke@435 | 442 | if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { |
duke@435 | 443 | // the exception oop and pc are in rax, and rdx |
duke@435 | 444 | // no other registers need to be preserved, so invalidate them |
duke@435 | 445 | __ invalidate_registers(false, true, true, false, true, true); |
duke@435 | 446 | |
duke@435 | 447 | // check that there is really an exception |
duke@435 | 448 | __ verify_not_null_oop(rax); |
duke@435 | 449 | |
duke@435 | 450 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
duke@435 | 451 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); |
duke@435 | 452 | |
duke@435 | 453 | // if the call returns here, then the exception handler for particular |
duke@435 | 454 | // exception doesn't exist -> unwind activation and forward exception to caller |
duke@435 | 455 | } |
duke@435 | 456 | |
duke@435 | 457 | // the exception oop is in rax, |
duke@435 | 458 | // no other registers need to be preserved, so invalidate them |
duke@435 | 459 | __ invalidate_registers(false, true, true, true, true, true); |
duke@435 | 460 | |
duke@435 | 461 | // check that there is really an exception |
duke@435 | 462 | __ verify_not_null_oop(rax); |
duke@435 | 463 | |
duke@435 | 464 | // unlock the receiver/klass if necessary |
duke@435 | 465 | // rax,: exception |
duke@435 | 466 | ciMethod* method = compilation()->method(); |
duke@435 | 467 | if (method->is_synchronized() && GenerateSynchronizationCode) { |
duke@435 | 468 | monitorexit(FrameMap::rbx_oop_opr, FrameMap::rcx_opr, SYNC_header, 0, rax); |
duke@435 | 469 | } |
duke@435 | 470 | |
duke@435 | 471 | // unwind activation and forward exception to caller |
duke@435 | 472 | // rax,: exception |
duke@435 | 473 | __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
duke@435 | 474 | |
duke@435 | 475 | assert(code_offset() - offset <= exception_handler_size, "overflow"); |
duke@435 | 476 | |
duke@435 | 477 | __ end_a_stub(); |
duke@435 | 478 | } |
duke@435 | 479 | |
duke@435 | 480 | void LIR_Assembler::emit_deopt_handler() { |
duke@435 | 481 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 482 | // is coming at the end after block reordering) the return address |
duke@435 | 483 | // must still point into the code area in order to avoid assertion |
duke@435 | 484 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 485 | // (was bug 5/14/1999 - gri) |
duke@435 | 486 | |
duke@435 | 487 | __ nop(); |
duke@435 | 488 | |
duke@435 | 489 | // generate code for exception handler |
duke@435 | 490 | address handler_base = __ start_a_stub(deopt_handler_size); |
duke@435 | 491 | if (handler_base == NULL) { |
duke@435 | 492 | // not enough space left for the handler |
duke@435 | 493 | bailout("deopt handler overflow"); |
duke@435 | 494 | return; |
duke@435 | 495 | } |
duke@435 | 496 | #ifdef ASSERT |
duke@435 | 497 | int offset = code_offset(); |
duke@435 | 498 | #endif // ASSERT |
duke@435 | 499 | |
duke@435 | 500 | compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); |
duke@435 | 501 | |
duke@435 | 502 | InternalAddress here(__ pc()); |
duke@435 | 503 | __ pushptr(here.addr()); |
duke@435 | 504 | |
duke@435 | 505 | __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
duke@435 | 506 | |
duke@435 | 507 | assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
duke@435 | 508 | |
duke@435 | 509 | __ end_a_stub(); |
duke@435 | 510 | |
duke@435 | 511 | } |
duke@435 | 512 | |
duke@435 | 513 | |
duke@435 | 514 | // This is the fast version of java.lang.String.compare; it has not |
duke@435 | 515 | // OSR-entry and therefore, we generate a slow version for OSR's |
duke@435 | 516 | void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { |
never@739 | 517 | __ movptr (rbx, rcx); // receiver is in rcx |
never@739 | 518 | __ movptr (rax, arg1->as_register()); |
duke@435 | 519 | |
duke@435 | 520 | // Get addresses of first characters from both Strings |
never@739 | 521 | __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
never@739 | 522 | __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); |
never@739 | 523 | __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 524 | |
duke@435 | 525 | |
duke@435 | 526 | // rbx, may be NULL |
duke@435 | 527 | add_debug_info_for_null_check_here(info); |
never@739 | 528 | __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
never@739 | 529 | __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); |
never@739 | 530 | __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); |
duke@435 | 531 | |
duke@435 | 532 | // compute minimum length (in rax) and difference of lengths (on top of stack) |
duke@435 | 533 | if (VM_Version::supports_cmov()) { |
never@739 | 534 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 535 | __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 536 | __ mov (rcx, rbx); |
never@739 | 537 | __ subptr (rbx, rax); // subtract lengths |
never@739 | 538 | __ push (rbx); // result |
never@739 | 539 | __ cmov (Assembler::lessEqual, rax, rcx); |
duke@435 | 540 | } else { |
duke@435 | 541 | Label L; |
never@739 | 542 | __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
never@739 | 543 | __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); |
never@739 | 544 | __ mov (rax, rbx); |
never@739 | 545 | __ subptr (rbx, rcx); |
never@739 | 546 | __ push (rbx); |
never@739 | 547 | __ jcc (Assembler::lessEqual, L); |
never@739 | 548 | __ mov (rax, rcx); |
duke@435 | 549 | __ bind (L); |
duke@435 | 550 | } |
duke@435 | 551 | // is minimum length 0? |
duke@435 | 552 | Label noLoop, haveResult; |
never@739 | 553 | __ testptr (rax, rax); |
duke@435 | 554 | __ jcc (Assembler::zero, noLoop); |
duke@435 | 555 | |
duke@435 | 556 | // compare first characters |
jrose@1057 | 557 | __ load_unsigned_short(rcx, Address(rdi, 0)); |
jrose@1057 | 558 | __ load_unsigned_short(rbx, Address(rsi, 0)); |
duke@435 | 559 | __ subl(rcx, rbx); |
duke@435 | 560 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 561 | // starting loop |
duke@435 | 562 | __ decrement(rax); // we already tested index: skip one |
duke@435 | 563 | __ jcc(Assembler::zero, noLoop); |
duke@435 | 564 | |
duke@435 | 565 | // set rsi.edi to the end of the arrays (arrays have same length) |
duke@435 | 566 | // negate the index |
duke@435 | 567 | |
never@739 | 568 | __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 569 | __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
never@739 | 570 | __ negptr(rax); |
duke@435 | 571 | |
duke@435 | 572 | // compare the strings in a loop |
duke@435 | 573 | |
duke@435 | 574 | Label loop; |
duke@435 | 575 | __ align(wordSize); |
duke@435 | 576 | __ bind(loop); |
jrose@1057 | 577 | __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
jrose@1057 | 578 | __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
duke@435 | 579 | __ subl(rcx, rbx); |
duke@435 | 580 | __ jcc(Assembler::notZero, haveResult); |
duke@435 | 581 | __ increment(rax); |
duke@435 | 582 | __ jcc(Assembler::notZero, loop); |
duke@435 | 583 | |
duke@435 | 584 | // strings are equal up to min length |
duke@435 | 585 | |
duke@435 | 586 | __ bind(noLoop); |
never@739 | 587 | __ pop(rax); |
duke@435 | 588 | return_op(LIR_OprFact::illegalOpr); |
duke@435 | 589 | |
duke@435 | 590 | __ bind(haveResult); |
duke@435 | 591 | // leave instruction is going to discard the TOS value |
never@739 | 592 | __ mov (rax, rcx); // result of call is in rax, |
duke@435 | 593 | } |
duke@435 | 594 | |
duke@435 | 595 | |
duke@435 | 596 | void LIR_Assembler::return_op(LIR_Opr result) { |
duke@435 | 597 | assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); |
duke@435 | 598 | if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { |
duke@435 | 599 | assert(result->fpu() == 0, "result must already be on TOS"); |
duke@435 | 600 | } |
duke@435 | 601 | |
duke@435 | 602 | // Pop the stack before the safepoint code |
duke@435 | 603 | __ leave(); |
duke@435 | 604 | |
duke@435 | 605 | bool result_is_oop = result->is_valid() ? result->is_oop() : false; |
duke@435 | 606 | |
duke@435 | 607 | // Note: we do not need to round double result; float result has the right precision |
duke@435 | 608 | // the poll sets the condition code, but no data registers |
duke@435 | 609 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 610 | relocInfo::poll_return_type); |
never@739 | 611 | |
never@739 | 612 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 613 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 614 | // which breaks the signal handler code |
never@739 | 615 | |
duke@435 | 616 | __ test32(rax, polling_page); |
duke@435 | 617 | |
duke@435 | 618 | __ ret(0); |
duke@435 | 619 | } |
duke@435 | 620 | |
duke@435 | 621 | |
duke@435 | 622 | int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 623 | AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), |
duke@435 | 624 | relocInfo::poll_type); |
duke@435 | 625 | |
duke@435 | 626 | if (info != NULL) { |
duke@435 | 627 | add_debug_info_for_branch(info); |
duke@435 | 628 | } else { |
duke@435 | 629 | ShouldNotReachHere(); |
duke@435 | 630 | } |
duke@435 | 631 | |
duke@435 | 632 | int offset = __ offset(); |
never@739 | 633 | |
never@739 | 634 | // NOTE: the requires that the polling page be reachable else the reloc |
never@739 | 635 | // goes to the movq that loads the address and not the faulting instruction |
never@739 | 636 | // which breaks the signal handler code |
never@739 | 637 | |
duke@435 | 638 | __ test32(rax, polling_page); |
duke@435 | 639 | return offset; |
duke@435 | 640 | } |
duke@435 | 641 | |
duke@435 | 642 | |
duke@435 | 643 | void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { |
never@739 | 644 | if (from_reg != to_reg) __ mov(to_reg, from_reg); |
duke@435 | 645 | } |
duke@435 | 646 | |
duke@435 | 647 | void LIR_Assembler::swap_reg(Register a, Register b) { |
never@739 | 648 | __ xchgptr(a, b); |
duke@435 | 649 | } |
duke@435 | 650 | |
duke@435 | 651 | |
duke@435 | 652 | void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
duke@435 | 653 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 654 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 655 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 656 | |
duke@435 | 657 | switch (c->type()) { |
duke@435 | 658 | case T_INT: { |
duke@435 | 659 | assert(patch_code == lir_patch_none, "no patching handled here"); |
duke@435 | 660 | __ movl(dest->as_register(), c->as_jint()); |
duke@435 | 661 | break; |
duke@435 | 662 | } |
duke@435 | 663 | |
duke@435 | 664 | case T_LONG: { |
duke@435 | 665 | assert(patch_code == lir_patch_none, "no patching handled here"); |
never@739 | 666 | #ifdef _LP64 |
never@739 | 667 | __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); |
never@739 | 668 | #else |
never@739 | 669 | __ movptr(dest->as_register_lo(), c->as_jint_lo()); |
never@739 | 670 | __ movptr(dest->as_register_hi(), c->as_jint_hi()); |
never@739 | 671 | #endif // _LP64 |
duke@435 | 672 | break; |
duke@435 | 673 | } |
duke@435 | 674 | |
duke@435 | 675 | case T_OBJECT: { |
duke@435 | 676 | if (patch_code != lir_patch_none) { |
duke@435 | 677 | jobject2reg_with_patching(dest->as_register(), info); |
duke@435 | 678 | } else { |
duke@435 | 679 | __ movoop(dest->as_register(), c->as_jobject()); |
duke@435 | 680 | } |
duke@435 | 681 | break; |
duke@435 | 682 | } |
duke@435 | 683 | |
duke@435 | 684 | case T_FLOAT: { |
duke@435 | 685 | if (dest->is_single_xmm()) { |
duke@435 | 686 | if (c->is_zero_float()) { |
duke@435 | 687 | __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); |
duke@435 | 688 | } else { |
duke@435 | 689 | __ movflt(dest->as_xmm_float_reg(), |
duke@435 | 690 | InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 691 | } |
duke@435 | 692 | } else { |
duke@435 | 693 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 694 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 695 | if (c->is_zero_float()) { |
duke@435 | 696 | __ fldz(); |
duke@435 | 697 | } else if (c->is_one_float()) { |
duke@435 | 698 | __ fld1(); |
duke@435 | 699 | } else { |
duke@435 | 700 | __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); |
duke@435 | 701 | } |
duke@435 | 702 | } |
duke@435 | 703 | break; |
duke@435 | 704 | } |
duke@435 | 705 | |
duke@435 | 706 | case T_DOUBLE: { |
duke@435 | 707 | if (dest->is_double_xmm()) { |
duke@435 | 708 | if (c->is_zero_double()) { |
duke@435 | 709 | __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); |
duke@435 | 710 | } else { |
duke@435 | 711 | __ movdbl(dest->as_xmm_double_reg(), |
duke@435 | 712 | InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 713 | } |
duke@435 | 714 | } else { |
duke@435 | 715 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 716 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 717 | if (c->is_zero_double()) { |
duke@435 | 718 | __ fldz(); |
duke@435 | 719 | } else if (c->is_one_double()) { |
duke@435 | 720 | __ fld1(); |
duke@435 | 721 | } else { |
duke@435 | 722 | __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); |
duke@435 | 723 | } |
duke@435 | 724 | } |
duke@435 | 725 | break; |
duke@435 | 726 | } |
duke@435 | 727 | |
duke@435 | 728 | default: |
duke@435 | 729 | ShouldNotReachHere(); |
duke@435 | 730 | } |
duke@435 | 731 | } |
duke@435 | 732 | |
duke@435 | 733 | void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 734 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 735 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 736 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 737 | |
duke@435 | 738 | switch (c->type()) { |
duke@435 | 739 | case T_INT: // fall through |
duke@435 | 740 | case T_FLOAT: |
duke@435 | 741 | __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
duke@435 | 742 | break; |
duke@435 | 743 | |
duke@435 | 744 | case T_OBJECT: |
duke@435 | 745 | __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); |
duke@435 | 746 | break; |
duke@435 | 747 | |
duke@435 | 748 | case T_LONG: // fall through |
duke@435 | 749 | case T_DOUBLE: |
never@739 | 750 | #ifdef _LP64 |
never@739 | 751 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 752 | lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); |
never@739 | 753 | #else |
never@739 | 754 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 755 | lo_word_offset_in_bytes), c->as_jint_lo_bits()); |
never@739 | 756 | __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), |
never@739 | 757 | hi_word_offset_in_bytes), c->as_jint_hi_bits()); |
never@739 | 758 | #endif // _LP64 |
duke@435 | 759 | break; |
duke@435 | 760 | |
duke@435 | 761 | default: |
duke@435 | 762 | ShouldNotReachHere(); |
duke@435 | 763 | } |
duke@435 | 764 | } |
duke@435 | 765 | |
duke@435 | 766 | void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { |
duke@435 | 767 | assert(src->is_constant(), "should not call otherwise"); |
duke@435 | 768 | assert(dest->is_address(), "should not call otherwise"); |
duke@435 | 769 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 770 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 771 | |
never@739 | 772 | int null_check_here = code_offset(); |
duke@435 | 773 | switch (type) { |
duke@435 | 774 | case T_INT: // fall through |
duke@435 | 775 | case T_FLOAT: |
duke@435 | 776 | __ movl(as_Address(addr), c->as_jint_bits()); |
duke@435 | 777 | break; |
duke@435 | 778 | |
duke@435 | 779 | case T_OBJECT: // fall through |
duke@435 | 780 | case T_ARRAY: |
duke@435 | 781 | if (c->as_jobject() == NULL) { |
xlu@947 | 782 | __ movptr(as_Address(addr), NULL_WORD); |
duke@435 | 783 | } else { |
never@739 | 784 | if (is_literal_address(addr)) { |
never@739 | 785 | ShouldNotReachHere(); |
never@739 | 786 | __ movoop(as_Address(addr, noreg), c->as_jobject()); |
never@739 | 787 | } else { |
never@739 | 788 | __ movoop(as_Address(addr), c->as_jobject()); |
never@739 | 789 | } |
duke@435 | 790 | } |
duke@435 | 791 | break; |
duke@435 | 792 | |
duke@435 | 793 | case T_LONG: // fall through |
duke@435 | 794 | case T_DOUBLE: |
never@739 | 795 | #ifdef _LP64 |
never@739 | 796 | if (is_literal_address(addr)) { |
never@739 | 797 | ShouldNotReachHere(); |
never@739 | 798 | __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); |
never@739 | 799 | } else { |
never@739 | 800 | __ movptr(r10, (intptr_t)c->as_jlong_bits()); |
never@739 | 801 | null_check_here = code_offset(); |
never@739 | 802 | __ movptr(as_Address_lo(addr), r10); |
never@739 | 803 | } |
never@739 | 804 | #else |
never@739 | 805 | // Always reachable in 32bit so this doesn't produce useless move literal |
never@739 | 806 | __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); |
never@739 | 807 | __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); |
never@739 | 808 | #endif // _LP64 |
duke@435 | 809 | break; |
duke@435 | 810 | |
duke@435 | 811 | case T_BOOLEAN: // fall through |
duke@435 | 812 | case T_BYTE: |
duke@435 | 813 | __ movb(as_Address(addr), c->as_jint() & 0xFF); |
duke@435 | 814 | break; |
duke@435 | 815 | |
duke@435 | 816 | case T_CHAR: // fall through |
duke@435 | 817 | case T_SHORT: |
duke@435 | 818 | __ movw(as_Address(addr), c->as_jint() & 0xFFFF); |
duke@435 | 819 | break; |
duke@435 | 820 | |
duke@435 | 821 | default: |
duke@435 | 822 | ShouldNotReachHere(); |
duke@435 | 823 | }; |
never@739 | 824 | |
never@739 | 825 | if (info != NULL) { |
never@739 | 826 | add_debug_info_for_null_check(null_check_here, info); |
never@739 | 827 | } |
duke@435 | 828 | } |
duke@435 | 829 | |
duke@435 | 830 | |
duke@435 | 831 | void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 832 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 833 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 834 | |
duke@435 | 835 | // move between cpu-registers |
duke@435 | 836 | if (dest->is_single_cpu()) { |
never@739 | 837 | #ifdef _LP64 |
never@739 | 838 | if (src->type() == T_LONG) { |
never@739 | 839 | // Can do LONG -> OBJECT |
never@739 | 840 | move_regs(src->as_register_lo(), dest->as_register()); |
never@739 | 841 | return; |
never@739 | 842 | } |
never@739 | 843 | #endif |
duke@435 | 844 | assert(src->is_single_cpu(), "must match"); |
duke@435 | 845 | if (src->type() == T_OBJECT) { |
duke@435 | 846 | __ verify_oop(src->as_register()); |
duke@435 | 847 | } |
duke@435 | 848 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 849 | |
duke@435 | 850 | } else if (dest->is_double_cpu()) { |
never@739 | 851 | #ifdef _LP64 |
never@739 | 852 | if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
never@739 | 853 | // Surprising to me but we can see move of a long to t_object |
never@739 | 854 | __ verify_oop(src->as_register()); |
never@739 | 855 | move_regs(src->as_register(), dest->as_register_lo()); |
never@739 | 856 | return; |
never@739 | 857 | } |
never@739 | 858 | #endif |
duke@435 | 859 | assert(src->is_double_cpu(), "must match"); |
duke@435 | 860 | Register f_lo = src->as_register_lo(); |
duke@435 | 861 | Register f_hi = src->as_register_hi(); |
duke@435 | 862 | Register t_lo = dest->as_register_lo(); |
duke@435 | 863 | Register t_hi = dest->as_register_hi(); |
never@739 | 864 | #ifdef _LP64 |
never@739 | 865 | assert(f_hi == f_lo, "must be same"); |
never@739 | 866 | assert(t_hi == t_lo, "must be same"); |
never@739 | 867 | move_regs(f_lo, t_lo); |
never@739 | 868 | #else |
duke@435 | 869 | assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
duke@435 | 870 | |
never@739 | 871 | |
duke@435 | 872 | if (f_lo == t_hi && f_hi == t_lo) { |
duke@435 | 873 | swap_reg(f_lo, f_hi); |
duke@435 | 874 | } else if (f_hi == t_lo) { |
duke@435 | 875 | assert(f_lo != t_hi, "overwriting register"); |
duke@435 | 876 | move_regs(f_hi, t_hi); |
duke@435 | 877 | move_regs(f_lo, t_lo); |
duke@435 | 878 | } else { |
duke@435 | 879 | assert(f_hi != t_lo, "overwriting register"); |
duke@435 | 880 | move_regs(f_lo, t_lo); |
duke@435 | 881 | move_regs(f_hi, t_hi); |
duke@435 | 882 | } |
never@739 | 883 | #endif // LP64 |
duke@435 | 884 | |
duke@435 | 885 | // special moves from fpu-register to xmm-register |
duke@435 | 886 | // necessary for method results |
duke@435 | 887 | } else if (src->is_single_xmm() && !dest->is_single_xmm()) { |
duke@435 | 888 | __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); |
duke@435 | 889 | __ fld_s(Address(rsp, 0)); |
duke@435 | 890 | } else if (src->is_double_xmm() && !dest->is_double_xmm()) { |
duke@435 | 891 | __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); |
duke@435 | 892 | __ fld_d(Address(rsp, 0)); |
duke@435 | 893 | } else if (dest->is_single_xmm() && !src->is_single_xmm()) { |
duke@435 | 894 | __ fstp_s(Address(rsp, 0)); |
duke@435 | 895 | __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); |
duke@435 | 896 | } else if (dest->is_double_xmm() && !src->is_double_xmm()) { |
duke@435 | 897 | __ fstp_d(Address(rsp, 0)); |
duke@435 | 898 | __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); |
duke@435 | 899 | |
duke@435 | 900 | // move between xmm-registers |
duke@435 | 901 | } else if (dest->is_single_xmm()) { |
duke@435 | 902 | assert(src->is_single_xmm(), "must match"); |
duke@435 | 903 | __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); |
duke@435 | 904 | } else if (dest->is_double_xmm()) { |
duke@435 | 905 | assert(src->is_double_xmm(), "must match"); |
duke@435 | 906 | __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); |
duke@435 | 907 | |
duke@435 | 908 | // move between fpu-registers (no instruction necessary because of fpu-stack) |
duke@435 | 909 | } else if (dest->is_single_fpu() || dest->is_double_fpu()) { |
duke@435 | 910 | assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); |
duke@435 | 911 | assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); |
duke@435 | 912 | } else { |
duke@435 | 913 | ShouldNotReachHere(); |
duke@435 | 914 | } |
duke@435 | 915 | } |
duke@435 | 916 | |
duke@435 | 917 | void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
duke@435 | 918 | assert(src->is_register(), "should not call otherwise"); |
duke@435 | 919 | assert(dest->is_stack(), "should not call otherwise"); |
duke@435 | 920 | |
duke@435 | 921 | if (src->is_single_cpu()) { |
duke@435 | 922 | Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 923 | if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 924 | __ verify_oop(src->as_register()); |
never@739 | 925 | __ movptr (dst, src->as_register()); |
never@739 | 926 | } else { |
never@739 | 927 | __ movl (dst, src->as_register()); |
duke@435 | 928 | } |
duke@435 | 929 | |
duke@435 | 930 | } else if (src->is_double_cpu()) { |
duke@435 | 931 | Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 932 | Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 933 | __ movptr (dstLO, src->as_register_lo()); |
never@739 | 934 | NOT_LP64(__ movptr (dstHI, src->as_register_hi())); |
duke@435 | 935 | |
duke@435 | 936 | } else if (src->is_single_xmm()) { |
duke@435 | 937 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 938 | __ movflt(dst_addr, src->as_xmm_float_reg()); |
duke@435 | 939 | |
duke@435 | 940 | } else if (src->is_double_xmm()) { |
duke@435 | 941 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 942 | __ movdbl(dst_addr, src->as_xmm_double_reg()); |
duke@435 | 943 | |
duke@435 | 944 | } else if (src->is_single_fpu()) { |
duke@435 | 945 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 946 | Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 947 | if (pop_fpu_stack) __ fstp_s (dst_addr); |
duke@435 | 948 | else __ fst_s (dst_addr); |
duke@435 | 949 | |
duke@435 | 950 | } else if (src->is_double_fpu()) { |
duke@435 | 951 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 952 | Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 953 | if (pop_fpu_stack) __ fstp_d (dst_addr); |
duke@435 | 954 | else __ fst_d (dst_addr); |
duke@435 | 955 | |
duke@435 | 956 | } else { |
duke@435 | 957 | ShouldNotReachHere(); |
duke@435 | 958 | } |
duke@435 | 959 | } |
duke@435 | 960 | |
duke@435 | 961 | |
duke@435 | 962 | void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { |
duke@435 | 963 | LIR_Address* to_addr = dest->as_address_ptr(); |
duke@435 | 964 | PatchingStub* patch = NULL; |
duke@435 | 965 | |
duke@435 | 966 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 967 | __ verify_oop(src->as_register()); |
duke@435 | 968 | } |
duke@435 | 969 | if (patch_code != lir_patch_none) { |
duke@435 | 970 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 971 | Address toa = as_Address(to_addr); |
never@739 | 972 | assert(toa.disp() != 0, "must have"); |
duke@435 | 973 | } |
duke@435 | 974 | if (info != NULL) { |
duke@435 | 975 | add_debug_info_for_null_check_here(info); |
duke@435 | 976 | } |
duke@435 | 977 | |
duke@435 | 978 | switch (type) { |
duke@435 | 979 | case T_FLOAT: { |
duke@435 | 980 | if (src->is_single_xmm()) { |
duke@435 | 981 | __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); |
duke@435 | 982 | } else { |
duke@435 | 983 | assert(src->is_single_fpu(), "must be"); |
duke@435 | 984 | assert(src->fpu_regnr() == 0, "argument must be on TOS"); |
duke@435 | 985 | if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); |
duke@435 | 986 | else __ fst_s (as_Address(to_addr)); |
duke@435 | 987 | } |
duke@435 | 988 | break; |
duke@435 | 989 | } |
duke@435 | 990 | |
duke@435 | 991 | case T_DOUBLE: { |
duke@435 | 992 | if (src->is_double_xmm()) { |
duke@435 | 993 | __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); |
duke@435 | 994 | } else { |
duke@435 | 995 | assert(src->is_double_fpu(), "must be"); |
duke@435 | 996 | assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); |
duke@435 | 997 | if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); |
duke@435 | 998 | else __ fst_d (as_Address(to_addr)); |
duke@435 | 999 | } |
duke@435 | 1000 | break; |
duke@435 | 1001 | } |
duke@435 | 1002 | |
duke@435 | 1003 | case T_ADDRESS: // fall through |
duke@435 | 1004 | case T_ARRAY: // fall through |
duke@435 | 1005 | case T_OBJECT: // fall through |
never@739 | 1006 | #ifdef _LP64 |
never@739 | 1007 | __ movptr(as_Address(to_addr), src->as_register()); |
never@739 | 1008 | break; |
never@739 | 1009 | #endif // _LP64 |
duke@435 | 1010 | case T_INT: |
duke@435 | 1011 | __ movl(as_Address(to_addr), src->as_register()); |
duke@435 | 1012 | break; |
duke@435 | 1013 | |
duke@435 | 1014 | case T_LONG: { |
duke@435 | 1015 | Register from_lo = src->as_register_lo(); |
duke@435 | 1016 | Register from_hi = src->as_register_hi(); |
never@739 | 1017 | #ifdef _LP64 |
never@739 | 1018 | __ movptr(as_Address_lo(to_addr), from_lo); |
never@739 | 1019 | #else |
duke@435 | 1020 | Register base = to_addr->base()->as_register(); |
duke@435 | 1021 | Register index = noreg; |
duke@435 | 1022 | if (to_addr->index()->is_register()) { |
duke@435 | 1023 | index = to_addr->index()->as_register(); |
duke@435 | 1024 | } |
duke@435 | 1025 | if (base == from_lo || index == from_lo) { |
duke@435 | 1026 | assert(base != from_hi, "can't be"); |
duke@435 | 1027 | assert(index == noreg || (index != base && index != from_hi), "can't handle this"); |
duke@435 | 1028 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1029 | if (patch != NULL) { |
duke@435 | 1030 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1031 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1032 | patch_code = lir_patch_low; |
duke@435 | 1033 | } |
duke@435 | 1034 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1035 | } else { |
duke@435 | 1036 | assert(index == noreg || (index != base && index != from_lo), "can't handle this"); |
duke@435 | 1037 | __ movl(as_Address_lo(to_addr), from_lo); |
duke@435 | 1038 | if (patch != NULL) { |
duke@435 | 1039 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1040 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1041 | patch_code = lir_patch_high; |
duke@435 | 1042 | } |
duke@435 | 1043 | __ movl(as_Address_hi(to_addr), from_hi); |
duke@435 | 1044 | } |
never@739 | 1045 | #endif // _LP64 |
duke@435 | 1046 | break; |
duke@435 | 1047 | } |
duke@435 | 1048 | |
duke@435 | 1049 | case T_BYTE: // fall through |
duke@435 | 1050 | case T_BOOLEAN: { |
duke@435 | 1051 | Register src_reg = src->as_register(); |
duke@435 | 1052 | Address dst_addr = as_Address(to_addr); |
duke@435 | 1053 | assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1054 | __ movb(dst_addr, src_reg); |
duke@435 | 1055 | break; |
duke@435 | 1056 | } |
duke@435 | 1057 | |
duke@435 | 1058 | case T_CHAR: // fall through |
duke@435 | 1059 | case T_SHORT: |
duke@435 | 1060 | __ movw(as_Address(to_addr), src->as_register()); |
duke@435 | 1061 | break; |
duke@435 | 1062 | |
duke@435 | 1063 | default: |
duke@435 | 1064 | ShouldNotReachHere(); |
duke@435 | 1065 | } |
duke@435 | 1066 | |
duke@435 | 1067 | if (patch_code != lir_patch_none) { |
duke@435 | 1068 | patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); |
duke@435 | 1069 | } |
duke@435 | 1070 | } |
duke@435 | 1071 | |
duke@435 | 1072 | |
duke@435 | 1073 | void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1074 | assert(src->is_stack(), "should not call otherwise"); |
duke@435 | 1075 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1076 | |
duke@435 | 1077 | if (dest->is_single_cpu()) { |
duke@435 | 1078 | if (type == T_ARRAY || type == T_OBJECT) { |
never@739 | 1079 | __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1080 | __ verify_oop(dest->as_register()); |
never@739 | 1081 | } else { |
never@739 | 1082 | __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
duke@435 | 1083 | } |
duke@435 | 1084 | |
duke@435 | 1085 | } else if (dest->is_double_cpu()) { |
duke@435 | 1086 | Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); |
duke@435 | 1087 | Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); |
never@739 | 1088 | __ movptr(dest->as_register_lo(), src_addr_LO); |
never@739 | 1089 | NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); |
duke@435 | 1090 | |
duke@435 | 1091 | } else if (dest->is_single_xmm()) { |
duke@435 | 1092 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1093 | __ movflt(dest->as_xmm_float_reg(), src_addr); |
duke@435 | 1094 | |
duke@435 | 1095 | } else if (dest->is_double_xmm()) { |
duke@435 | 1096 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1097 | __ movdbl(dest->as_xmm_double_reg(), src_addr); |
duke@435 | 1098 | |
duke@435 | 1099 | } else if (dest->is_single_fpu()) { |
duke@435 | 1100 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1101 | Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1102 | __ fld_s(src_addr); |
duke@435 | 1103 | |
duke@435 | 1104 | } else if (dest->is_double_fpu()) { |
duke@435 | 1105 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1106 | Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); |
duke@435 | 1107 | __ fld_d(src_addr); |
duke@435 | 1108 | |
duke@435 | 1109 | } else { |
duke@435 | 1110 | ShouldNotReachHere(); |
duke@435 | 1111 | } |
duke@435 | 1112 | } |
duke@435 | 1113 | |
duke@435 | 1114 | |
duke@435 | 1115 | void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1116 | if (src->is_single_stack()) { |
never@739 | 1117 | if (type == T_OBJECT || type == T_ARRAY) { |
never@739 | 1118 | __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1119 | __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); |
never@739 | 1120 | } else { |
never@739 | 1121 | __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
never@739 | 1122 | __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); |
never@739 | 1123 | } |
duke@435 | 1124 | |
duke@435 | 1125 | } else if (src->is_double_stack()) { |
never@739 | 1126 | #ifdef _LP64 |
never@739 | 1127 | __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); |
never@739 | 1128 | __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); |
never@739 | 1129 | #else |
duke@435 | 1130 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
never@739 | 1131 | // push and pop the part at src + wordSize, adding wordSize for the previous push |
never@756 | 1132 | __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
never@756 | 1133 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
duke@435 | 1134 | __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
never@739 | 1135 | #endif // _LP64 |
duke@435 | 1136 | |
duke@435 | 1137 | } else { |
duke@435 | 1138 | ShouldNotReachHere(); |
duke@435 | 1139 | } |
duke@435 | 1140 | } |
duke@435 | 1141 | |
duke@435 | 1142 | |
duke@435 | 1143 | void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { |
duke@435 | 1144 | assert(src->is_address(), "should not call otherwise"); |
duke@435 | 1145 | assert(dest->is_register(), "should not call otherwise"); |
duke@435 | 1146 | |
duke@435 | 1147 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1148 | Address from_addr = as_Address(addr); |
duke@435 | 1149 | |
duke@435 | 1150 | switch (type) { |
duke@435 | 1151 | case T_BOOLEAN: // fall through |
duke@435 | 1152 | case T_BYTE: // fall through |
duke@435 | 1153 | case T_CHAR: // fall through |
duke@435 | 1154 | case T_SHORT: |
duke@435 | 1155 | if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { |
duke@435 | 1156 | // on pre P6 processors we may get partial register stalls |
duke@435 | 1157 | // so blow away the value of to_rinfo before loading a |
duke@435 | 1158 | // partial word into it. Do it here so that it precedes |
duke@435 | 1159 | // the potential patch point below. |
never@739 | 1160 | __ xorptr(dest->as_register(), dest->as_register()); |
duke@435 | 1161 | } |
duke@435 | 1162 | break; |
duke@435 | 1163 | } |
duke@435 | 1164 | |
duke@435 | 1165 | PatchingStub* patch = NULL; |
duke@435 | 1166 | if (patch_code != lir_patch_none) { |
duke@435 | 1167 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
never@739 | 1168 | assert(from_addr.disp() != 0, "must have"); |
duke@435 | 1169 | } |
duke@435 | 1170 | if (info != NULL) { |
duke@435 | 1171 | add_debug_info_for_null_check_here(info); |
duke@435 | 1172 | } |
duke@435 | 1173 | |
duke@435 | 1174 | switch (type) { |
duke@435 | 1175 | case T_FLOAT: { |
duke@435 | 1176 | if (dest->is_single_xmm()) { |
duke@435 | 1177 | __ movflt(dest->as_xmm_float_reg(), from_addr); |
duke@435 | 1178 | } else { |
duke@435 | 1179 | assert(dest->is_single_fpu(), "must be"); |
duke@435 | 1180 | assert(dest->fpu_regnr() == 0, "dest must be TOS"); |
duke@435 | 1181 | __ fld_s(from_addr); |
duke@435 | 1182 | } |
duke@435 | 1183 | break; |
duke@435 | 1184 | } |
duke@435 | 1185 | |
duke@435 | 1186 | case T_DOUBLE: { |
duke@435 | 1187 | if (dest->is_double_xmm()) { |
duke@435 | 1188 | __ movdbl(dest->as_xmm_double_reg(), from_addr); |
duke@435 | 1189 | } else { |
duke@435 | 1190 | assert(dest->is_double_fpu(), "must be"); |
duke@435 | 1191 | assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); |
duke@435 | 1192 | __ fld_d(from_addr); |
duke@435 | 1193 | } |
duke@435 | 1194 | break; |
duke@435 | 1195 | } |
duke@435 | 1196 | |
duke@435 | 1197 | case T_ADDRESS: // fall through |
duke@435 | 1198 | case T_OBJECT: // fall through |
duke@435 | 1199 | case T_ARRAY: // fall through |
never@739 | 1200 | #ifdef _LP64 |
never@739 | 1201 | __ movptr(dest->as_register(), from_addr); |
never@739 | 1202 | break; |
never@739 | 1203 | #endif // _L64 |
duke@435 | 1204 | case T_INT: |
never@739 | 1205 | // %%% could this be a movl? this is safer but longer instruction |
never@739 | 1206 | __ movl2ptr(dest->as_register(), from_addr); |
duke@435 | 1207 | break; |
duke@435 | 1208 | |
duke@435 | 1209 | case T_LONG: { |
duke@435 | 1210 | Register to_lo = dest->as_register_lo(); |
duke@435 | 1211 | Register to_hi = dest->as_register_hi(); |
never@739 | 1212 | #ifdef _LP64 |
never@739 | 1213 | __ movptr(to_lo, as_Address_lo(addr)); |
never@739 | 1214 | #else |
duke@435 | 1215 | Register base = addr->base()->as_register(); |
duke@435 | 1216 | Register index = noreg; |
duke@435 | 1217 | if (addr->index()->is_register()) { |
duke@435 | 1218 | index = addr->index()->as_register(); |
duke@435 | 1219 | } |
duke@435 | 1220 | if ((base == to_lo && index == to_hi) || |
duke@435 | 1221 | (base == to_hi && index == to_lo)) { |
duke@435 | 1222 | // addresses with 2 registers are only formed as a result of |
duke@435 | 1223 | // array access so this code will never have to deal with |
duke@435 | 1224 | // patches or null checks. |
duke@435 | 1225 | assert(info == NULL && patch == NULL, "must be"); |
never@739 | 1226 | __ lea(to_hi, as_Address(addr)); |
duke@435 | 1227 | __ movl(to_lo, Address(to_hi, 0)); |
duke@435 | 1228 | __ movl(to_hi, Address(to_hi, BytesPerWord)); |
duke@435 | 1229 | } else if (base == to_lo || index == to_lo) { |
duke@435 | 1230 | assert(base != to_hi, "can't be"); |
duke@435 | 1231 | assert(index == noreg || (index != base && index != to_hi), "can't handle this"); |
duke@435 | 1232 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1233 | if (patch != NULL) { |
duke@435 | 1234 | patching_epilog(patch, lir_patch_high, base, info); |
duke@435 | 1235 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1236 | patch_code = lir_patch_low; |
duke@435 | 1237 | } |
duke@435 | 1238 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1239 | } else { |
duke@435 | 1240 | assert(index == noreg || (index != base && index != to_lo), "can't handle this"); |
duke@435 | 1241 | __ movl(to_lo, as_Address_lo(addr)); |
duke@435 | 1242 | if (patch != NULL) { |
duke@435 | 1243 | patching_epilog(patch, lir_patch_low, base, info); |
duke@435 | 1244 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1245 | patch_code = lir_patch_high; |
duke@435 | 1246 | } |
duke@435 | 1247 | __ movl(to_hi, as_Address_hi(addr)); |
duke@435 | 1248 | } |
never@739 | 1249 | #endif // _LP64 |
duke@435 | 1250 | break; |
duke@435 | 1251 | } |
duke@435 | 1252 | |
duke@435 | 1253 | case T_BOOLEAN: // fall through |
duke@435 | 1254 | case T_BYTE: { |
duke@435 | 1255 | Register dest_reg = dest->as_register(); |
duke@435 | 1256 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1257 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1258 | __ movsbl(dest_reg, from_addr); |
duke@435 | 1259 | } else { |
duke@435 | 1260 | __ movb(dest_reg, from_addr); |
duke@435 | 1261 | __ shll(dest_reg, 24); |
duke@435 | 1262 | __ sarl(dest_reg, 24); |
duke@435 | 1263 | } |
never@739 | 1264 | // These are unsigned so the zero extension on 64bit is just what we need |
duke@435 | 1265 | break; |
duke@435 | 1266 | } |
duke@435 | 1267 | |
duke@435 | 1268 | case T_CHAR: { |
duke@435 | 1269 | Register dest_reg = dest->as_register(); |
duke@435 | 1270 | assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); |
duke@435 | 1271 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1272 | __ movzwl(dest_reg, from_addr); |
duke@435 | 1273 | } else { |
duke@435 | 1274 | __ movw(dest_reg, from_addr); |
duke@435 | 1275 | } |
never@739 | 1276 | // This is unsigned so the zero extension on 64bit is just what we need |
never@739 | 1277 | // __ movl2ptr(dest_reg, dest_reg); |
duke@435 | 1278 | break; |
duke@435 | 1279 | } |
duke@435 | 1280 | |
duke@435 | 1281 | case T_SHORT: { |
duke@435 | 1282 | Register dest_reg = dest->as_register(); |
duke@435 | 1283 | if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { |
never@739 | 1284 | __ movswl(dest_reg, from_addr); |
duke@435 | 1285 | } else { |
duke@435 | 1286 | __ movw(dest_reg, from_addr); |
duke@435 | 1287 | __ shll(dest_reg, 16); |
duke@435 | 1288 | __ sarl(dest_reg, 16); |
duke@435 | 1289 | } |
never@739 | 1290 | // Might not be needed in 64bit but certainly doesn't hurt (except for code size) |
never@739 | 1291 | __ movl2ptr(dest_reg, dest_reg); |
duke@435 | 1292 | break; |
duke@435 | 1293 | } |
duke@435 | 1294 | |
duke@435 | 1295 | default: |
duke@435 | 1296 | ShouldNotReachHere(); |
duke@435 | 1297 | } |
duke@435 | 1298 | |
duke@435 | 1299 | if (patch != NULL) { |
duke@435 | 1300 | patching_epilog(patch, patch_code, addr->base()->as_register(), info); |
duke@435 | 1301 | } |
duke@435 | 1302 | |
duke@435 | 1303 | if (type == T_ARRAY || type == T_OBJECT) { |
duke@435 | 1304 | __ verify_oop(dest->as_register()); |
duke@435 | 1305 | } |
duke@435 | 1306 | } |
duke@435 | 1307 | |
duke@435 | 1308 | |
duke@435 | 1309 | void LIR_Assembler::prefetchr(LIR_Opr src) { |
duke@435 | 1310 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1311 | Address from_addr = as_Address(addr); |
duke@435 | 1312 | |
duke@435 | 1313 | if (VM_Version::supports_sse()) { |
duke@435 | 1314 | switch (ReadPrefetchInstr) { |
duke@435 | 1315 | case 0: |
duke@435 | 1316 | __ prefetchnta(from_addr); break; |
duke@435 | 1317 | case 1: |
duke@435 | 1318 | __ prefetcht0(from_addr); break; |
duke@435 | 1319 | case 2: |
duke@435 | 1320 | __ prefetcht2(from_addr); break; |
duke@435 | 1321 | default: |
duke@435 | 1322 | ShouldNotReachHere(); break; |
duke@435 | 1323 | } |
duke@435 | 1324 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1325 | __ prefetchr(from_addr); |
duke@435 | 1326 | } |
duke@435 | 1327 | } |
duke@435 | 1328 | |
duke@435 | 1329 | |
duke@435 | 1330 | void LIR_Assembler::prefetchw(LIR_Opr src) { |
duke@435 | 1331 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1332 | Address from_addr = as_Address(addr); |
duke@435 | 1333 | |
duke@435 | 1334 | if (VM_Version::supports_sse()) { |
duke@435 | 1335 | switch (AllocatePrefetchInstr) { |
duke@435 | 1336 | case 0: |
duke@435 | 1337 | __ prefetchnta(from_addr); break; |
duke@435 | 1338 | case 1: |
duke@435 | 1339 | __ prefetcht0(from_addr); break; |
duke@435 | 1340 | case 2: |
duke@435 | 1341 | __ prefetcht2(from_addr); break; |
duke@435 | 1342 | case 3: |
duke@435 | 1343 | __ prefetchw(from_addr); break; |
duke@435 | 1344 | default: |
duke@435 | 1345 | ShouldNotReachHere(); break; |
duke@435 | 1346 | } |
duke@435 | 1347 | } else if (VM_Version::supports_3dnow()) { |
duke@435 | 1348 | __ prefetchw(from_addr); |
duke@435 | 1349 | } |
duke@435 | 1350 | } |
duke@435 | 1351 | |
duke@435 | 1352 | |
duke@435 | 1353 | NEEDS_CLEANUP; // This could be static? |
duke@435 | 1354 | Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { |
kvn@464 | 1355 | int elem_size = type2aelembytes(type); |
duke@435 | 1356 | switch (elem_size) { |
duke@435 | 1357 | case 1: return Address::times_1; |
duke@435 | 1358 | case 2: return Address::times_2; |
duke@435 | 1359 | case 4: return Address::times_4; |
duke@435 | 1360 | case 8: return Address::times_8; |
duke@435 | 1361 | } |
duke@435 | 1362 | ShouldNotReachHere(); |
duke@435 | 1363 | return Address::no_scale; |
duke@435 | 1364 | } |
duke@435 | 1365 | |
duke@435 | 1366 | |
duke@435 | 1367 | void LIR_Assembler::emit_op3(LIR_Op3* op) { |
duke@435 | 1368 | switch (op->code()) { |
duke@435 | 1369 | case lir_idiv: |
duke@435 | 1370 | case lir_irem: |
duke@435 | 1371 | arithmetic_idiv(op->code(), |
duke@435 | 1372 | op->in_opr1(), |
duke@435 | 1373 | op->in_opr2(), |
duke@435 | 1374 | op->in_opr3(), |
duke@435 | 1375 | op->result_opr(), |
duke@435 | 1376 | op->info()); |
duke@435 | 1377 | break; |
duke@435 | 1378 | default: ShouldNotReachHere(); break; |
duke@435 | 1379 | } |
duke@435 | 1380 | } |
duke@435 | 1381 | |
duke@435 | 1382 | void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
duke@435 | 1383 | #ifdef ASSERT |
duke@435 | 1384 | assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
duke@435 | 1385 | if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
duke@435 | 1386 | if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
duke@435 | 1387 | #endif |
duke@435 | 1388 | |
duke@435 | 1389 | if (op->cond() == lir_cond_always) { |
duke@435 | 1390 | if (op->info() != NULL) add_debug_info_for_branch(op->info()); |
duke@435 | 1391 | __ jmp (*(op->label())); |
duke@435 | 1392 | } else { |
duke@435 | 1393 | Assembler::Condition acond = Assembler::zero; |
duke@435 | 1394 | if (op->code() == lir_cond_float_branch) { |
duke@435 | 1395 | assert(op->ublock() != NULL, "must have unordered successor"); |
duke@435 | 1396 | __ jcc(Assembler::parity, *(op->ublock()->label())); |
duke@435 | 1397 | switch(op->cond()) { |
duke@435 | 1398 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1399 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1400 | case lir_cond_less: acond = Assembler::below; break; |
duke@435 | 1401 | case lir_cond_lessEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1402 | case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1403 | case lir_cond_greater: acond = Assembler::above; break; |
duke@435 | 1404 | default: ShouldNotReachHere(); |
duke@435 | 1405 | } |
duke@435 | 1406 | } else { |
duke@435 | 1407 | switch (op->cond()) { |
duke@435 | 1408 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1409 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1410 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 1411 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 1412 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; |
duke@435 | 1413 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 1414 | case lir_cond_belowEqual: acond = Assembler::belowEqual; break; |
duke@435 | 1415 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; |
duke@435 | 1416 | default: ShouldNotReachHere(); |
duke@435 | 1417 | } |
duke@435 | 1418 | } |
duke@435 | 1419 | __ jcc(acond,*(op->label())); |
duke@435 | 1420 | } |
duke@435 | 1421 | } |
duke@435 | 1422 | |
duke@435 | 1423 | void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
duke@435 | 1424 | LIR_Opr src = op->in_opr(); |
duke@435 | 1425 | LIR_Opr dest = op->result_opr(); |
duke@435 | 1426 | |
duke@435 | 1427 | switch (op->bytecode()) { |
duke@435 | 1428 | case Bytecodes::_i2l: |
never@739 | 1429 | #ifdef _LP64 |
never@739 | 1430 | __ movl2ptr(dest->as_register_lo(), src->as_register()); |
never@739 | 1431 | #else |
duke@435 | 1432 | move_regs(src->as_register(), dest->as_register_lo()); |
duke@435 | 1433 | move_regs(src->as_register(), dest->as_register_hi()); |
duke@435 | 1434 | __ sarl(dest->as_register_hi(), 31); |
never@739 | 1435 | #endif // LP64 |
duke@435 | 1436 | break; |
duke@435 | 1437 | |
duke@435 | 1438 | case Bytecodes::_l2i: |
duke@435 | 1439 | move_regs(src->as_register_lo(), dest->as_register()); |
duke@435 | 1440 | break; |
duke@435 | 1441 | |
duke@435 | 1442 | case Bytecodes::_i2b: |
duke@435 | 1443 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1444 | __ sign_extend_byte(dest->as_register()); |
duke@435 | 1445 | break; |
duke@435 | 1446 | |
duke@435 | 1447 | case Bytecodes::_i2c: |
duke@435 | 1448 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1449 | __ andl(dest->as_register(), 0xFFFF); |
duke@435 | 1450 | break; |
duke@435 | 1451 | |
duke@435 | 1452 | case Bytecodes::_i2s: |
duke@435 | 1453 | move_regs(src->as_register(), dest->as_register()); |
duke@435 | 1454 | __ sign_extend_short(dest->as_register()); |
duke@435 | 1455 | break; |
duke@435 | 1456 | |
duke@435 | 1457 | |
duke@435 | 1458 | case Bytecodes::_f2d: |
duke@435 | 1459 | case Bytecodes::_d2f: |
duke@435 | 1460 | if (dest->is_single_xmm()) { |
duke@435 | 1461 | __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); |
duke@435 | 1462 | } else if (dest->is_double_xmm()) { |
duke@435 | 1463 | __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); |
duke@435 | 1464 | } else { |
duke@435 | 1465 | assert(src->fpu() == dest->fpu(), "register must be equal"); |
duke@435 | 1466 | // do nothing (float result is rounded later through spilling) |
duke@435 | 1467 | } |
duke@435 | 1468 | break; |
duke@435 | 1469 | |
duke@435 | 1470 | case Bytecodes::_i2f: |
duke@435 | 1471 | case Bytecodes::_i2d: |
duke@435 | 1472 | if (dest->is_single_xmm()) { |
never@739 | 1473 | __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
duke@435 | 1474 | } else if (dest->is_double_xmm()) { |
never@739 | 1475 | __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
duke@435 | 1476 | } else { |
duke@435 | 1477 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1478 | __ movl(Address(rsp, 0), src->as_register()); |
duke@435 | 1479 | __ fild_s(Address(rsp, 0)); |
duke@435 | 1480 | } |
duke@435 | 1481 | break; |
duke@435 | 1482 | |
duke@435 | 1483 | case Bytecodes::_f2i: |
duke@435 | 1484 | case Bytecodes::_d2i: |
duke@435 | 1485 | if (src->is_single_xmm()) { |
never@739 | 1486 | __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
duke@435 | 1487 | } else if (src->is_double_xmm()) { |
never@739 | 1488 | __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
duke@435 | 1489 | } else { |
duke@435 | 1490 | assert(src->fpu() == 0, "input must be on TOS"); |
duke@435 | 1491 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); |
duke@435 | 1492 | __ fist_s(Address(rsp, 0)); |
duke@435 | 1493 | __ movl(dest->as_register(), Address(rsp, 0)); |
duke@435 | 1494 | __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
duke@435 | 1495 | } |
duke@435 | 1496 | |
duke@435 | 1497 | // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub |
duke@435 | 1498 | assert(op->stub() != NULL, "stub required"); |
duke@435 | 1499 | __ cmpl(dest->as_register(), 0x80000000); |
duke@435 | 1500 | __ jcc(Assembler::equal, *op->stub()->entry()); |
duke@435 | 1501 | __ bind(*op->stub()->continuation()); |
duke@435 | 1502 | break; |
duke@435 | 1503 | |
duke@435 | 1504 | case Bytecodes::_l2f: |
duke@435 | 1505 | case Bytecodes::_l2d: |
duke@435 | 1506 | assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1507 | assert(dest->fpu() == 0, "result must be on TOS"); |
duke@435 | 1508 | |
never@739 | 1509 | __ movptr(Address(rsp, 0), src->as_register_lo()); |
never@739 | 1510 | NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); |
duke@435 | 1511 | __ fild_d(Address(rsp, 0)); |
duke@435 | 1512 | // float result is rounded later through spilling |
duke@435 | 1513 | break; |
duke@435 | 1514 | |
duke@435 | 1515 | case Bytecodes::_f2l: |
duke@435 | 1516 | case Bytecodes::_d2l: |
duke@435 | 1517 | assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); |
duke@435 | 1518 | assert(src->fpu() == 0, "input must be on TOS"); |
never@739 | 1519 | assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
duke@435 | 1520 | |
duke@435 | 1521 | // instruction sequence too long to inline it here |
duke@435 | 1522 | { |
duke@435 | 1523 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); |
duke@435 | 1524 | } |
duke@435 | 1525 | break; |
duke@435 | 1526 | |
duke@435 | 1527 | default: ShouldNotReachHere(); |
duke@435 | 1528 | } |
duke@435 | 1529 | } |
duke@435 | 1530 | |
duke@435 | 1531 | void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
duke@435 | 1532 | if (op->init_check()) { |
duke@435 | 1533 | __ cmpl(Address(op->klass()->as_register(), |
duke@435 | 1534 | instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), |
duke@435 | 1535 | instanceKlass::fully_initialized); |
duke@435 | 1536 | add_debug_info_for_null_check_here(op->stub()->info()); |
duke@435 | 1537 | __ jcc(Assembler::notEqual, *op->stub()->entry()); |
duke@435 | 1538 | } |
duke@435 | 1539 | __ allocate_object(op->obj()->as_register(), |
duke@435 | 1540 | op->tmp1()->as_register(), |
duke@435 | 1541 | op->tmp2()->as_register(), |
duke@435 | 1542 | op->header_size(), |
duke@435 | 1543 | op->object_size(), |
duke@435 | 1544 | op->klass()->as_register(), |
duke@435 | 1545 | *op->stub()->entry()); |
duke@435 | 1546 | __ bind(*op->stub()->continuation()); |
duke@435 | 1547 | } |
duke@435 | 1548 | |
duke@435 | 1549 | void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
duke@435 | 1550 | if (UseSlowPath || |
duke@435 | 1551 | (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
duke@435 | 1552 | (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
duke@435 | 1553 | __ jmp(*op->stub()->entry()); |
duke@435 | 1554 | } else { |
duke@435 | 1555 | Register len = op->len()->as_register(); |
duke@435 | 1556 | Register tmp1 = op->tmp1()->as_register(); |
duke@435 | 1557 | Register tmp2 = op->tmp2()->as_register(); |
duke@435 | 1558 | Register tmp3 = op->tmp3()->as_register(); |
duke@435 | 1559 | if (len == tmp1) { |
duke@435 | 1560 | tmp1 = tmp3; |
duke@435 | 1561 | } else if (len == tmp2) { |
duke@435 | 1562 | tmp2 = tmp3; |
duke@435 | 1563 | } else if (len == tmp3) { |
duke@435 | 1564 | // everything is ok |
duke@435 | 1565 | } else { |
never@739 | 1566 | __ mov(tmp3, len); |
duke@435 | 1567 | } |
duke@435 | 1568 | __ allocate_array(op->obj()->as_register(), |
duke@435 | 1569 | len, |
duke@435 | 1570 | tmp1, |
duke@435 | 1571 | tmp2, |
duke@435 | 1572 | arrayOopDesc::header_size(op->type()), |
duke@435 | 1573 | array_element_size(op->type()), |
duke@435 | 1574 | op->klass()->as_register(), |
duke@435 | 1575 | *op->stub()->entry()); |
duke@435 | 1576 | } |
duke@435 | 1577 | __ bind(*op->stub()->continuation()); |
duke@435 | 1578 | } |
duke@435 | 1579 | |
duke@435 | 1580 | |
duke@435 | 1581 | |
duke@435 | 1582 | void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
duke@435 | 1583 | LIR_Code code = op->code(); |
duke@435 | 1584 | if (code == lir_store_check) { |
duke@435 | 1585 | Register value = op->object()->as_register(); |
duke@435 | 1586 | Register array = op->array()->as_register(); |
duke@435 | 1587 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1588 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1589 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1590 | |
duke@435 | 1591 | CodeStub* stub = op->stub(); |
duke@435 | 1592 | Label done; |
never@739 | 1593 | __ cmpptr(value, (int32_t)NULL_WORD); |
duke@435 | 1594 | __ jcc(Assembler::equal, done); |
duke@435 | 1595 | add_debug_info_for_null_check_here(op->info_for_exception()); |
never@739 | 1596 | __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
never@739 | 1597 | __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1598 | |
duke@435 | 1599 | // get instance klass |
never@739 | 1600 | __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
duke@435 | 1601 | // get super_check_offset |
duke@435 | 1602 | __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); |
duke@435 | 1603 | // See if we get an immediate positive hit |
never@739 | 1604 | __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1)); |
duke@435 | 1605 | __ jcc(Assembler::equal, done); |
duke@435 | 1606 | // check for immediate negative hit |
duke@435 | 1607 | __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); |
duke@435 | 1608 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1609 | // check for self |
never@739 | 1610 | __ cmpptr(klass_RInfo, k_RInfo); |
duke@435 | 1611 | __ jcc(Assembler::equal, done); |
duke@435 | 1612 | |
never@739 | 1613 | __ push(klass_RInfo); |
never@739 | 1614 | __ push(k_RInfo); |
duke@435 | 1615 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1616 | __ pop(klass_RInfo); |
never@739 | 1617 | __ pop(k_RInfo); |
never@739 | 1618 | // result is a boolean |
duke@435 | 1619 | __ cmpl(k_RInfo, 0); |
duke@435 | 1620 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1621 | __ bind(done); |
duke@435 | 1622 | } else if (op->code() == lir_checkcast) { |
duke@435 | 1623 | // we always need a stub for the failure case. |
duke@435 | 1624 | CodeStub* stub = op->stub(); |
duke@435 | 1625 | Register obj = op->object()->as_register(); |
duke@435 | 1626 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1627 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1628 | Register dst = op->result_opr()->as_register(); |
duke@435 | 1629 | ciKlass* k = op->klass(); |
duke@435 | 1630 | Register Rtmp1 = noreg; |
duke@435 | 1631 | |
duke@435 | 1632 | Label done; |
duke@435 | 1633 | if (obj == k_RInfo) { |
duke@435 | 1634 | k_RInfo = dst; |
duke@435 | 1635 | } else if (obj == klass_RInfo) { |
duke@435 | 1636 | klass_RInfo = dst; |
duke@435 | 1637 | } |
duke@435 | 1638 | if (k->is_loaded()) { |
duke@435 | 1639 | select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
duke@435 | 1640 | } else { |
duke@435 | 1641 | Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 1642 | select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); |
duke@435 | 1643 | } |
duke@435 | 1644 | |
duke@435 | 1645 | assert_different_registers(obj, k_RInfo, klass_RInfo); |
duke@435 | 1646 | if (!k->is_loaded()) { |
duke@435 | 1647 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
duke@435 | 1648 | } else { |
never@739 | 1649 | #ifdef _LP64 |
never@739 | 1650 | __ movoop(k_RInfo, k->encoding()); |
never@739 | 1651 | #else |
duke@435 | 1652 | k_RInfo = noreg; |
never@739 | 1653 | #endif // _LP64 |
duke@435 | 1654 | } |
duke@435 | 1655 | assert(obj != k_RInfo, "must be different"); |
never@739 | 1656 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1657 | if (op->profiled_method() != NULL) { |
duke@435 | 1658 | ciMethod* method = op->profiled_method(); |
duke@435 | 1659 | int bci = op->profiled_bci(); |
duke@435 | 1660 | |
duke@435 | 1661 | Label profile_done; |
duke@435 | 1662 | __ jcc(Assembler::notEqual, profile_done); |
duke@435 | 1663 | // Object is null; update methodDataOop |
duke@435 | 1664 | ciMethodData* md = method->method_data(); |
duke@435 | 1665 | if (md == NULL) { |
duke@435 | 1666 | bailout("out of memory building methodDataOop"); |
duke@435 | 1667 | return; |
duke@435 | 1668 | } |
duke@435 | 1669 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 1670 | assert(data != NULL, "need data for checkcast"); |
duke@435 | 1671 | assert(data->is_BitData(), "need BitData for checkcast"); |
duke@435 | 1672 | Register mdo = klass_RInfo; |
duke@435 | 1673 | __ movoop(mdo, md->encoding()); |
duke@435 | 1674 | Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
duke@435 | 1675 | int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
duke@435 | 1676 | __ orl(data_addr, header_bits); |
duke@435 | 1677 | __ jmp(done); |
duke@435 | 1678 | __ bind(profile_done); |
duke@435 | 1679 | } else { |
duke@435 | 1680 | __ jcc(Assembler::equal, done); |
duke@435 | 1681 | } |
duke@435 | 1682 | __ verify_oop(obj); |
duke@435 | 1683 | |
duke@435 | 1684 | if (op->fast_check()) { |
duke@435 | 1685 | // get object classo |
duke@435 | 1686 | // not a safepoint as obj null check happens earlier |
duke@435 | 1687 | if (k->is_loaded()) { |
never@739 | 1688 | #ifdef _LP64 |
never@739 | 1689 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
never@739 | 1690 | #else |
duke@435 | 1691 | __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding()); |
never@739 | 1692 | #endif // _LP64 |
duke@435 | 1693 | } else { |
never@739 | 1694 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1695 | |
duke@435 | 1696 | } |
duke@435 | 1697 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1698 | __ bind(done); |
duke@435 | 1699 | } else { |
duke@435 | 1700 | // get object class |
duke@435 | 1701 | // not a safepoint as obj null check happens earlier |
never@739 | 1702 | __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1703 | if (k->is_loaded()) { |
duke@435 | 1704 | // See if we get an immediate positive hit |
never@739 | 1705 | #ifdef _LP64 |
never@739 | 1706 | __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); |
never@739 | 1707 | #else |
duke@435 | 1708 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding()); |
never@739 | 1709 | #endif // _LP64 |
duke@435 | 1710 | if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { |
duke@435 | 1711 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1712 | } else { |
duke@435 | 1713 | // See if we get an immediate positive hit |
duke@435 | 1714 | __ jcc(Assembler::equal, done); |
duke@435 | 1715 | // check for self |
never@739 | 1716 | #ifdef _LP64 |
never@739 | 1717 | __ cmpptr(klass_RInfo, k_RInfo); |
never@739 | 1718 | #else |
duke@435 | 1719 | __ cmpoop(klass_RInfo, k->encoding()); |
never@739 | 1720 | #endif // _LP64 |
duke@435 | 1721 | __ jcc(Assembler::equal, done); |
duke@435 | 1722 | |
never@739 | 1723 | __ push(klass_RInfo); |
never@739 | 1724 | #ifdef _LP64 |
never@739 | 1725 | __ push(k_RInfo); |
never@739 | 1726 | #else |
duke@435 | 1727 | __ pushoop(k->encoding()); |
never@739 | 1728 | #endif // _LP64 |
duke@435 | 1729 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1730 | __ pop(klass_RInfo); |
never@739 | 1731 | __ pop(klass_RInfo); |
never@739 | 1732 | // result is a boolean |
duke@435 | 1733 | __ cmpl(klass_RInfo, 0); |
duke@435 | 1734 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1735 | } |
duke@435 | 1736 | __ bind(done); |
duke@435 | 1737 | } else { |
duke@435 | 1738 | __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); |
duke@435 | 1739 | // See if we get an immediate positive hit |
never@739 | 1740 | __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1)); |
duke@435 | 1741 | __ jcc(Assembler::equal, done); |
duke@435 | 1742 | // check for immediate negative hit |
duke@435 | 1743 | __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); |
duke@435 | 1744 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 1745 | // check for self |
never@739 | 1746 | __ cmpptr(klass_RInfo, k_RInfo); |
duke@435 | 1747 | __ jcc(Assembler::equal, done); |
duke@435 | 1748 | |
never@739 | 1749 | __ push(klass_RInfo); |
never@739 | 1750 | __ push(k_RInfo); |
duke@435 | 1751 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1752 | __ pop(klass_RInfo); |
never@739 | 1753 | __ pop(k_RInfo); |
never@739 | 1754 | // result is a boolean |
duke@435 | 1755 | __ cmpl(k_RInfo, 0); |
duke@435 | 1756 | __ jcc(Assembler::equal, *stub->entry()); |
duke@435 | 1757 | __ bind(done); |
duke@435 | 1758 | } |
duke@435 | 1759 | |
duke@435 | 1760 | } |
duke@435 | 1761 | if (dst != obj) { |
never@739 | 1762 | __ mov(dst, obj); |
duke@435 | 1763 | } |
duke@435 | 1764 | } else if (code == lir_instanceof) { |
duke@435 | 1765 | Register obj = op->object()->as_register(); |
duke@435 | 1766 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 1767 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 1768 | Register dst = op->result_opr()->as_register(); |
duke@435 | 1769 | ciKlass* k = op->klass(); |
duke@435 | 1770 | |
duke@435 | 1771 | Label done; |
duke@435 | 1772 | Label zero; |
duke@435 | 1773 | Label one; |
duke@435 | 1774 | if (obj == k_RInfo) { |
duke@435 | 1775 | k_RInfo = klass_RInfo; |
duke@435 | 1776 | klass_RInfo = obj; |
duke@435 | 1777 | } |
duke@435 | 1778 | // patching may screw with our temporaries on sparc, |
duke@435 | 1779 | // so let's do it before loading the class |
duke@435 | 1780 | if (!k->is_loaded()) { |
duke@435 | 1781 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
never@739 | 1782 | } else { |
never@739 | 1783 | LP64_ONLY(__ movoop(k_RInfo, k->encoding())); |
duke@435 | 1784 | } |
duke@435 | 1785 | assert(obj != k_RInfo, "must be different"); |
duke@435 | 1786 | |
duke@435 | 1787 | __ verify_oop(obj); |
duke@435 | 1788 | if (op->fast_check()) { |
never@739 | 1789 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1790 | __ jcc(Assembler::equal, zero); |
duke@435 | 1791 | // get object class |
duke@435 | 1792 | // not a safepoint as obj null check happens earlier |
never@739 | 1793 | if (LP64_ONLY(false &&) k->is_loaded()) { |
never@739 | 1794 | NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding())); |
duke@435 | 1795 | k_RInfo = noreg; |
duke@435 | 1796 | } else { |
never@739 | 1797 | __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
duke@435 | 1798 | |
duke@435 | 1799 | } |
duke@435 | 1800 | __ jcc(Assembler::equal, one); |
duke@435 | 1801 | } else { |
duke@435 | 1802 | // get object class |
duke@435 | 1803 | // not a safepoint as obj null check happens earlier |
never@739 | 1804 | __ cmpptr(obj, (int32_t)NULL_WORD); |
duke@435 | 1805 | __ jcc(Assembler::equal, zero); |
never@739 | 1806 | __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
never@739 | 1807 | |
never@739 | 1808 | #ifndef _LP64 |
duke@435 | 1809 | if (k->is_loaded()) { |
duke@435 | 1810 | // See if we get an immediate positive hit |
duke@435 | 1811 | __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding()); |
duke@435 | 1812 | __ jcc(Assembler::equal, one); |
duke@435 | 1813 | if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { |
duke@435 | 1814 | // check for self |
duke@435 | 1815 | __ cmpoop(klass_RInfo, k->encoding()); |
duke@435 | 1816 | __ jcc(Assembler::equal, one); |
never@739 | 1817 | __ push(klass_RInfo); |
duke@435 | 1818 | __ pushoop(k->encoding()); |
duke@435 | 1819 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1820 | __ pop(klass_RInfo); |
never@739 | 1821 | __ pop(dst); |
duke@435 | 1822 | __ jmp(done); |
duke@435 | 1823 | } |
duke@435 | 1824 | } else { |
never@739 | 1825 | #else |
never@739 | 1826 | { // YUCK |
never@739 | 1827 | #endif // LP64 |
duke@435 | 1828 | assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); |
duke@435 | 1829 | |
duke@435 | 1830 | __ movl(dst, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); |
duke@435 | 1831 | // See if we get an immediate positive hit |
never@739 | 1832 | __ cmpptr(k_RInfo, Address(klass_RInfo, dst, Address::times_1)); |
duke@435 | 1833 | __ jcc(Assembler::equal, one); |
duke@435 | 1834 | // check for immediate negative hit |
duke@435 | 1835 | __ cmpl(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); |
duke@435 | 1836 | __ jcc(Assembler::notEqual, zero); |
duke@435 | 1837 | // check for self |
never@739 | 1838 | __ cmpptr(klass_RInfo, k_RInfo); |
duke@435 | 1839 | __ jcc(Assembler::equal, one); |
duke@435 | 1840 | |
never@739 | 1841 | __ push(klass_RInfo); |
never@739 | 1842 | __ push(k_RInfo); |
duke@435 | 1843 | __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
never@739 | 1844 | __ pop(klass_RInfo); |
never@739 | 1845 | __ pop(dst); |
duke@435 | 1846 | __ jmp(done); |
duke@435 | 1847 | } |
duke@435 | 1848 | } |
duke@435 | 1849 | __ bind(zero); |
never@739 | 1850 | __ xorptr(dst, dst); |
duke@435 | 1851 | __ jmp(done); |
duke@435 | 1852 | __ bind(one); |
never@739 | 1853 | __ movptr(dst, 1); |
duke@435 | 1854 | __ bind(done); |
duke@435 | 1855 | } else { |
duke@435 | 1856 | ShouldNotReachHere(); |
duke@435 | 1857 | } |
duke@435 | 1858 | |
duke@435 | 1859 | } |
duke@435 | 1860 | |
duke@435 | 1861 | |
duke@435 | 1862 | void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
never@739 | 1863 | if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
duke@435 | 1864 | assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
duke@435 | 1865 | assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); |
duke@435 | 1866 | assert(op->new_value()->as_register_lo() == rbx, "wrong register"); |
duke@435 | 1867 | assert(op->new_value()->as_register_hi() == rcx, "wrong register"); |
duke@435 | 1868 | Register addr = op->addr()->as_register(); |
duke@435 | 1869 | if (os::is_MP()) { |
duke@435 | 1870 | __ lock(); |
duke@435 | 1871 | } |
never@739 | 1872 | NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
never@739 | 1873 | |
never@739 | 1874 | } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { |
never@739 | 1875 | NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) |
never@739 | 1876 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
duke@435 | 1877 | Register newval = op->new_value()->as_register(); |
duke@435 | 1878 | Register cmpval = op->cmp_value()->as_register(); |
duke@435 | 1879 | assert(cmpval == rax, "wrong register"); |
duke@435 | 1880 | assert(newval != NULL, "new val must be register"); |
duke@435 | 1881 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
duke@435 | 1882 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
duke@435 | 1883 | assert(newval != addr, "new value and addr must be in different registers"); |
duke@435 | 1884 | if (os::is_MP()) { |
duke@435 | 1885 | __ lock(); |
duke@435 | 1886 | } |
never@739 | 1887 | if ( op->code() == lir_cas_obj) { |
never@739 | 1888 | __ cmpxchgptr(newval, Address(addr, 0)); |
never@739 | 1889 | } else if (op->code() == lir_cas_int) { |
never@739 | 1890 | __ cmpxchgl(newval, Address(addr, 0)); |
never@739 | 1891 | } else { |
never@739 | 1892 | LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); |
never@739 | 1893 | } |
never@739 | 1894 | #ifdef _LP64 |
never@739 | 1895 | } else if (op->code() == lir_cas_long) { |
never@739 | 1896 | Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); |
never@739 | 1897 | Register newval = op->new_value()->as_register_lo(); |
never@739 | 1898 | Register cmpval = op->cmp_value()->as_register_lo(); |
never@739 | 1899 | assert(cmpval == rax, "wrong register"); |
never@739 | 1900 | assert(newval != NULL, "new val must be register"); |
never@739 | 1901 | assert(cmpval != newval, "cmp and new values must be in different registers"); |
never@739 | 1902 | assert(cmpval != addr, "cmp and addr must be in different registers"); |
never@739 | 1903 | assert(newval != addr, "new value and addr must be in different registers"); |
never@739 | 1904 | if (os::is_MP()) { |
never@739 | 1905 | __ lock(); |
never@739 | 1906 | } |
never@739 | 1907 | __ cmpxchgq(newval, Address(addr, 0)); |
never@739 | 1908 | #endif // _LP64 |
duke@435 | 1909 | } else { |
duke@435 | 1910 | Unimplemented(); |
duke@435 | 1911 | } |
duke@435 | 1912 | } |
duke@435 | 1913 | |
duke@435 | 1914 | |
duke@435 | 1915 | void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { |
duke@435 | 1916 | Assembler::Condition acond, ncond; |
duke@435 | 1917 | switch (condition) { |
duke@435 | 1918 | case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; |
duke@435 | 1919 | case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; |
duke@435 | 1920 | case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; |
duke@435 | 1921 | case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; |
duke@435 | 1922 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; |
duke@435 | 1923 | case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; |
duke@435 | 1924 | case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; |
duke@435 | 1925 | case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; |
duke@435 | 1926 | default: ShouldNotReachHere(); |
duke@435 | 1927 | } |
duke@435 | 1928 | |
duke@435 | 1929 | if (opr1->is_cpu_register()) { |
duke@435 | 1930 | reg2reg(opr1, result); |
duke@435 | 1931 | } else if (opr1->is_stack()) { |
duke@435 | 1932 | stack2reg(opr1, result, result->type()); |
duke@435 | 1933 | } else if (opr1->is_constant()) { |
duke@435 | 1934 | const2reg(opr1, result, lir_patch_none, NULL); |
duke@435 | 1935 | } else { |
duke@435 | 1936 | ShouldNotReachHere(); |
duke@435 | 1937 | } |
duke@435 | 1938 | |
duke@435 | 1939 | if (VM_Version::supports_cmov() && !opr2->is_constant()) { |
duke@435 | 1940 | // optimized version that does not require a branch |
duke@435 | 1941 | if (opr2->is_single_cpu()) { |
duke@435 | 1942 | assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); |
never@739 | 1943 | __ cmov(ncond, result->as_register(), opr2->as_register()); |
duke@435 | 1944 | } else if (opr2->is_double_cpu()) { |
duke@435 | 1945 | assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
duke@435 | 1946 | assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); |
never@739 | 1947 | __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
never@739 | 1948 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) |
duke@435 | 1949 | } else if (opr2->is_single_stack()) { |
duke@435 | 1950 | __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 1951 | } else if (opr2->is_double_stack()) { |
never@739 | 1952 | __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
never@739 | 1953 | NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) |
duke@435 | 1954 | } else { |
duke@435 | 1955 | ShouldNotReachHere(); |
duke@435 | 1956 | } |
duke@435 | 1957 | |
duke@435 | 1958 | } else { |
duke@435 | 1959 | Label skip; |
duke@435 | 1960 | __ jcc (acond, skip); |
duke@435 | 1961 | if (opr2->is_cpu_register()) { |
duke@435 | 1962 | reg2reg(opr2, result); |
duke@435 | 1963 | } else if (opr2->is_stack()) { |
duke@435 | 1964 | stack2reg(opr2, result, result->type()); |
duke@435 | 1965 | } else if (opr2->is_constant()) { |
duke@435 | 1966 | const2reg(opr2, result, lir_patch_none, NULL); |
duke@435 | 1967 | } else { |
duke@435 | 1968 | ShouldNotReachHere(); |
duke@435 | 1969 | } |
duke@435 | 1970 | __ bind(skip); |
duke@435 | 1971 | } |
duke@435 | 1972 | } |
duke@435 | 1973 | |
duke@435 | 1974 | |
duke@435 | 1975 | void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
duke@435 | 1976 | assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); |
duke@435 | 1977 | |
duke@435 | 1978 | if (left->is_single_cpu()) { |
duke@435 | 1979 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 1980 | Register lreg = left->as_register(); |
duke@435 | 1981 | |
duke@435 | 1982 | if (right->is_single_cpu()) { |
duke@435 | 1983 | // cpu register - cpu register |
duke@435 | 1984 | Register rreg = right->as_register(); |
duke@435 | 1985 | switch (code) { |
duke@435 | 1986 | case lir_add: __ addl (lreg, rreg); break; |
duke@435 | 1987 | case lir_sub: __ subl (lreg, rreg); break; |
duke@435 | 1988 | case lir_mul: __ imull(lreg, rreg); break; |
duke@435 | 1989 | default: ShouldNotReachHere(); |
duke@435 | 1990 | } |
duke@435 | 1991 | |
duke@435 | 1992 | } else if (right->is_stack()) { |
duke@435 | 1993 | // cpu register - stack |
duke@435 | 1994 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 1995 | switch (code) { |
duke@435 | 1996 | case lir_add: __ addl(lreg, raddr); break; |
duke@435 | 1997 | case lir_sub: __ subl(lreg, raddr); break; |
duke@435 | 1998 | default: ShouldNotReachHere(); |
duke@435 | 1999 | } |
duke@435 | 2000 | |
duke@435 | 2001 | } else if (right->is_constant()) { |
duke@435 | 2002 | // cpu register - constant |
duke@435 | 2003 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2004 | switch (code) { |
duke@435 | 2005 | case lir_add: { |
duke@435 | 2006 | __ increment(lreg, c); |
duke@435 | 2007 | break; |
duke@435 | 2008 | } |
duke@435 | 2009 | case lir_sub: { |
duke@435 | 2010 | __ decrement(lreg, c); |
duke@435 | 2011 | break; |
duke@435 | 2012 | } |
duke@435 | 2013 | default: ShouldNotReachHere(); |
duke@435 | 2014 | } |
duke@435 | 2015 | |
duke@435 | 2016 | } else { |
duke@435 | 2017 | ShouldNotReachHere(); |
duke@435 | 2018 | } |
duke@435 | 2019 | |
duke@435 | 2020 | } else if (left->is_double_cpu()) { |
duke@435 | 2021 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2022 | Register lreg_lo = left->as_register_lo(); |
duke@435 | 2023 | Register lreg_hi = left->as_register_hi(); |
duke@435 | 2024 | |
duke@435 | 2025 | if (right->is_double_cpu()) { |
duke@435 | 2026 | // cpu register - cpu register |
duke@435 | 2027 | Register rreg_lo = right->as_register_lo(); |
duke@435 | 2028 | Register rreg_hi = right->as_register_hi(); |
never@739 | 2029 | NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
never@739 | 2030 | LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); |
duke@435 | 2031 | switch (code) { |
duke@435 | 2032 | case lir_add: |
never@739 | 2033 | __ addptr(lreg_lo, rreg_lo); |
never@739 | 2034 | NOT_LP64(__ adcl(lreg_hi, rreg_hi)); |
duke@435 | 2035 | break; |
duke@435 | 2036 | case lir_sub: |
never@739 | 2037 | __ subptr(lreg_lo, rreg_lo); |
never@739 | 2038 | NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); |
duke@435 | 2039 | break; |
duke@435 | 2040 | case lir_mul: |
never@739 | 2041 | #ifdef _LP64 |
never@739 | 2042 | __ imulq(lreg_lo, rreg_lo); |
never@739 | 2043 | #else |
duke@435 | 2044 | assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
duke@435 | 2045 | __ imull(lreg_hi, rreg_lo); |
duke@435 | 2046 | __ imull(rreg_hi, lreg_lo); |
duke@435 | 2047 | __ addl (rreg_hi, lreg_hi); |
duke@435 | 2048 | __ mull (rreg_lo); |
duke@435 | 2049 | __ addl (lreg_hi, rreg_hi); |
never@739 | 2050 | #endif // _LP64 |
duke@435 | 2051 | break; |
duke@435 | 2052 | default: |
duke@435 | 2053 | ShouldNotReachHere(); |
duke@435 | 2054 | } |
duke@435 | 2055 | |
duke@435 | 2056 | } else if (right->is_constant()) { |
duke@435 | 2057 | // cpu register - constant |
never@739 | 2058 | #ifdef _LP64 |
never@739 | 2059 | jlong c = right->as_constant_ptr()->as_jlong_bits(); |
never@739 | 2060 | __ movptr(r10, (intptr_t) c); |
never@739 | 2061 | switch (code) { |
never@739 | 2062 | case lir_add: |
never@739 | 2063 | __ addptr(lreg_lo, r10); |
never@739 | 2064 | break; |
never@739 | 2065 | case lir_sub: |
never@739 | 2066 | __ subptr(lreg_lo, r10); |
never@739 | 2067 | break; |
never@739 | 2068 | default: |
never@739 | 2069 | ShouldNotReachHere(); |
never@739 | 2070 | } |
never@739 | 2071 | #else |
duke@435 | 2072 | jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2073 | jint c_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2074 | switch (code) { |
duke@435 | 2075 | case lir_add: |
never@739 | 2076 | __ addptr(lreg_lo, c_lo); |
duke@435 | 2077 | __ adcl(lreg_hi, c_hi); |
duke@435 | 2078 | break; |
duke@435 | 2079 | case lir_sub: |
never@739 | 2080 | __ subptr(lreg_lo, c_lo); |
duke@435 | 2081 | __ sbbl(lreg_hi, c_hi); |
duke@435 | 2082 | break; |
duke@435 | 2083 | default: |
duke@435 | 2084 | ShouldNotReachHere(); |
duke@435 | 2085 | } |
never@739 | 2086 | #endif // _LP64 |
duke@435 | 2087 | |
duke@435 | 2088 | } else { |
duke@435 | 2089 | ShouldNotReachHere(); |
duke@435 | 2090 | } |
duke@435 | 2091 | |
duke@435 | 2092 | } else if (left->is_single_xmm()) { |
duke@435 | 2093 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2094 | XMMRegister lreg = left->as_xmm_float_reg(); |
duke@435 | 2095 | |
duke@435 | 2096 | if (right->is_single_xmm()) { |
duke@435 | 2097 | XMMRegister rreg = right->as_xmm_float_reg(); |
duke@435 | 2098 | switch (code) { |
duke@435 | 2099 | case lir_add: __ addss(lreg, rreg); break; |
duke@435 | 2100 | case lir_sub: __ subss(lreg, rreg); break; |
duke@435 | 2101 | case lir_mul_strictfp: // fall through |
duke@435 | 2102 | case lir_mul: __ mulss(lreg, rreg); break; |
duke@435 | 2103 | case lir_div_strictfp: // fall through |
duke@435 | 2104 | case lir_div: __ divss(lreg, rreg); break; |
duke@435 | 2105 | default: ShouldNotReachHere(); |
duke@435 | 2106 | } |
duke@435 | 2107 | } else { |
duke@435 | 2108 | Address raddr; |
duke@435 | 2109 | if (right->is_single_stack()) { |
duke@435 | 2110 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2111 | } else if (right->is_constant()) { |
duke@435 | 2112 | // hack for now |
duke@435 | 2113 | raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); |
duke@435 | 2114 | } else { |
duke@435 | 2115 | ShouldNotReachHere(); |
duke@435 | 2116 | } |
duke@435 | 2117 | switch (code) { |
duke@435 | 2118 | case lir_add: __ addss(lreg, raddr); break; |
duke@435 | 2119 | case lir_sub: __ subss(lreg, raddr); break; |
duke@435 | 2120 | case lir_mul_strictfp: // fall through |
duke@435 | 2121 | case lir_mul: __ mulss(lreg, raddr); break; |
duke@435 | 2122 | case lir_div_strictfp: // fall through |
duke@435 | 2123 | case lir_div: __ divss(lreg, raddr); break; |
duke@435 | 2124 | default: ShouldNotReachHere(); |
duke@435 | 2125 | } |
duke@435 | 2126 | } |
duke@435 | 2127 | |
duke@435 | 2128 | } else if (left->is_double_xmm()) { |
duke@435 | 2129 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2130 | |
duke@435 | 2131 | XMMRegister lreg = left->as_xmm_double_reg(); |
duke@435 | 2132 | if (right->is_double_xmm()) { |
duke@435 | 2133 | XMMRegister rreg = right->as_xmm_double_reg(); |
duke@435 | 2134 | switch (code) { |
duke@435 | 2135 | case lir_add: __ addsd(lreg, rreg); break; |
duke@435 | 2136 | case lir_sub: __ subsd(lreg, rreg); break; |
duke@435 | 2137 | case lir_mul_strictfp: // fall through |
duke@435 | 2138 | case lir_mul: __ mulsd(lreg, rreg); break; |
duke@435 | 2139 | case lir_div_strictfp: // fall through |
duke@435 | 2140 | case lir_div: __ divsd(lreg, rreg); break; |
duke@435 | 2141 | default: ShouldNotReachHere(); |
duke@435 | 2142 | } |
duke@435 | 2143 | } else { |
duke@435 | 2144 | Address raddr; |
duke@435 | 2145 | if (right->is_double_stack()) { |
duke@435 | 2146 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2147 | } else if (right->is_constant()) { |
duke@435 | 2148 | // hack for now |
duke@435 | 2149 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2150 | } else { |
duke@435 | 2151 | ShouldNotReachHere(); |
duke@435 | 2152 | } |
duke@435 | 2153 | switch (code) { |
duke@435 | 2154 | case lir_add: __ addsd(lreg, raddr); break; |
duke@435 | 2155 | case lir_sub: __ subsd(lreg, raddr); break; |
duke@435 | 2156 | case lir_mul_strictfp: // fall through |
duke@435 | 2157 | case lir_mul: __ mulsd(lreg, raddr); break; |
duke@435 | 2158 | case lir_div_strictfp: // fall through |
duke@435 | 2159 | case lir_div: __ divsd(lreg, raddr); break; |
duke@435 | 2160 | default: ShouldNotReachHere(); |
duke@435 | 2161 | } |
duke@435 | 2162 | } |
duke@435 | 2163 | |
duke@435 | 2164 | } else if (left->is_single_fpu()) { |
duke@435 | 2165 | assert(dest->is_single_fpu(), "fpu stack allocation required"); |
duke@435 | 2166 | |
duke@435 | 2167 | if (right->is_single_fpu()) { |
duke@435 | 2168 | arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); |
duke@435 | 2169 | |
duke@435 | 2170 | } else { |
duke@435 | 2171 | assert(left->fpu_regnr() == 0, "left must be on TOS"); |
duke@435 | 2172 | assert(dest->fpu_regnr() == 0, "dest must be on TOS"); |
duke@435 | 2173 | |
duke@435 | 2174 | Address raddr; |
duke@435 | 2175 | if (right->is_single_stack()) { |
duke@435 | 2176 | raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2177 | } else if (right->is_constant()) { |
duke@435 | 2178 | address const_addr = float_constant(right->as_jfloat()); |
duke@435 | 2179 | assert(const_addr != NULL, "incorrect float/double constant maintainance"); |
duke@435 | 2180 | // hack for now |
duke@435 | 2181 | raddr = __ as_Address(InternalAddress(const_addr)); |
duke@435 | 2182 | } else { |
duke@435 | 2183 | ShouldNotReachHere(); |
duke@435 | 2184 | } |
duke@435 | 2185 | |
duke@435 | 2186 | switch (code) { |
duke@435 | 2187 | case lir_add: __ fadd_s(raddr); break; |
duke@435 | 2188 | case lir_sub: __ fsub_s(raddr); break; |
duke@435 | 2189 | case lir_mul_strictfp: // fall through |
duke@435 | 2190 | case lir_mul: __ fmul_s(raddr); break; |
duke@435 | 2191 | case lir_div_strictfp: // fall through |
duke@435 | 2192 | case lir_div: __ fdiv_s(raddr); break; |
duke@435 | 2193 | default: ShouldNotReachHere(); |
duke@435 | 2194 | } |
duke@435 | 2195 | } |
duke@435 | 2196 | |
duke@435 | 2197 | } else if (left->is_double_fpu()) { |
duke@435 | 2198 | assert(dest->is_double_fpu(), "fpu stack allocation required"); |
duke@435 | 2199 | |
duke@435 | 2200 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2201 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2202 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); |
duke@435 | 2203 | __ fmulp(left->fpu_regnrLo() + 1); |
duke@435 | 2204 | } |
duke@435 | 2205 | |
duke@435 | 2206 | if (right->is_double_fpu()) { |
duke@435 | 2207 | arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); |
duke@435 | 2208 | |
duke@435 | 2209 | } else { |
duke@435 | 2210 | assert(left->fpu_regnrLo() == 0, "left must be on TOS"); |
duke@435 | 2211 | assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); |
duke@435 | 2212 | |
duke@435 | 2213 | Address raddr; |
duke@435 | 2214 | if (right->is_double_stack()) { |
duke@435 | 2215 | raddr = frame_map()->address_for_slot(right->double_stack_ix()); |
duke@435 | 2216 | } else if (right->is_constant()) { |
duke@435 | 2217 | // hack for now |
duke@435 | 2218 | raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); |
duke@435 | 2219 | } else { |
duke@435 | 2220 | ShouldNotReachHere(); |
duke@435 | 2221 | } |
duke@435 | 2222 | |
duke@435 | 2223 | switch (code) { |
duke@435 | 2224 | case lir_add: __ fadd_d(raddr); break; |
duke@435 | 2225 | case lir_sub: __ fsub_d(raddr); break; |
duke@435 | 2226 | case lir_mul_strictfp: // fall through |
duke@435 | 2227 | case lir_mul: __ fmul_d(raddr); break; |
duke@435 | 2228 | case lir_div_strictfp: // fall through |
duke@435 | 2229 | case lir_div: __ fdiv_d(raddr); break; |
duke@435 | 2230 | default: ShouldNotReachHere(); |
duke@435 | 2231 | } |
duke@435 | 2232 | } |
duke@435 | 2233 | |
duke@435 | 2234 | if (code == lir_mul_strictfp || code == lir_div_strictfp) { |
duke@435 | 2235 | // Double values require special handling for strictfp mul/div on x86 |
duke@435 | 2236 | __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); |
duke@435 | 2237 | __ fmulp(dest->fpu_regnrLo() + 1); |
duke@435 | 2238 | } |
duke@435 | 2239 | |
duke@435 | 2240 | } else if (left->is_single_stack() || left->is_address()) { |
duke@435 | 2241 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2242 | |
duke@435 | 2243 | Address laddr; |
duke@435 | 2244 | if (left->is_single_stack()) { |
duke@435 | 2245 | laddr = frame_map()->address_for_slot(left->single_stack_ix()); |
duke@435 | 2246 | } else if (left->is_address()) { |
duke@435 | 2247 | laddr = as_Address(left->as_address_ptr()); |
duke@435 | 2248 | } else { |
duke@435 | 2249 | ShouldNotReachHere(); |
duke@435 | 2250 | } |
duke@435 | 2251 | |
duke@435 | 2252 | if (right->is_single_cpu()) { |
duke@435 | 2253 | Register rreg = right->as_register(); |
duke@435 | 2254 | switch (code) { |
duke@435 | 2255 | case lir_add: __ addl(laddr, rreg); break; |
duke@435 | 2256 | case lir_sub: __ subl(laddr, rreg); break; |
duke@435 | 2257 | default: ShouldNotReachHere(); |
duke@435 | 2258 | } |
duke@435 | 2259 | } else if (right->is_constant()) { |
duke@435 | 2260 | jint c = right->as_constant_ptr()->as_jint(); |
duke@435 | 2261 | switch (code) { |
duke@435 | 2262 | case lir_add: { |
never@739 | 2263 | __ incrementl(laddr, c); |
duke@435 | 2264 | break; |
duke@435 | 2265 | } |
duke@435 | 2266 | case lir_sub: { |
never@739 | 2267 | __ decrementl(laddr, c); |
duke@435 | 2268 | break; |
duke@435 | 2269 | } |
duke@435 | 2270 | default: ShouldNotReachHere(); |
duke@435 | 2271 | } |
duke@435 | 2272 | } else { |
duke@435 | 2273 | ShouldNotReachHere(); |
duke@435 | 2274 | } |
duke@435 | 2275 | |
duke@435 | 2276 | } else { |
duke@435 | 2277 | ShouldNotReachHere(); |
duke@435 | 2278 | } |
duke@435 | 2279 | } |
duke@435 | 2280 | |
duke@435 | 2281 | void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { |
duke@435 | 2282 | assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); |
duke@435 | 2283 | assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); |
duke@435 | 2284 | assert(left_index == 0 || right_index == 0, "either must be on top of stack"); |
duke@435 | 2285 | |
duke@435 | 2286 | bool left_is_tos = (left_index == 0); |
duke@435 | 2287 | bool dest_is_tos = (dest_index == 0); |
duke@435 | 2288 | int non_tos_index = (left_is_tos ? right_index : left_index); |
duke@435 | 2289 | |
duke@435 | 2290 | switch (code) { |
duke@435 | 2291 | case lir_add: |
duke@435 | 2292 | if (pop_fpu_stack) __ faddp(non_tos_index); |
duke@435 | 2293 | else if (dest_is_tos) __ fadd (non_tos_index); |
duke@435 | 2294 | else __ fadda(non_tos_index); |
duke@435 | 2295 | break; |
duke@435 | 2296 | |
duke@435 | 2297 | case lir_sub: |
duke@435 | 2298 | if (left_is_tos) { |
duke@435 | 2299 | if (pop_fpu_stack) __ fsubrp(non_tos_index); |
duke@435 | 2300 | else if (dest_is_tos) __ fsub (non_tos_index); |
duke@435 | 2301 | else __ fsubra(non_tos_index); |
duke@435 | 2302 | } else { |
duke@435 | 2303 | if (pop_fpu_stack) __ fsubp (non_tos_index); |
duke@435 | 2304 | else if (dest_is_tos) __ fsubr (non_tos_index); |
duke@435 | 2305 | else __ fsuba (non_tos_index); |
duke@435 | 2306 | } |
duke@435 | 2307 | break; |
duke@435 | 2308 | |
duke@435 | 2309 | case lir_mul_strictfp: // fall through |
duke@435 | 2310 | case lir_mul: |
duke@435 | 2311 | if (pop_fpu_stack) __ fmulp(non_tos_index); |
duke@435 | 2312 | else if (dest_is_tos) __ fmul (non_tos_index); |
duke@435 | 2313 | else __ fmula(non_tos_index); |
duke@435 | 2314 | break; |
duke@435 | 2315 | |
duke@435 | 2316 | case lir_div_strictfp: // fall through |
duke@435 | 2317 | case lir_div: |
duke@435 | 2318 | if (left_is_tos) { |
duke@435 | 2319 | if (pop_fpu_stack) __ fdivrp(non_tos_index); |
duke@435 | 2320 | else if (dest_is_tos) __ fdiv (non_tos_index); |
duke@435 | 2321 | else __ fdivra(non_tos_index); |
duke@435 | 2322 | } else { |
duke@435 | 2323 | if (pop_fpu_stack) __ fdivp (non_tos_index); |
duke@435 | 2324 | else if (dest_is_tos) __ fdivr (non_tos_index); |
duke@435 | 2325 | else __ fdiva (non_tos_index); |
duke@435 | 2326 | } |
duke@435 | 2327 | break; |
duke@435 | 2328 | |
duke@435 | 2329 | case lir_rem: |
duke@435 | 2330 | assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); |
duke@435 | 2331 | __ fremr(noreg); |
duke@435 | 2332 | break; |
duke@435 | 2333 | |
duke@435 | 2334 | default: |
duke@435 | 2335 | ShouldNotReachHere(); |
duke@435 | 2336 | } |
duke@435 | 2337 | } |
duke@435 | 2338 | |
duke@435 | 2339 | |
duke@435 | 2340 | void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { |
duke@435 | 2341 | if (value->is_double_xmm()) { |
duke@435 | 2342 | switch(code) { |
duke@435 | 2343 | case lir_abs : |
duke@435 | 2344 | { |
duke@435 | 2345 | if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { |
duke@435 | 2346 | __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); |
duke@435 | 2347 | } |
duke@435 | 2348 | __ andpd(dest->as_xmm_double_reg(), |
duke@435 | 2349 | ExternalAddress((address)double_signmask_pool)); |
duke@435 | 2350 | } |
duke@435 | 2351 | break; |
duke@435 | 2352 | |
duke@435 | 2353 | case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; |
duke@435 | 2354 | // all other intrinsics are not available in the SSE instruction set, so FPU is used |
duke@435 | 2355 | default : ShouldNotReachHere(); |
duke@435 | 2356 | } |
duke@435 | 2357 | |
duke@435 | 2358 | } else if (value->is_double_fpu()) { |
duke@435 | 2359 | assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); |
duke@435 | 2360 | switch(code) { |
duke@435 | 2361 | case lir_log : __ flog() ; break; |
duke@435 | 2362 | case lir_log10 : __ flog10() ; break; |
duke@435 | 2363 | case lir_abs : __ fabs() ; break; |
duke@435 | 2364 | case lir_sqrt : __ fsqrt(); break; |
duke@435 | 2365 | case lir_sin : |
duke@435 | 2366 | // Should consider not saving rbx, if not necessary |
duke@435 | 2367 | __ trigfunc('s', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2368 | break; |
duke@435 | 2369 | case lir_cos : |
duke@435 | 2370 | // Should consider not saving rbx, if not necessary |
duke@435 | 2371 | assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); |
duke@435 | 2372 | __ trigfunc('c', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2373 | break; |
duke@435 | 2374 | case lir_tan : |
duke@435 | 2375 | // Should consider not saving rbx, if not necessary |
duke@435 | 2376 | __ trigfunc('t', op->as_Op2()->fpu_stack_size()); |
duke@435 | 2377 | break; |
duke@435 | 2378 | default : ShouldNotReachHere(); |
duke@435 | 2379 | } |
duke@435 | 2380 | } else { |
duke@435 | 2381 | Unimplemented(); |
duke@435 | 2382 | } |
duke@435 | 2383 | } |
duke@435 | 2384 | |
duke@435 | 2385 | void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
duke@435 | 2386 | // assert(left->destroys_register(), "check"); |
duke@435 | 2387 | if (left->is_single_cpu()) { |
duke@435 | 2388 | Register reg = left->as_register(); |
duke@435 | 2389 | if (right->is_constant()) { |
duke@435 | 2390 | int val = right->as_constant_ptr()->as_jint(); |
duke@435 | 2391 | switch (code) { |
duke@435 | 2392 | case lir_logic_and: __ andl (reg, val); break; |
duke@435 | 2393 | case lir_logic_or: __ orl (reg, val); break; |
duke@435 | 2394 | case lir_logic_xor: __ xorl (reg, val); break; |
duke@435 | 2395 | default: ShouldNotReachHere(); |
duke@435 | 2396 | } |
duke@435 | 2397 | } else if (right->is_stack()) { |
duke@435 | 2398 | // added support for stack operands |
duke@435 | 2399 | Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); |
duke@435 | 2400 | switch (code) { |
duke@435 | 2401 | case lir_logic_and: __ andl (reg, raddr); break; |
duke@435 | 2402 | case lir_logic_or: __ orl (reg, raddr); break; |
duke@435 | 2403 | case lir_logic_xor: __ xorl (reg, raddr); break; |
duke@435 | 2404 | default: ShouldNotReachHere(); |
duke@435 | 2405 | } |
duke@435 | 2406 | } else { |
duke@435 | 2407 | Register rright = right->as_register(); |
duke@435 | 2408 | switch (code) { |
never@739 | 2409 | case lir_logic_and: __ andptr (reg, rright); break; |
never@739 | 2410 | case lir_logic_or : __ orptr (reg, rright); break; |
never@739 | 2411 | case lir_logic_xor: __ xorptr (reg, rright); break; |
duke@435 | 2412 | default: ShouldNotReachHere(); |
duke@435 | 2413 | } |
duke@435 | 2414 | } |
duke@435 | 2415 | move_regs(reg, dst->as_register()); |
duke@435 | 2416 | } else { |
duke@435 | 2417 | Register l_lo = left->as_register_lo(); |
duke@435 | 2418 | Register l_hi = left->as_register_hi(); |
duke@435 | 2419 | if (right->is_constant()) { |
never@739 | 2420 | #ifdef _LP64 |
never@739 | 2421 | __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); |
never@739 | 2422 | switch (code) { |
never@739 | 2423 | case lir_logic_and: |
never@739 | 2424 | __ andq(l_lo, rscratch1); |
never@739 | 2425 | break; |
never@739 | 2426 | case lir_logic_or: |
never@739 | 2427 | __ orq(l_lo, rscratch1); |
never@739 | 2428 | break; |
never@739 | 2429 | case lir_logic_xor: |
never@739 | 2430 | __ xorq(l_lo, rscratch1); |
never@739 | 2431 | break; |
never@739 | 2432 | default: ShouldNotReachHere(); |
never@739 | 2433 | } |
never@739 | 2434 | #else |
duke@435 | 2435 | int r_lo = right->as_constant_ptr()->as_jint_lo(); |
duke@435 | 2436 | int r_hi = right->as_constant_ptr()->as_jint_hi(); |
duke@435 | 2437 | switch (code) { |
duke@435 | 2438 | case lir_logic_and: |
duke@435 | 2439 | __ andl(l_lo, r_lo); |
duke@435 | 2440 | __ andl(l_hi, r_hi); |
duke@435 | 2441 | break; |
duke@435 | 2442 | case lir_logic_or: |
duke@435 | 2443 | __ orl(l_lo, r_lo); |
duke@435 | 2444 | __ orl(l_hi, r_hi); |
duke@435 | 2445 | break; |
duke@435 | 2446 | case lir_logic_xor: |
duke@435 | 2447 | __ xorl(l_lo, r_lo); |
duke@435 | 2448 | __ xorl(l_hi, r_hi); |
duke@435 | 2449 | break; |
duke@435 | 2450 | default: ShouldNotReachHere(); |
duke@435 | 2451 | } |
never@739 | 2452 | #endif // _LP64 |
duke@435 | 2453 | } else { |
duke@435 | 2454 | Register r_lo = right->as_register_lo(); |
duke@435 | 2455 | Register r_hi = right->as_register_hi(); |
duke@435 | 2456 | assert(l_lo != r_hi, "overwriting registers"); |
duke@435 | 2457 | switch (code) { |
duke@435 | 2458 | case lir_logic_and: |
never@739 | 2459 | __ andptr(l_lo, r_lo); |
never@739 | 2460 | NOT_LP64(__ andptr(l_hi, r_hi);) |
duke@435 | 2461 | break; |
duke@435 | 2462 | case lir_logic_or: |
never@739 | 2463 | __ orptr(l_lo, r_lo); |
never@739 | 2464 | NOT_LP64(__ orptr(l_hi, r_hi);) |
duke@435 | 2465 | break; |
duke@435 | 2466 | case lir_logic_xor: |
never@739 | 2467 | __ xorptr(l_lo, r_lo); |
never@739 | 2468 | NOT_LP64(__ xorptr(l_hi, r_hi);) |
duke@435 | 2469 | break; |
duke@435 | 2470 | default: ShouldNotReachHere(); |
duke@435 | 2471 | } |
duke@435 | 2472 | } |
duke@435 | 2473 | |
duke@435 | 2474 | Register dst_lo = dst->as_register_lo(); |
duke@435 | 2475 | Register dst_hi = dst->as_register_hi(); |
duke@435 | 2476 | |
never@739 | 2477 | #ifdef _LP64 |
never@739 | 2478 | move_regs(l_lo, dst_lo); |
never@739 | 2479 | #else |
duke@435 | 2480 | if (dst_lo == l_hi) { |
duke@435 | 2481 | assert(dst_hi != l_lo, "overwriting registers"); |
duke@435 | 2482 | move_regs(l_hi, dst_hi); |
duke@435 | 2483 | move_regs(l_lo, dst_lo); |
duke@435 | 2484 | } else { |
duke@435 | 2485 | assert(dst_lo != l_hi, "overwriting registers"); |
duke@435 | 2486 | move_regs(l_lo, dst_lo); |
duke@435 | 2487 | move_regs(l_hi, dst_hi); |
duke@435 | 2488 | } |
never@739 | 2489 | #endif // _LP64 |
duke@435 | 2490 | } |
duke@435 | 2491 | } |
duke@435 | 2492 | |
duke@435 | 2493 | |
duke@435 | 2494 | // we assume that rax, and rdx can be overwritten |
duke@435 | 2495 | void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { |
duke@435 | 2496 | |
duke@435 | 2497 | assert(left->is_single_cpu(), "left must be register"); |
duke@435 | 2498 | assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); |
duke@435 | 2499 | assert(result->is_single_cpu(), "result must be register"); |
duke@435 | 2500 | |
duke@435 | 2501 | // assert(left->destroys_register(), "check"); |
duke@435 | 2502 | // assert(right->destroys_register(), "check"); |
duke@435 | 2503 | |
duke@435 | 2504 | Register lreg = left->as_register(); |
duke@435 | 2505 | Register dreg = result->as_register(); |
duke@435 | 2506 | |
duke@435 | 2507 | if (right->is_constant()) { |
duke@435 | 2508 | int divisor = right->as_constant_ptr()->as_jint(); |
duke@435 | 2509 | assert(divisor > 0 && is_power_of_2(divisor), "must be"); |
duke@435 | 2510 | if (code == lir_idiv) { |
duke@435 | 2511 | assert(lreg == rax, "must be rax,"); |
duke@435 | 2512 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2513 | __ cdql(); // sign extend into rdx:rax |
duke@435 | 2514 | if (divisor == 2) { |
duke@435 | 2515 | __ subl(lreg, rdx); |
duke@435 | 2516 | } else { |
duke@435 | 2517 | __ andl(rdx, divisor - 1); |
duke@435 | 2518 | __ addl(lreg, rdx); |
duke@435 | 2519 | } |
duke@435 | 2520 | __ sarl(lreg, log2_intptr(divisor)); |
duke@435 | 2521 | move_regs(lreg, dreg); |
duke@435 | 2522 | } else if (code == lir_irem) { |
duke@435 | 2523 | Label done; |
never@739 | 2524 | __ mov(dreg, lreg); |
duke@435 | 2525 | __ andl(dreg, 0x80000000 | (divisor - 1)); |
duke@435 | 2526 | __ jcc(Assembler::positive, done); |
duke@435 | 2527 | __ decrement(dreg); |
duke@435 | 2528 | __ orl(dreg, ~(divisor - 1)); |
duke@435 | 2529 | __ increment(dreg); |
duke@435 | 2530 | __ bind(done); |
duke@435 | 2531 | } else { |
duke@435 | 2532 | ShouldNotReachHere(); |
duke@435 | 2533 | } |
duke@435 | 2534 | } else { |
duke@435 | 2535 | Register rreg = right->as_register(); |
duke@435 | 2536 | assert(lreg == rax, "left register must be rax,"); |
duke@435 | 2537 | assert(rreg != rdx, "right register must not be rdx"); |
duke@435 | 2538 | assert(temp->as_register() == rdx, "tmp register must be rdx"); |
duke@435 | 2539 | |
duke@435 | 2540 | move_regs(lreg, rax); |
duke@435 | 2541 | |
duke@435 | 2542 | int idivl_offset = __ corrected_idivl(rreg); |
duke@435 | 2543 | add_debug_info_for_div0(idivl_offset, info); |
duke@435 | 2544 | if (code == lir_irem) { |
duke@435 | 2545 | move_regs(rdx, dreg); // result is in rdx |
duke@435 | 2546 | } else { |
duke@435 | 2547 | move_regs(rax, dreg); |
duke@435 | 2548 | } |
duke@435 | 2549 | } |
duke@435 | 2550 | } |
duke@435 | 2551 | |
duke@435 | 2552 | |
duke@435 | 2553 | void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
duke@435 | 2554 | if (opr1->is_single_cpu()) { |
duke@435 | 2555 | Register reg1 = opr1->as_register(); |
duke@435 | 2556 | if (opr2->is_single_cpu()) { |
duke@435 | 2557 | // cpu register - cpu register |
never@739 | 2558 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2559 | __ cmpptr(reg1, opr2->as_register()); |
never@739 | 2560 | } else { |
never@739 | 2561 | assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
never@739 | 2562 | __ cmpl(reg1, opr2->as_register()); |
never@739 | 2563 | } |
duke@435 | 2564 | } else if (opr2->is_stack()) { |
duke@435 | 2565 | // cpu register - stack |
never@739 | 2566 | if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
never@739 | 2567 | __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2568 | } else { |
never@739 | 2569 | __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
never@739 | 2570 | } |
duke@435 | 2571 | } else if (opr2->is_constant()) { |
duke@435 | 2572 | // cpu register - constant |
duke@435 | 2573 | LIR_Const* c = opr2->as_constant_ptr(); |
duke@435 | 2574 | if (c->type() == T_INT) { |
duke@435 | 2575 | __ cmpl(reg1, c->as_jint()); |
never@739 | 2576 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2577 | // In 64bit oops are single register |
duke@435 | 2578 | jobject o = c->as_jobject(); |
duke@435 | 2579 | if (o == NULL) { |
never@739 | 2580 | __ cmpptr(reg1, (int32_t)NULL_WORD); |
duke@435 | 2581 | } else { |
never@739 | 2582 | #ifdef _LP64 |
never@739 | 2583 | __ movoop(rscratch1, o); |
never@739 | 2584 | __ cmpptr(reg1, rscratch1); |
never@739 | 2585 | #else |
duke@435 | 2586 | __ cmpoop(reg1, c->as_jobject()); |
never@739 | 2587 | #endif // _LP64 |
duke@435 | 2588 | } |
duke@435 | 2589 | } else { |
duke@435 | 2590 | ShouldNotReachHere(); |
duke@435 | 2591 | } |
duke@435 | 2592 | // cpu register - address |
duke@435 | 2593 | } else if (opr2->is_address()) { |
duke@435 | 2594 | if (op->info() != NULL) { |
duke@435 | 2595 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2596 | } |
duke@435 | 2597 | __ cmpl(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2598 | } else { |
duke@435 | 2599 | ShouldNotReachHere(); |
duke@435 | 2600 | } |
duke@435 | 2601 | |
duke@435 | 2602 | } else if(opr1->is_double_cpu()) { |
duke@435 | 2603 | Register xlo = opr1->as_register_lo(); |
duke@435 | 2604 | Register xhi = opr1->as_register_hi(); |
duke@435 | 2605 | if (opr2->is_double_cpu()) { |
never@739 | 2606 | #ifdef _LP64 |
never@739 | 2607 | __ cmpptr(xlo, opr2->as_register_lo()); |
never@739 | 2608 | #else |
duke@435 | 2609 | // cpu register - cpu register |
duke@435 | 2610 | Register ylo = opr2->as_register_lo(); |
duke@435 | 2611 | Register yhi = opr2->as_register_hi(); |
duke@435 | 2612 | __ subl(xlo, ylo); |
duke@435 | 2613 | __ sbbl(xhi, yhi); |
duke@435 | 2614 | if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
duke@435 | 2615 | __ orl(xhi, xlo); |
duke@435 | 2616 | } |
never@739 | 2617 | #endif // _LP64 |
duke@435 | 2618 | } else if (opr2->is_constant()) { |
duke@435 | 2619 | // cpu register - constant 0 |
duke@435 | 2620 | assert(opr2->as_jlong() == (jlong)0, "only handles zero"); |
never@739 | 2621 | #ifdef _LP64 |
never@739 | 2622 | __ cmpptr(xlo, (int32_t)opr2->as_jlong()); |
never@739 | 2623 | #else |
duke@435 | 2624 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
duke@435 | 2625 | __ orl(xhi, xlo); |
never@739 | 2626 | #endif // _LP64 |
duke@435 | 2627 | } else { |
duke@435 | 2628 | ShouldNotReachHere(); |
duke@435 | 2629 | } |
duke@435 | 2630 | |
duke@435 | 2631 | } else if (opr1->is_single_xmm()) { |
duke@435 | 2632 | XMMRegister reg1 = opr1->as_xmm_float_reg(); |
duke@435 | 2633 | if (opr2->is_single_xmm()) { |
duke@435 | 2634 | // xmm register - xmm register |
duke@435 | 2635 | __ ucomiss(reg1, opr2->as_xmm_float_reg()); |
duke@435 | 2636 | } else if (opr2->is_stack()) { |
duke@435 | 2637 | // xmm register - stack |
duke@435 | 2638 | __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); |
duke@435 | 2639 | } else if (opr2->is_constant()) { |
duke@435 | 2640 | // xmm register - constant |
duke@435 | 2641 | __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); |
duke@435 | 2642 | } else if (opr2->is_address()) { |
duke@435 | 2643 | // xmm register - address |
duke@435 | 2644 | if (op->info() != NULL) { |
duke@435 | 2645 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2646 | } |
duke@435 | 2647 | __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); |
duke@435 | 2648 | } else { |
duke@435 | 2649 | ShouldNotReachHere(); |
duke@435 | 2650 | } |
duke@435 | 2651 | |
duke@435 | 2652 | } else if (opr1->is_double_xmm()) { |
duke@435 | 2653 | XMMRegister reg1 = opr1->as_xmm_double_reg(); |
duke@435 | 2654 | if (opr2->is_double_xmm()) { |
duke@435 | 2655 | // xmm register - xmm register |
duke@435 | 2656 | __ ucomisd(reg1, opr2->as_xmm_double_reg()); |
duke@435 | 2657 | } else if (opr2->is_stack()) { |
duke@435 | 2658 | // xmm register - stack |
duke@435 | 2659 | __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); |
duke@435 | 2660 | } else if (opr2->is_constant()) { |
duke@435 | 2661 | // xmm register - constant |
duke@435 | 2662 | __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); |
duke@435 | 2663 | } else if (opr2->is_address()) { |
duke@435 | 2664 | // xmm register - address |
duke@435 | 2665 | if (op->info() != NULL) { |
duke@435 | 2666 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2667 | } |
duke@435 | 2668 | __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); |
duke@435 | 2669 | } else { |
duke@435 | 2670 | ShouldNotReachHere(); |
duke@435 | 2671 | } |
duke@435 | 2672 | |
duke@435 | 2673 | } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { |
duke@435 | 2674 | assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); |
duke@435 | 2675 | assert(opr2->is_fpu_register(), "both must be registers"); |
duke@435 | 2676 | __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2677 | |
duke@435 | 2678 | } else if (opr1->is_address() && opr2->is_constant()) { |
never@739 | 2679 | LIR_Const* c = opr2->as_constant_ptr(); |
never@739 | 2680 | #ifdef _LP64 |
never@739 | 2681 | if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2682 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); |
never@739 | 2683 | __ movoop(rscratch1, c->as_jobject()); |
never@739 | 2684 | } |
never@739 | 2685 | #endif // LP64 |
duke@435 | 2686 | if (op->info() != NULL) { |
duke@435 | 2687 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2688 | } |
duke@435 | 2689 | // special case: address - constant |
duke@435 | 2690 | LIR_Address* addr = opr1->as_address_ptr(); |
duke@435 | 2691 | if (c->type() == T_INT) { |
duke@435 | 2692 | __ cmpl(as_Address(addr), c->as_jint()); |
never@739 | 2693 | } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
never@739 | 2694 | #ifdef _LP64 |
never@739 | 2695 | // %%% Make this explode if addr isn't reachable until we figure out a |
never@739 | 2696 | // better strategy by giving noreg as the temp for as_Address |
never@739 | 2697 | __ cmpptr(rscratch1, as_Address(addr, noreg)); |
never@739 | 2698 | #else |
duke@435 | 2699 | __ cmpoop(as_Address(addr), c->as_jobject()); |
never@739 | 2700 | #endif // _LP64 |
duke@435 | 2701 | } else { |
duke@435 | 2702 | ShouldNotReachHere(); |
duke@435 | 2703 | } |
duke@435 | 2704 | |
duke@435 | 2705 | } else { |
duke@435 | 2706 | ShouldNotReachHere(); |
duke@435 | 2707 | } |
duke@435 | 2708 | } |
duke@435 | 2709 | |
duke@435 | 2710 | void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { |
duke@435 | 2711 | if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
duke@435 | 2712 | if (left->is_single_xmm()) { |
duke@435 | 2713 | assert(right->is_single_xmm(), "must match"); |
duke@435 | 2714 | __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2715 | } else if (left->is_double_xmm()) { |
duke@435 | 2716 | assert(right->is_double_xmm(), "must match"); |
duke@435 | 2717 | __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); |
duke@435 | 2718 | |
duke@435 | 2719 | } else { |
duke@435 | 2720 | assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); |
duke@435 | 2721 | assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); |
duke@435 | 2722 | |
duke@435 | 2723 | assert(left->fpu() == 0, "left must be on TOS"); |
duke@435 | 2724 | __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), |
duke@435 | 2725 | op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); |
duke@435 | 2726 | } |
duke@435 | 2727 | } else { |
duke@435 | 2728 | assert(code == lir_cmp_l2i, "check"); |
never@739 | 2729 | #ifdef _LP64 |
never@739 | 2730 | Register dest = dst->as_register(); |
never@739 | 2731 | __ xorptr(dest, dest); |
never@739 | 2732 | Label high, done; |
never@739 | 2733 | __ cmpptr(left->as_register_lo(), right->as_register_lo()); |
never@739 | 2734 | __ jcc(Assembler::equal, done); |
never@739 | 2735 | __ jcc(Assembler::greater, high); |
never@739 | 2736 | __ decrement(dest); |
never@739 | 2737 | __ jmp(done); |
never@739 | 2738 | __ bind(high); |
never@739 | 2739 | __ increment(dest); |
never@739 | 2740 | |
never@739 | 2741 | __ bind(done); |
never@739 | 2742 | |
never@739 | 2743 | #else |
duke@435 | 2744 | __ lcmp2int(left->as_register_hi(), |
duke@435 | 2745 | left->as_register_lo(), |
duke@435 | 2746 | right->as_register_hi(), |
duke@435 | 2747 | right->as_register_lo()); |
duke@435 | 2748 | move_regs(left->as_register_hi(), dst->as_register()); |
never@739 | 2749 | #endif // _LP64 |
duke@435 | 2750 | } |
duke@435 | 2751 | } |
duke@435 | 2752 | |
duke@435 | 2753 | |
duke@435 | 2754 | void LIR_Assembler::align_call(LIR_Code code) { |
duke@435 | 2755 | if (os::is_MP()) { |
duke@435 | 2756 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2757 | int offset = __ offset(); |
duke@435 | 2758 | switch (code) { |
duke@435 | 2759 | case lir_static_call: |
duke@435 | 2760 | case lir_optvirtual_call: |
duke@435 | 2761 | offset += NativeCall::displacement_offset; |
duke@435 | 2762 | break; |
duke@435 | 2763 | case lir_icvirtual_call: |
duke@435 | 2764 | offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; |
duke@435 | 2765 | break; |
duke@435 | 2766 | case lir_virtual_call: // currently, sparc-specific for niagara |
duke@435 | 2767 | default: ShouldNotReachHere(); |
duke@435 | 2768 | } |
duke@435 | 2769 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2770 | __ nop(); |
duke@435 | 2771 | } |
duke@435 | 2772 | } |
duke@435 | 2773 | } |
duke@435 | 2774 | |
duke@435 | 2775 | |
duke@435 | 2776 | void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { |
duke@435 | 2777 | assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2778 | "must be aligned"); |
duke@435 | 2779 | __ call(AddressLiteral(entry, rtype)); |
duke@435 | 2780 | add_call_info(code_offset(), info); |
duke@435 | 2781 | } |
duke@435 | 2782 | |
duke@435 | 2783 | |
duke@435 | 2784 | void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { |
duke@435 | 2785 | RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
duke@435 | 2786 | __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); |
duke@435 | 2787 | assert(!os::is_MP() || |
duke@435 | 2788 | (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
duke@435 | 2789 | "must be aligned"); |
duke@435 | 2790 | __ call(AddressLiteral(entry, rh)); |
duke@435 | 2791 | add_call_info(code_offset(), info); |
duke@435 | 2792 | } |
duke@435 | 2793 | |
duke@435 | 2794 | |
duke@435 | 2795 | /* Currently, vtable-dispatch is only enabled for sparc platforms */ |
duke@435 | 2796 | void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { |
duke@435 | 2797 | ShouldNotReachHere(); |
duke@435 | 2798 | } |
duke@435 | 2799 | |
duke@435 | 2800 | void LIR_Assembler::emit_static_call_stub() { |
duke@435 | 2801 | address call_pc = __ pc(); |
duke@435 | 2802 | address stub = __ start_a_stub(call_stub_size); |
duke@435 | 2803 | if (stub == NULL) { |
duke@435 | 2804 | bailout("static call stub overflow"); |
duke@435 | 2805 | return; |
duke@435 | 2806 | } |
duke@435 | 2807 | |
duke@435 | 2808 | int start = __ offset(); |
duke@435 | 2809 | if (os::is_MP()) { |
duke@435 | 2810 | // make sure that the displacement word of the call ends up word aligned |
duke@435 | 2811 | int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; |
duke@435 | 2812 | while (offset++ % BytesPerWord != 0) { |
duke@435 | 2813 | __ nop(); |
duke@435 | 2814 | } |
duke@435 | 2815 | } |
duke@435 | 2816 | __ relocate(static_stub_Relocation::spec(call_pc)); |
duke@435 | 2817 | __ movoop(rbx, (jobject)NULL); |
duke@435 | 2818 | // must be set to -1 at code generation time |
duke@435 | 2819 | assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); |
never@739 | 2820 | // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
never@739 | 2821 | __ jump(RuntimeAddress(__ pc())); |
duke@435 | 2822 | |
duke@435 | 2823 | assert(__ offset() - start <= call_stub_size, "stub too big") |
duke@435 | 2824 | __ end_a_stub(); |
duke@435 | 2825 | } |
duke@435 | 2826 | |
duke@435 | 2827 | |
duke@435 | 2828 | void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { |
duke@435 | 2829 | assert(exceptionOop->as_register() == rax, "must match"); |
duke@435 | 2830 | assert(unwind || exceptionPC->as_register() == rdx, "must match"); |
duke@435 | 2831 | |
duke@435 | 2832 | // exception object is not added to oop map by LinearScan |
duke@435 | 2833 | // (LinearScan assumes that no oops are in fixed registers) |
duke@435 | 2834 | info->add_register_oop(exceptionOop); |
duke@435 | 2835 | Runtime1::StubID unwind_id; |
duke@435 | 2836 | |
duke@435 | 2837 | if (!unwind) { |
duke@435 | 2838 | // get current pc information |
duke@435 | 2839 | // pc is only needed if the method has an exception handler, the unwind code does not need it. |
duke@435 | 2840 | int pc_for_athrow_offset = __ offset(); |
duke@435 | 2841 | InternalAddress pc_for_athrow(__ pc()); |
duke@435 | 2842 | __ lea(exceptionPC->as_register(), pc_for_athrow); |
duke@435 | 2843 | add_call_info(pc_for_athrow_offset, info); // for exception handler |
duke@435 | 2844 | |
duke@435 | 2845 | __ verify_not_null_oop(rax); |
duke@435 | 2846 | // search an exception handler (rax: exception oop, rdx: throwing pc) |
duke@435 | 2847 | if (compilation()->has_fpu_code()) { |
duke@435 | 2848 | unwind_id = Runtime1::handle_exception_id; |
duke@435 | 2849 | } else { |
duke@435 | 2850 | unwind_id = Runtime1::handle_exception_nofpu_id; |
duke@435 | 2851 | } |
duke@435 | 2852 | } else { |
duke@435 | 2853 | unwind_id = Runtime1::unwind_exception_id; |
duke@435 | 2854 | } |
duke@435 | 2855 | __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
duke@435 | 2856 | |
duke@435 | 2857 | // enough room for two byte trap |
duke@435 | 2858 | __ nop(); |
duke@435 | 2859 | } |
duke@435 | 2860 | |
duke@435 | 2861 | |
duke@435 | 2862 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
duke@435 | 2863 | |
duke@435 | 2864 | // optimized version for linear scan: |
duke@435 | 2865 | // * count must be already in ECX (guaranteed by LinearScan) |
duke@435 | 2866 | // * left and dest must be equal |
duke@435 | 2867 | // * tmp must be unused |
duke@435 | 2868 | assert(count->as_register() == SHIFT_count, "count must be in ECX"); |
duke@435 | 2869 | assert(left == dest, "left and dest must be equal"); |
duke@435 | 2870 | assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); |
duke@435 | 2871 | |
duke@435 | 2872 | if (left->is_single_cpu()) { |
duke@435 | 2873 | Register value = left->as_register(); |
duke@435 | 2874 | assert(value != SHIFT_count, "left cannot be ECX"); |
duke@435 | 2875 | |
duke@435 | 2876 | switch (code) { |
duke@435 | 2877 | case lir_shl: __ shll(value); break; |
duke@435 | 2878 | case lir_shr: __ sarl(value); break; |
duke@435 | 2879 | case lir_ushr: __ shrl(value); break; |
duke@435 | 2880 | default: ShouldNotReachHere(); |
duke@435 | 2881 | } |
duke@435 | 2882 | } else if (left->is_double_cpu()) { |
duke@435 | 2883 | Register lo = left->as_register_lo(); |
duke@435 | 2884 | Register hi = left->as_register_hi(); |
duke@435 | 2885 | assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); |
never@739 | 2886 | #ifdef _LP64 |
never@739 | 2887 | switch (code) { |
never@739 | 2888 | case lir_shl: __ shlptr(lo); break; |
never@739 | 2889 | case lir_shr: __ sarptr(lo); break; |
never@739 | 2890 | case lir_ushr: __ shrptr(lo); break; |
never@739 | 2891 | default: ShouldNotReachHere(); |
never@739 | 2892 | } |
never@739 | 2893 | #else |
duke@435 | 2894 | |
duke@435 | 2895 | switch (code) { |
duke@435 | 2896 | case lir_shl: __ lshl(hi, lo); break; |
duke@435 | 2897 | case lir_shr: __ lshr(hi, lo, true); break; |
duke@435 | 2898 | case lir_ushr: __ lshr(hi, lo, false); break; |
duke@435 | 2899 | default: ShouldNotReachHere(); |
duke@435 | 2900 | } |
never@739 | 2901 | #endif // LP64 |
duke@435 | 2902 | } else { |
duke@435 | 2903 | ShouldNotReachHere(); |
duke@435 | 2904 | } |
duke@435 | 2905 | } |
duke@435 | 2906 | |
duke@435 | 2907 | |
duke@435 | 2908 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
duke@435 | 2909 | if (dest->is_single_cpu()) { |
duke@435 | 2910 | // first move left into dest so that left is not destroyed by the shift |
duke@435 | 2911 | Register value = dest->as_register(); |
duke@435 | 2912 | count = count & 0x1F; // Java spec |
duke@435 | 2913 | |
duke@435 | 2914 | move_regs(left->as_register(), value); |
duke@435 | 2915 | switch (code) { |
duke@435 | 2916 | case lir_shl: __ shll(value, count); break; |
duke@435 | 2917 | case lir_shr: __ sarl(value, count); break; |
duke@435 | 2918 | case lir_ushr: __ shrl(value, count); break; |
duke@435 | 2919 | default: ShouldNotReachHere(); |
duke@435 | 2920 | } |
duke@435 | 2921 | } else if (dest->is_double_cpu()) { |
never@739 | 2922 | #ifndef _LP64 |
duke@435 | 2923 | Unimplemented(); |
never@739 | 2924 | #else |
never@739 | 2925 | // first move left into dest so that left is not destroyed by the shift |
never@739 | 2926 | Register value = dest->as_register_lo(); |
never@739 | 2927 | count = count & 0x1F; // Java spec |
never@739 | 2928 | |
never@739 | 2929 | move_regs(left->as_register_lo(), value); |
never@739 | 2930 | switch (code) { |
never@739 | 2931 | case lir_shl: __ shlptr(value, count); break; |
never@739 | 2932 | case lir_shr: __ sarptr(value, count); break; |
never@739 | 2933 | case lir_ushr: __ shrptr(value, count); break; |
never@739 | 2934 | default: ShouldNotReachHere(); |
never@739 | 2935 | } |
never@739 | 2936 | #endif // _LP64 |
duke@435 | 2937 | } else { |
duke@435 | 2938 | ShouldNotReachHere(); |
duke@435 | 2939 | } |
duke@435 | 2940 | } |
duke@435 | 2941 | |
duke@435 | 2942 | |
duke@435 | 2943 | void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { |
duke@435 | 2944 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2945 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2946 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 2947 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
duke@435 | 2948 | } |
duke@435 | 2949 | |
duke@435 | 2950 | |
duke@435 | 2951 | void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { |
duke@435 | 2952 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2953 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2954 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
never@739 | 2955 | __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
duke@435 | 2956 | } |
duke@435 | 2957 | |
duke@435 | 2958 | |
duke@435 | 2959 | void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { |
duke@435 | 2960 | assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); |
duke@435 | 2961 | int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; |
duke@435 | 2962 | assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); |
duke@435 | 2963 | __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); |
duke@435 | 2964 | } |
duke@435 | 2965 | |
duke@435 | 2966 | |
duke@435 | 2967 | // This code replaces a call to arraycopy; no exception may |
duke@435 | 2968 | // be thrown in this code, they must be thrown in the System.arraycopy |
duke@435 | 2969 | // activation frame; we could save some checks if this would not be the case |
duke@435 | 2970 | void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
duke@435 | 2971 | ciArrayKlass* default_type = op->expected_type(); |
duke@435 | 2972 | Register src = op->src()->as_register(); |
duke@435 | 2973 | Register dst = op->dst()->as_register(); |
duke@435 | 2974 | Register src_pos = op->src_pos()->as_register(); |
duke@435 | 2975 | Register dst_pos = op->dst_pos()->as_register(); |
duke@435 | 2976 | Register length = op->length()->as_register(); |
duke@435 | 2977 | Register tmp = op->tmp()->as_register(); |
duke@435 | 2978 | |
duke@435 | 2979 | CodeStub* stub = op->stub(); |
duke@435 | 2980 | int flags = op->flags(); |
duke@435 | 2981 | BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
duke@435 | 2982 | if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
duke@435 | 2983 | |
duke@435 | 2984 | // if we don't know anything or it's an object array, just go through the generic arraycopy |
duke@435 | 2985 | if (default_type == NULL) { |
duke@435 | 2986 | Label done; |
duke@435 | 2987 | // save outgoing arguments on stack in case call to System.arraycopy is needed |
duke@435 | 2988 | // HACK ALERT. This code used to push the parameters in a hardwired fashion |
duke@435 | 2989 | // for interpreter calling conventions. Now we have to do it in new style conventions. |
duke@435 | 2990 | // For the moment until C1 gets the new register allocator I just force all the |
duke@435 | 2991 | // args to the right place (except the register args) and then on the back side |
duke@435 | 2992 | // reload the register args properly if we go slow path. Yuck |
duke@435 | 2993 | |
duke@435 | 2994 | // These are proper for the calling convention |
duke@435 | 2995 | |
duke@435 | 2996 | store_parameter(length, 2); |
duke@435 | 2997 | store_parameter(dst_pos, 1); |
duke@435 | 2998 | store_parameter(dst, 0); |
duke@435 | 2999 | |
duke@435 | 3000 | // these are just temporary placements until we need to reload |
duke@435 | 3001 | store_parameter(src_pos, 3); |
duke@435 | 3002 | store_parameter(src, 4); |
never@739 | 3003 | NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
never@739 | 3004 | |
never@739 | 3005 | address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
duke@435 | 3006 | |
duke@435 | 3007 | // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint |
never@739 | 3008 | #ifdef _LP64 |
never@739 | 3009 | // The arguments are in java calling convention so we can trivially shift them to C |
never@739 | 3010 | // convention |
never@739 | 3011 | assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3012 | __ mov(c_rarg0, j_rarg0); |
never@739 | 3013 | assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); |
never@739 | 3014 | __ mov(c_rarg1, j_rarg1); |
never@739 | 3015 | assert_different_registers(c_rarg2, j_rarg3, j_rarg4); |
never@739 | 3016 | __ mov(c_rarg2, j_rarg2); |
never@739 | 3017 | assert_different_registers(c_rarg3, j_rarg4); |
never@739 | 3018 | __ mov(c_rarg3, j_rarg3); |
never@739 | 3019 | #ifdef _WIN64 |
never@739 | 3020 | // Allocate abi space for args but be sure to keep stack aligned |
never@739 | 3021 | __ subptr(rsp, 6*wordSize); |
never@739 | 3022 | store_parameter(j_rarg4, 4); |
never@739 | 3023 | __ call(RuntimeAddress(entry)); |
never@739 | 3024 | __ addptr(rsp, 6*wordSize); |
never@739 | 3025 | #else |
never@739 | 3026 | __ mov(c_rarg4, j_rarg4); |
never@739 | 3027 | __ call(RuntimeAddress(entry)); |
never@739 | 3028 | #endif // _WIN64 |
never@739 | 3029 | #else |
never@739 | 3030 | __ push(length); |
never@739 | 3031 | __ push(dst_pos); |
never@739 | 3032 | __ push(dst); |
never@739 | 3033 | __ push(src_pos); |
never@739 | 3034 | __ push(src); |
duke@435 | 3035 | __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
duke@435 | 3036 | |
never@739 | 3037 | #endif // _LP64 |
never@739 | 3038 | |
duke@435 | 3039 | __ cmpl(rax, 0); |
duke@435 | 3040 | __ jcc(Assembler::equal, *stub->continuation()); |
duke@435 | 3041 | |
duke@435 | 3042 | // Reload values from the stack so they are where the stub |
duke@435 | 3043 | // expects them. |
never@739 | 3044 | __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
never@739 | 3045 | __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
never@739 | 3046 | __ movptr (length, Address(rsp, 2*BytesPerWord)); |
never@739 | 3047 | __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
never@739 | 3048 | __ movptr (src, Address(rsp, 4*BytesPerWord)); |
duke@435 | 3049 | __ jmp(*stub->entry()); |
duke@435 | 3050 | |
duke@435 | 3051 | __ bind(*stub->continuation()); |
duke@435 | 3052 | return; |
duke@435 | 3053 | } |
duke@435 | 3054 | |
duke@435 | 3055 | assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); |
duke@435 | 3056 | |
kvn@464 | 3057 | int elem_size = type2aelembytes(basic_type); |
duke@435 | 3058 | int shift_amount; |
duke@435 | 3059 | Address::ScaleFactor scale; |
duke@435 | 3060 | |
duke@435 | 3061 | switch (elem_size) { |
duke@435 | 3062 | case 1 : |
duke@435 | 3063 | shift_amount = 0; |
duke@435 | 3064 | scale = Address::times_1; |
duke@435 | 3065 | break; |
duke@435 | 3066 | case 2 : |
duke@435 | 3067 | shift_amount = 1; |
duke@435 | 3068 | scale = Address::times_2; |
duke@435 | 3069 | break; |
duke@435 | 3070 | case 4 : |
duke@435 | 3071 | shift_amount = 2; |
duke@435 | 3072 | scale = Address::times_4; |
duke@435 | 3073 | break; |
duke@435 | 3074 | case 8 : |
duke@435 | 3075 | shift_amount = 3; |
duke@435 | 3076 | scale = Address::times_8; |
duke@435 | 3077 | break; |
duke@435 | 3078 | default: |
duke@435 | 3079 | ShouldNotReachHere(); |
duke@435 | 3080 | } |
duke@435 | 3081 | |
duke@435 | 3082 | Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3083 | Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); |
duke@435 | 3084 | Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3085 | Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); |
duke@435 | 3086 | |
never@739 | 3087 | // length and pos's are all sign extended at this point on 64bit |
never@739 | 3088 | |
duke@435 | 3089 | // test for NULL |
duke@435 | 3090 | if (flags & LIR_OpArrayCopy::src_null_check) { |
never@739 | 3091 | __ testptr(src, src); |
duke@435 | 3092 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3093 | } |
duke@435 | 3094 | if (flags & LIR_OpArrayCopy::dst_null_check) { |
never@739 | 3095 | __ testptr(dst, dst); |
duke@435 | 3096 | __ jcc(Assembler::zero, *stub->entry()); |
duke@435 | 3097 | } |
duke@435 | 3098 | |
duke@435 | 3099 | // check if negative |
duke@435 | 3100 | if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
duke@435 | 3101 | __ testl(src_pos, src_pos); |
duke@435 | 3102 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3103 | } |
duke@435 | 3104 | if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
duke@435 | 3105 | __ testl(dst_pos, dst_pos); |
duke@435 | 3106 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3107 | } |
duke@435 | 3108 | if (flags & LIR_OpArrayCopy::length_positive_check) { |
duke@435 | 3109 | __ testl(length, length); |
duke@435 | 3110 | __ jcc(Assembler::less, *stub->entry()); |
duke@435 | 3111 | } |
duke@435 | 3112 | |
duke@435 | 3113 | if (flags & LIR_OpArrayCopy::src_range_check) { |
never@739 | 3114 | __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
duke@435 | 3115 | __ cmpl(tmp, src_length_addr); |
duke@435 | 3116 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3117 | } |
duke@435 | 3118 | if (flags & LIR_OpArrayCopy::dst_range_check) { |
never@739 | 3119 | __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
duke@435 | 3120 | __ cmpl(tmp, dst_length_addr); |
duke@435 | 3121 | __ jcc(Assembler::above, *stub->entry()); |
duke@435 | 3122 | } |
duke@435 | 3123 | |
duke@435 | 3124 | if (flags & LIR_OpArrayCopy::type_check) { |
never@739 | 3125 | __ movptr(tmp, src_klass_addr); |
never@739 | 3126 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3127 | __ jcc(Assembler::notEqual, *stub->entry()); |
duke@435 | 3128 | } |
duke@435 | 3129 | |
duke@435 | 3130 | #ifdef ASSERT |
duke@435 | 3131 | if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
duke@435 | 3132 | // Sanity check the known type with the incoming class. For the |
duke@435 | 3133 | // primitive case the types must match exactly with src.klass and |
duke@435 | 3134 | // dst.klass each exactly matching the default type. For the |
duke@435 | 3135 | // object array case, if no type check is needed then either the |
duke@435 | 3136 | // dst type is exactly the expected type and the src type is a |
duke@435 | 3137 | // subtype which we can't check or src is the same array as dst |
duke@435 | 3138 | // but not necessarily exactly of type default_type. |
duke@435 | 3139 | Label known_ok, halt; |
duke@435 | 3140 | __ movoop(tmp, default_type->encoding()); |
duke@435 | 3141 | if (basic_type != T_OBJECT) { |
never@739 | 3142 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3143 | __ jcc(Assembler::notEqual, halt); |
never@739 | 3144 | __ cmpptr(tmp, src_klass_addr); |
duke@435 | 3145 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3146 | } else { |
never@739 | 3147 | __ cmpptr(tmp, dst_klass_addr); |
duke@435 | 3148 | __ jcc(Assembler::equal, known_ok); |
never@739 | 3149 | __ cmpptr(src, dst); |
duke@435 | 3150 | __ jcc(Assembler::equal, known_ok); |
duke@435 | 3151 | } |
duke@435 | 3152 | __ bind(halt); |
duke@435 | 3153 | __ stop("incorrect type information in arraycopy"); |
duke@435 | 3154 | __ bind(known_ok); |
duke@435 | 3155 | } |
duke@435 | 3156 | #endif |
duke@435 | 3157 | |
never@739 | 3158 | if (shift_amount > 0 && basic_type != T_OBJECT) { |
never@739 | 3159 | __ shlptr(length, shift_amount); |
never@739 | 3160 | } |
never@739 | 3161 | |
never@739 | 3162 | #ifdef _LP64 |
never@739 | 3163 | assert_different_registers(c_rarg0, dst, dst_pos, length); |
never@739 | 3164 | __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3165 | assert_different_registers(c_rarg1, length); |
never@739 | 3166 | __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
never@739 | 3167 | __ mov(c_rarg2, length); |
never@739 | 3168 | |
never@739 | 3169 | #else |
never@739 | 3170 | __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3171 | store_parameter(tmp, 0); |
never@739 | 3172 | __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
duke@435 | 3173 | store_parameter(tmp, 1); |
duke@435 | 3174 | store_parameter(length, 2); |
never@739 | 3175 | #endif // _LP64 |
duke@435 | 3176 | if (basic_type == T_OBJECT) { |
duke@435 | 3177 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); |
duke@435 | 3178 | } else { |
duke@435 | 3179 | __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); |
duke@435 | 3180 | } |
duke@435 | 3181 | |
duke@435 | 3182 | __ bind(*stub->continuation()); |
duke@435 | 3183 | } |
duke@435 | 3184 | |
duke@435 | 3185 | |
duke@435 | 3186 | void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
duke@435 | 3187 | Register obj = op->obj_opr()->as_register(); // may not be an oop |
duke@435 | 3188 | Register hdr = op->hdr_opr()->as_register(); |
duke@435 | 3189 | Register lock = op->lock_opr()->as_register(); |
duke@435 | 3190 | if (!UseFastLocking) { |
duke@435 | 3191 | __ jmp(*op->stub()->entry()); |
duke@435 | 3192 | } else if (op->code() == lir_lock) { |
duke@435 | 3193 | Register scratch = noreg; |
duke@435 | 3194 | if (UseBiasedLocking) { |
duke@435 | 3195 | scratch = op->scratch_opr()->as_register(); |
duke@435 | 3196 | } |
duke@435 | 3197 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3198 | // add debug info for NullPointerException only if one is possible |
duke@435 | 3199 | int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); |
duke@435 | 3200 | if (op->info() != NULL) { |
duke@435 | 3201 | add_debug_info_for_null_check(null_check_offset, op->info()); |
duke@435 | 3202 | } |
duke@435 | 3203 | // done |
duke@435 | 3204 | } else if (op->code() == lir_unlock) { |
duke@435 | 3205 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 3206 | __ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
duke@435 | 3207 | } else { |
duke@435 | 3208 | Unimplemented(); |
duke@435 | 3209 | } |
duke@435 | 3210 | __ bind(*op->stub()->continuation()); |
duke@435 | 3211 | } |
duke@435 | 3212 | |
duke@435 | 3213 | |
duke@435 | 3214 | void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
duke@435 | 3215 | ciMethod* method = op->profiled_method(); |
duke@435 | 3216 | int bci = op->profiled_bci(); |
duke@435 | 3217 | |
duke@435 | 3218 | // Update counter for all call types |
duke@435 | 3219 | ciMethodData* md = method->method_data(); |
duke@435 | 3220 | if (md == NULL) { |
duke@435 | 3221 | bailout("out of memory building methodDataOop"); |
duke@435 | 3222 | return; |
duke@435 | 3223 | } |
duke@435 | 3224 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 3225 | assert(data->is_CounterData(), "need CounterData for calls"); |
duke@435 | 3226 | assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
duke@435 | 3227 | Register mdo = op->mdo()->as_register(); |
duke@435 | 3228 | __ movoop(mdo, md->encoding()); |
duke@435 | 3229 | Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
duke@435 | 3230 | __ addl(counter_addr, DataLayout::counter_increment); |
duke@435 | 3231 | Bytecodes::Code bc = method->java_code_at_bci(bci); |
duke@435 | 3232 | // Perform additional virtual call profiling for invokevirtual and |
duke@435 | 3233 | // invokeinterface bytecodes |
duke@435 | 3234 | if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
duke@435 | 3235 | Tier1ProfileVirtualCalls) { |
duke@435 | 3236 | assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
duke@435 | 3237 | Register recv = op->recv()->as_register(); |
duke@435 | 3238 | assert_different_registers(mdo, recv); |
duke@435 | 3239 | assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
duke@435 | 3240 | ciKlass* known_klass = op->known_holder(); |
duke@435 | 3241 | if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { |
duke@435 | 3242 | // We know the type that will be seen at this call site; we can |
duke@435 | 3243 | // statically update the methodDataOop rather than needing to do |
duke@435 | 3244 | // dynamic tests on the receiver type |
duke@435 | 3245 | |
duke@435 | 3246 | // NOTE: we should probably put a lock around this search to |
duke@435 | 3247 | // avoid collisions by concurrent compilations |
duke@435 | 3248 | ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
duke@435 | 3249 | uint i; |
duke@435 | 3250 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3251 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3252 | if (known_klass->equals(receiver)) { |
duke@435 | 3253 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3254 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3255 | return; |
duke@435 | 3256 | } |
duke@435 | 3257 | } |
duke@435 | 3258 | |
duke@435 | 3259 | // Receiver type not found in profile data; select an empty slot |
duke@435 | 3260 | |
duke@435 | 3261 | // Note that this is less efficient than it should be because it |
duke@435 | 3262 | // always does a write to the receiver part of the |
duke@435 | 3263 | // VirtualCallData rather than just the first time |
duke@435 | 3264 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3265 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 3266 | if (receiver == NULL) { |
duke@435 | 3267 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
duke@435 | 3268 | __ movoop(recv_addr, known_klass->encoding()); |
duke@435 | 3269 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3270 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3271 | return; |
duke@435 | 3272 | } |
duke@435 | 3273 | } |
duke@435 | 3274 | } else { |
never@739 | 3275 | __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
duke@435 | 3276 | Label update_done; |
duke@435 | 3277 | uint i; |
duke@435 | 3278 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3279 | Label next_test; |
duke@435 | 3280 | // See if the receiver is receiver[n]. |
never@739 | 3281 | __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); |
duke@435 | 3282 | __ jcc(Assembler::notEqual, next_test); |
duke@435 | 3283 | Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
duke@435 | 3284 | __ addl(data_addr, DataLayout::counter_increment); |
duke@435 | 3285 | __ jmp(update_done); |
duke@435 | 3286 | __ bind(next_test); |
duke@435 | 3287 | } |
duke@435 | 3288 | |
duke@435 | 3289 | // Didn't find receiver; find next empty slot and fill it in |
duke@435 | 3290 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 3291 | Label next_test; |
duke@435 | 3292 | Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); |
never@739 | 3293 | __ cmpptr(recv_addr, (int32_t)NULL_WORD); |
duke@435 | 3294 | __ jcc(Assembler::notEqual, next_test); |
never@739 | 3295 | __ movptr(recv_addr, recv); |
duke@435 | 3296 | __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); |
duke@435 | 3297 | if (i < (VirtualCallData::row_limit() - 1)) { |
duke@435 | 3298 | __ jmp(update_done); |
duke@435 | 3299 | } |
duke@435 | 3300 | __ bind(next_test); |
duke@435 | 3301 | } |
duke@435 | 3302 | |
duke@435 | 3303 | __ bind(update_done); |
duke@435 | 3304 | } |
duke@435 | 3305 | } |
duke@435 | 3306 | } |
duke@435 | 3307 | |
duke@435 | 3308 | |
duke@435 | 3309 | void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
duke@435 | 3310 | Unimplemented(); |
duke@435 | 3311 | } |
duke@435 | 3312 | |
duke@435 | 3313 | |
duke@435 | 3314 | void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { |
never@739 | 3315 | __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
duke@435 | 3316 | } |
duke@435 | 3317 | |
duke@435 | 3318 | |
duke@435 | 3319 | void LIR_Assembler::align_backward_branch_target() { |
duke@435 | 3320 | __ align(BytesPerWord); |
duke@435 | 3321 | } |
duke@435 | 3322 | |
duke@435 | 3323 | |
duke@435 | 3324 | void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
duke@435 | 3325 | if (left->is_single_cpu()) { |
duke@435 | 3326 | __ negl(left->as_register()); |
duke@435 | 3327 | move_regs(left->as_register(), dest->as_register()); |
duke@435 | 3328 | |
duke@435 | 3329 | } else if (left->is_double_cpu()) { |
duke@435 | 3330 | Register lo = left->as_register_lo(); |
never@739 | 3331 | #ifdef _LP64 |
never@739 | 3332 | Register dst = dest->as_register_lo(); |
never@739 | 3333 | __ movptr(dst, lo); |
never@739 | 3334 | __ negptr(dst); |
never@739 | 3335 | #else |
duke@435 | 3336 | Register hi = left->as_register_hi(); |
duke@435 | 3337 | __ lneg(hi, lo); |
duke@435 | 3338 | if (dest->as_register_lo() == hi) { |
duke@435 | 3339 | assert(dest->as_register_hi() != lo, "destroying register"); |
duke@435 | 3340 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3341 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3342 | } else { |
duke@435 | 3343 | move_regs(lo, dest->as_register_lo()); |
duke@435 | 3344 | move_regs(hi, dest->as_register_hi()); |
duke@435 | 3345 | } |
never@739 | 3346 | #endif // _LP64 |
duke@435 | 3347 | |
duke@435 | 3348 | } else if (dest->is_single_xmm()) { |
duke@435 | 3349 | if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { |
duke@435 | 3350 | __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); |
duke@435 | 3351 | } |
duke@435 | 3352 | __ xorps(dest->as_xmm_float_reg(), |
duke@435 | 3353 | ExternalAddress((address)float_signflip_pool)); |
duke@435 | 3354 | |
duke@435 | 3355 | } else if (dest->is_double_xmm()) { |
duke@435 | 3356 | if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { |
duke@435 | 3357 | __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); |
duke@435 | 3358 | } |
duke@435 | 3359 | __ xorpd(dest->as_xmm_double_reg(), |
duke@435 | 3360 | ExternalAddress((address)double_signflip_pool)); |
duke@435 | 3361 | |
duke@435 | 3362 | } else if (left->is_single_fpu() || left->is_double_fpu()) { |
duke@435 | 3363 | assert(left->fpu() == 0, "arg must be on TOS"); |
duke@435 | 3364 | assert(dest->fpu() == 0, "dest must be TOS"); |
duke@435 | 3365 | __ fchs(); |
duke@435 | 3366 | |
duke@435 | 3367 | } else { |
duke@435 | 3368 | ShouldNotReachHere(); |
duke@435 | 3369 | } |
duke@435 | 3370 | } |
duke@435 | 3371 | |
duke@435 | 3372 | |
duke@435 | 3373 | void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { |
duke@435 | 3374 | assert(addr->is_address() && dest->is_register(), "check"); |
never@739 | 3375 | Register reg; |
never@739 | 3376 | reg = dest->as_pointer_register(); |
never@739 | 3377 | __ lea(reg, as_Address(addr->as_address_ptr())); |
duke@435 | 3378 | } |
duke@435 | 3379 | |
duke@435 | 3380 | |
duke@435 | 3381 | |
duke@435 | 3382 | void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 3383 | assert(!tmp->is_valid(), "don't need temporary"); |
duke@435 | 3384 | __ call(RuntimeAddress(dest)); |
duke@435 | 3385 | if (info != NULL) { |
duke@435 | 3386 | add_call_info_here(info); |
duke@435 | 3387 | } |
duke@435 | 3388 | } |
duke@435 | 3389 | |
duke@435 | 3390 | |
duke@435 | 3391 | void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
duke@435 | 3392 | assert(type == T_LONG, "only for volatile long fields"); |
duke@435 | 3393 | |
duke@435 | 3394 | if (info != NULL) { |
duke@435 | 3395 | add_debug_info_for_null_check_here(info); |
duke@435 | 3396 | } |
duke@435 | 3397 | |
duke@435 | 3398 | if (src->is_double_xmm()) { |
duke@435 | 3399 | if (dest->is_double_cpu()) { |
never@739 | 3400 | #ifdef _LP64 |
never@739 | 3401 | __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); |
never@739 | 3402 | #else |
never@739 | 3403 | __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); |
duke@435 | 3404 | __ psrlq(src->as_xmm_double_reg(), 32); |
never@739 | 3405 | __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
never@739 | 3406 | #endif // _LP64 |
duke@435 | 3407 | } else if (dest->is_double_stack()) { |
duke@435 | 3408 | __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); |
duke@435 | 3409 | } else if (dest->is_address()) { |
duke@435 | 3410 | __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); |
duke@435 | 3411 | } else { |
duke@435 | 3412 | ShouldNotReachHere(); |
duke@435 | 3413 | } |
duke@435 | 3414 | |
duke@435 | 3415 | } else if (dest->is_double_xmm()) { |
duke@435 | 3416 | if (src->is_double_stack()) { |
duke@435 | 3417 | __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3418 | } else if (src->is_address()) { |
duke@435 | 3419 | __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); |
duke@435 | 3420 | } else { |
duke@435 | 3421 | ShouldNotReachHere(); |
duke@435 | 3422 | } |
duke@435 | 3423 | |
duke@435 | 3424 | } else if (src->is_double_fpu()) { |
duke@435 | 3425 | assert(src->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3426 | if (dest->is_double_stack()) { |
duke@435 | 3427 | __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); |
duke@435 | 3428 | } else if (dest->is_address()) { |
duke@435 | 3429 | __ fistp_d(as_Address(dest->as_address_ptr())); |
duke@435 | 3430 | } else { |
duke@435 | 3431 | ShouldNotReachHere(); |
duke@435 | 3432 | } |
duke@435 | 3433 | |
duke@435 | 3434 | } else if (dest->is_double_fpu()) { |
duke@435 | 3435 | assert(dest->fpu_regnrLo() == 0, "must be TOS"); |
duke@435 | 3436 | if (src->is_double_stack()) { |
duke@435 | 3437 | __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); |
duke@435 | 3438 | } else if (src->is_address()) { |
duke@435 | 3439 | __ fild_d(as_Address(src->as_address_ptr())); |
duke@435 | 3440 | } else { |
duke@435 | 3441 | ShouldNotReachHere(); |
duke@435 | 3442 | } |
duke@435 | 3443 | } else { |
duke@435 | 3444 | ShouldNotReachHere(); |
duke@435 | 3445 | } |
duke@435 | 3446 | } |
duke@435 | 3447 | |
duke@435 | 3448 | |
duke@435 | 3449 | void LIR_Assembler::membar() { |
never@739 | 3450 | // QQQ sparc TSO uses this, |
never@739 | 3451 | __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
duke@435 | 3452 | } |
duke@435 | 3453 | |
duke@435 | 3454 | void LIR_Assembler::membar_acquire() { |
duke@435 | 3455 | // No x86 machines currently require load fences |
duke@435 | 3456 | // __ load_fence(); |
duke@435 | 3457 | } |
duke@435 | 3458 | |
duke@435 | 3459 | void LIR_Assembler::membar_release() { |
duke@435 | 3460 | // No x86 machines currently require store fences |
duke@435 | 3461 | // __ store_fence(); |
duke@435 | 3462 | } |
duke@435 | 3463 | |
duke@435 | 3464 | void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
duke@435 | 3465 | assert(result_reg->is_register(), "check"); |
never@739 | 3466 | #ifdef _LP64 |
never@739 | 3467 | // __ get_thread(result_reg->as_register_lo()); |
never@739 | 3468 | __ mov(result_reg->as_register(), r15_thread); |
never@739 | 3469 | #else |
duke@435 | 3470 | __ get_thread(result_reg->as_register()); |
never@739 | 3471 | #endif // _LP64 |
duke@435 | 3472 | } |
duke@435 | 3473 | |
duke@435 | 3474 | |
duke@435 | 3475 | void LIR_Assembler::peephole(LIR_List*) { |
duke@435 | 3476 | // do nothing for now |
duke@435 | 3477 | } |
duke@435 | 3478 | |
duke@435 | 3479 | |
duke@435 | 3480 | #undef __ |