Wed, 28 Aug 2013 11:22:43 +0200
8023597: Optimize G1 barriers code for unsafe load_store
Summary: Avoid loading old values in G1 pre-barriers for inlined unsafe load_store nodes.
Reviewed-by: kvn, tonyp
Contributed-by: Martin Doerr <martin.doerr@sap.com>
duke@435 | 1 | /* |
kvn@3882 | 2 | * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "libadt/vectset.hpp" |
stefank@2314 | 27 | #include "memory/allocation.inline.hpp" |
stefank@2314 | 28 | #include "opto/addnode.hpp" |
stefank@2314 | 29 | #include "opto/c2compiler.hpp" |
stefank@2314 | 30 | #include "opto/callnode.hpp" |
stefank@2314 | 31 | #include "opto/cfgnode.hpp" |
stefank@2314 | 32 | #include "opto/chaitin.hpp" |
stefank@2314 | 33 | #include "opto/loopnode.hpp" |
stefank@2314 | 34 | #include "opto/machnode.hpp" |
duke@435 | 35 | |
duke@435 | 36 | //------------------------------Split-------------------------------------- |
twisti@1040 | 37 | // Walk the graph in RPO and for each lrg which spills, propagate reaching |
twisti@1040 | 38 | // definitions. During propagation, split the live range around regions of |
duke@435 | 39 | // High Register Pressure (HRP). If a Def is in a region of Low Register |
duke@435 | 40 | // Pressure (LRP), it will not get spilled until we encounter a region of |
duke@435 | 41 | // HRP between it and one of its uses. We will spill at the transition |
duke@435 | 42 | // point between LRP and HRP. Uses in the HRP region will use the spilled |
duke@435 | 43 | // Def. The first Use outside the HRP region will generate a SpillCopy to |
duke@435 | 44 | // hoist the live range back up into a register, and all subsequent uses |
duke@435 | 45 | // will use that new Def until another HRP region is encountered. Defs in |
duke@435 | 46 | // HRP regions will get trailing SpillCopies to push the LRG down into the |
duke@435 | 47 | // stack immediately. |
duke@435 | 48 | // |
duke@435 | 49 | // As a side effect, unlink from (hence make dead) coalesced copies. |
duke@435 | 50 | // |
duke@435 | 51 | |
duke@435 | 52 | static const char out_of_nodes[] = "out of nodes during split"; |
duke@435 | 53 | |
adlertz@5227 | 54 | static bool contains_no_live_range_input(const Node* def) { |
adlertz@5227 | 55 | for (uint i = 1; i < def->req(); ++i) { |
adlertz@5227 | 56 | if (def->in(i) != NULL && def->in_RegMask(i).is_NotEmpty()) { |
adlertz@5227 | 57 | return false; |
adlertz@5227 | 58 | } |
adlertz@5227 | 59 | } |
adlertz@5227 | 60 | return true; |
adlertz@5227 | 61 | } |
adlertz@5227 | 62 | |
duke@435 | 63 | //------------------------------get_spillcopy_wide----------------------------- |
duke@435 | 64 | // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the |
duke@435 | 65 | // wide ideal-register spill-mask if possible. If the 'wide-mask' does |
duke@435 | 66 | // not cover the input (or output), use the input (or output) mask instead. |
duke@435 | 67 | Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { |
duke@435 | 68 | // If ideal reg doesn't exist we've got a bad schedule happening |
duke@435 | 69 | // that is forcing us to spill something that isn't spillable. |
duke@435 | 70 | // Bail rather than abort |
duke@435 | 71 | int ireg = def->ideal_reg(); |
duke@435 | 72 | if( ireg == 0 || ireg == Op_RegFlags ) { |
never@850 | 73 | assert(false, "attempted to spill a non-spillable item"); |
duke@435 | 74 | C->record_method_not_compilable("attempted to spill a non-spillable item"); |
duke@435 | 75 | return NULL; |
duke@435 | 76 | } |
duke@435 | 77 | if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { |
duke@435 | 78 | return NULL; |
duke@435 | 79 | } |
duke@435 | 80 | const RegMask *i_mask = &def->out_RegMask(); |
duke@435 | 81 | const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg]; |
duke@435 | 82 | const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask; |
duke@435 | 83 | const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask; |
duke@435 | 84 | const RegMask *w_o_mask; |
duke@435 | 85 | |
kvn@3882 | 86 | int num_regs = RegMask::num_registers(ireg); |
kvn@3882 | 87 | bool is_vect = RegMask::is_vector(ireg); |
duke@435 | 88 | if( w_mask->overlap( *o_mask ) && // Overlap AND |
kvn@3882 | 89 | ((num_regs == 1) // Single use or aligned |
kvn@3882 | 90 | || is_vect // or vector |
kvn@3882 | 91 | || !is_vect && o_mask->is_aligned_pairs()) ) { |
kvn@3882 | 92 | assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned"); |
duke@435 | 93 | // Don't come here for mis-aligned doubles |
duke@435 | 94 | w_o_mask = w_mask; |
duke@435 | 95 | } else { // wide ideal mask does not overlap with o_mask |
duke@435 | 96 | // Mis-aligned doubles come here and XMM->FPR moves on x86. |
duke@435 | 97 | w_o_mask = o_mask; // Must target desired registers |
duke@435 | 98 | // Does the ideal-reg-mask overlap with o_mask? I.e., can I use |
duke@435 | 99 | // a reg-reg move or do I need a trip across register classes |
duke@435 | 100 | // (and thus through memory)? |
duke@435 | 101 | if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() ) |
duke@435 | 102 | // Here we assume a trip through memory is required. |
duke@435 | 103 | w_i_mask = &C->FIRST_STACK_mask(); |
duke@435 | 104 | } |
duke@435 | 105 | return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); |
duke@435 | 106 | } |
duke@435 | 107 | |
duke@435 | 108 | //------------------------------insert_proj------------------------------------ |
twisti@1040 | 109 | // Insert the spill at chosen location. Skip over any intervening Proj's or |
duke@435 | 110 | // Phis. Skip over a CatchNode and projs, inserting in the fall-through block |
duke@435 | 111 | // instead. Update high-pressure indices. Create a new live range. |
duke@435 | 112 | void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) { |
duke@435 | 113 | // Skip intervening ProjNodes. Do not insert between a ProjNode and |
duke@435 | 114 | // its definer. |
adlertz@5635 | 115 | while( i < b->number_of_nodes() && |
adlertz@5635 | 116 | (b->get_node(i)->is_Proj() || |
adlertz@5635 | 117 | b->get_node(i)->is_Phi() ) ) |
duke@435 | 118 | i++; |
duke@435 | 119 | |
duke@435 | 120 | // Do not insert between a call and his Catch |
adlertz@5635 | 121 | if( b->get_node(i)->is_Catch() ) { |
duke@435 | 122 | // Put the instruction at the top of the fall-thru block. |
duke@435 | 123 | // Find the fall-thru projection |
duke@435 | 124 | while( 1 ) { |
adlertz@5635 | 125 | const CatchProjNode *cp = b->get_node(++i)->as_CatchProj(); |
duke@435 | 126 | if( cp->_con == CatchProjNode::fall_through_index ) |
duke@435 | 127 | break; |
duke@435 | 128 | } |
duke@435 | 129 | int sidx = i - b->end_idx()-1; |
duke@435 | 130 | b = b->_succs[sidx]; // Switch to successor block |
duke@435 | 131 | i = 1; // Right at start of block |
duke@435 | 132 | } |
duke@435 | 133 | |
adlertz@5635 | 134 | b->insert_node(spill, i); // Insert node in block |
adlertz@5509 | 135 | _cfg.map_node_to_block(spill, b); // Update node->block mapping to reflect |
duke@435 | 136 | // Adjust the point where we go hi-pressure |
duke@435 | 137 | if( i <= b->_ihrp_index ) b->_ihrp_index++; |
duke@435 | 138 | if( i <= b->_fhrp_index ) b->_fhrp_index++; |
duke@435 | 139 | |
duke@435 | 140 | // Assign a new Live Range Number to the SpillCopy and grow |
duke@435 | 141 | // the node->live range mapping. |
duke@435 | 142 | new_lrg(spill,maxlrg); |
duke@435 | 143 | } |
duke@435 | 144 | |
duke@435 | 145 | //------------------------------split_DEF-------------------------------------- |
twisti@1040 | 146 | // There are four categories of Split; UP/DOWN x DEF/USE |
duke@435 | 147 | // Only three of these really occur as DOWN/USE will always color |
duke@435 | 148 | // Any Split with a DEF cannot CISC-Spill now. Thus we need |
duke@435 | 149 | // two helper routines, one for Split DEFS (insert after instruction), |
duke@435 | 150 | // one for Split USES (insert before instruction). DEF insertion |
duke@435 | 151 | // happens inside Split, where the Leaveblock array is updated. |
duke@435 | 152 | uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) { |
duke@435 | 153 | #ifdef ASSERT |
duke@435 | 154 | // Increment the counter for this lrg |
duke@435 | 155 | splits.at_put(slidx, splits.at(slidx)+1); |
duke@435 | 156 | #endif |
duke@435 | 157 | // If we are spilling the memory op for an implicit null check, at the |
duke@435 | 158 | // null check location (ie - null check is in HRP block) we need to do |
duke@435 | 159 | // the null-check first, then spill-down in the following block. |
duke@435 | 160 | // (The implicit_null_check function ensures the use is also dominated |
duke@435 | 161 | // by the branch-not-taken block.) |
duke@435 | 162 | Node *be = b->end(); |
adlertz@5635 | 163 | if( be->is_MachNullCheck() && be->in(1) == def && def == b->get_node(loc)) { |
duke@435 | 164 | // Spill goes in the branch-not-taken block |
adlertz@5635 | 165 | b = b->_succs[b->get_node(b->end_idx()+1)->Opcode() == Op_IfTrue]; |
duke@435 | 166 | loc = 0; // Just past the Region |
duke@435 | 167 | } |
duke@435 | 168 | assert( loc >= 0, "must insert past block head" ); |
duke@435 | 169 | |
duke@435 | 170 | // Get a def-side SpillCopy |
duke@435 | 171 | Node *spill = get_spillcopy_wide(def,NULL,0); |
duke@435 | 172 | // Did we fail to split?, then bail |
duke@435 | 173 | if (!spill) { |
duke@435 | 174 | return 0; |
duke@435 | 175 | } |
duke@435 | 176 | |
duke@435 | 177 | // Insert the spill at chosen location |
duke@435 | 178 | insert_proj( b, loc+1, spill, maxlrg++); |
duke@435 | 179 | |
duke@435 | 180 | // Insert new node into Reaches array |
duke@435 | 181 | Reachblock[slidx] = spill; |
duke@435 | 182 | // Update debug list of reaching down definitions by adding this one |
duke@435 | 183 | debug_defs[slidx] = spill; |
duke@435 | 184 | |
duke@435 | 185 | // return updated count of live ranges |
duke@435 | 186 | return maxlrg; |
duke@435 | 187 | } |
duke@435 | 188 | |
duke@435 | 189 | //------------------------------split_USE-------------------------------------- |
duke@435 | 190 | // Splits at uses can involve redeffing the LRG, so no CISC Spilling there. |
duke@435 | 191 | // Debug uses want to know if def is already stack enabled. |
duke@435 | 192 | uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) { |
duke@435 | 193 | #ifdef ASSERT |
duke@435 | 194 | // Increment the counter for this lrg |
duke@435 | 195 | splits.at_put(slidx, splits.at(slidx)+1); |
duke@435 | 196 | #endif |
duke@435 | 197 | |
duke@435 | 198 | // Some setup stuff for handling debug node uses |
duke@435 | 199 | JVMState* jvms = use->jvms(); |
duke@435 | 200 | uint debug_start = jvms ? jvms->debug_start() : 999999; |
duke@435 | 201 | uint debug_end = jvms ? jvms->debug_end() : 999999; |
duke@435 | 202 | |
duke@435 | 203 | //------------------------------------------- |
duke@435 | 204 | // Check for use of debug info |
duke@435 | 205 | if (useidx >= debug_start && useidx < debug_end) { |
duke@435 | 206 | // Actually it's perfectly legal for constant debug info to appear |
duke@435 | 207 | // just unlikely. In this case the optimizer left a ConI of a 4 |
duke@435 | 208 | // as both inputs to a Phi with only a debug use. It's a single-def |
duke@435 | 209 | // live range of a rematerializable value. The live range spills, |
duke@435 | 210 | // rematerializes and now the ConI directly feeds into the debug info. |
duke@435 | 211 | // assert(!def->is_Con(), "constant debug info already constructed directly"); |
duke@435 | 212 | |
duke@435 | 213 | // Special split handling for Debug Info |
duke@435 | 214 | // If DEF is DOWN, just hook the edge and return |
duke@435 | 215 | // If DEF is UP, Split it DOWN for this USE. |
duke@435 | 216 | if( def->is_Mach() ) { |
duke@435 | 217 | if( def_down ) { |
duke@435 | 218 | // DEF is DOWN, so connect USE directly to the DEF |
duke@435 | 219 | use->set_req(useidx, def); |
duke@435 | 220 | } else { |
duke@435 | 221 | // Block and index where the use occurs. |
adlertz@5509 | 222 | Block *b = _cfg.get_block_for_node(use); |
duke@435 | 223 | // Put the clone just prior to use |
duke@435 | 224 | int bindex = b->find_node(use); |
duke@435 | 225 | // DEF is UP, so must copy it DOWN and hook in USE |
duke@435 | 226 | // Insert SpillCopy before the USE, which uses DEF as its input, |
duke@435 | 227 | // and defs a new live range, which is used by this node. |
duke@435 | 228 | Node *spill = get_spillcopy_wide(def,use,useidx); |
duke@435 | 229 | // did we fail to split? |
duke@435 | 230 | if (!spill) { |
duke@435 | 231 | // Bail |
duke@435 | 232 | return 0; |
duke@435 | 233 | } |
duke@435 | 234 | // insert into basic block |
duke@435 | 235 | insert_proj( b, bindex, spill, maxlrg++ ); |
duke@435 | 236 | // Use the new split |
duke@435 | 237 | use->set_req(useidx,spill); |
duke@435 | 238 | } |
duke@435 | 239 | // No further split handling needed for this use |
duke@435 | 240 | return maxlrg; |
duke@435 | 241 | } // End special splitting for debug info live range |
duke@435 | 242 | } // If debug info |
duke@435 | 243 | |
duke@435 | 244 | // CISC-SPILLING |
duke@435 | 245 | // Finally, check to see if USE is CISC-Spillable, and if so, |
duke@435 | 246 | // gather_lrg_masks will add the flags bit to its mask, and |
duke@435 | 247 | // no use side copy is needed. This frees up the live range |
duke@435 | 248 | // register choices without causing copy coalescing, etc. |
duke@435 | 249 | if( UseCISCSpill && cisc_sp ) { |
duke@435 | 250 | int inp = use->cisc_operand(); |
duke@435 | 251 | if( inp != AdlcVMDeps::Not_cisc_spillable ) |
duke@435 | 252 | // Convert operand number to edge index number |
duke@435 | 253 | inp = use->as_Mach()->operand_index(inp); |
duke@435 | 254 | if( inp == (int)useidx ) { |
duke@435 | 255 | use->set_req(useidx, def); |
duke@435 | 256 | #ifndef PRODUCT |
duke@435 | 257 | if( TraceCISCSpill ) { |
duke@435 | 258 | tty->print(" set_split: "); |
duke@435 | 259 | use->dump(); |
duke@435 | 260 | } |
duke@435 | 261 | #endif |
duke@435 | 262 | return maxlrg; |
duke@435 | 263 | } |
duke@435 | 264 | } |
duke@435 | 265 | |
duke@435 | 266 | //------------------------------------------- |
duke@435 | 267 | // Insert a Copy before the use |
duke@435 | 268 | |
duke@435 | 269 | // Block and index where the use occurs. |
duke@435 | 270 | int bindex; |
duke@435 | 271 | // Phi input spill-copys belong at the end of the prior block |
duke@435 | 272 | if( use->is_Phi() ) { |
adlertz@5509 | 273 | b = _cfg.get_block_for_node(b->pred(useidx)); |
duke@435 | 274 | bindex = b->end_idx(); |
duke@435 | 275 | } else { |
duke@435 | 276 | // Put the clone just prior to use |
duke@435 | 277 | bindex = b->find_node(use); |
duke@435 | 278 | } |
duke@435 | 279 | |
duke@435 | 280 | Node *spill = get_spillcopy_wide( def, use, useidx ); |
duke@435 | 281 | if( !spill ) return 0; // Bailed out |
duke@435 | 282 | // Insert SpillCopy before the USE, which uses the reaching DEF as |
duke@435 | 283 | // its input, and defs a new live range, which is used by this node. |
duke@435 | 284 | insert_proj( b, bindex, spill, maxlrg++ ); |
duke@435 | 285 | // Use the spill/clone |
duke@435 | 286 | use->set_req(useidx,spill); |
duke@435 | 287 | |
duke@435 | 288 | // return updated live range count |
duke@435 | 289 | return maxlrg; |
duke@435 | 290 | } |
duke@435 | 291 | |
kvn@2048 | 292 | //------------------------------clone_node---------------------------- |
kvn@2048 | 293 | // Clone node with anti dependence check. |
kvn@2048 | 294 | Node* clone_node(Node* def, Block *b, Compile* C) { |
kvn@2048 | 295 | if (def->needs_anti_dependence_check()) { |
kvn@2048 | 296 | #ifdef ASSERT |
kvn@2048 | 297 | if (Verbose) { |
kvn@2048 | 298 | tty->print_cr("RA attempts to clone node with anti_dependence:"); |
kvn@2048 | 299 | def->dump(-1); tty->cr(); |
kvn@2048 | 300 | tty->print_cr("into block:"); |
kvn@2048 | 301 | b->dump(); |
kvn@2048 | 302 | } |
kvn@2048 | 303 | #endif |
kvn@2048 | 304 | if (C->subsume_loads() == true && !C->failing()) { |
kvn@2048 | 305 | // Retry with subsume_loads == false |
kvn@2048 | 306 | // If this is the first failure, the sentinel string will "stick" |
kvn@2048 | 307 | // to the Compile object, and the C2Compiler will see it and retry. |
kvn@2048 | 308 | C->record_failure(C2Compiler::retry_no_subsuming_loads()); |
kvn@2048 | 309 | } else { |
kvn@2048 | 310 | // Bailout without retry |
kvn@2048 | 311 | C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence"); |
kvn@2048 | 312 | } |
kvn@2048 | 313 | return 0; |
kvn@2048 | 314 | } |
kvn@2048 | 315 | return def->clone(); |
kvn@2048 | 316 | } |
kvn@2048 | 317 | |
duke@435 | 318 | //------------------------------split_Rematerialize---------------------------- |
duke@435 | 319 | // Clone a local copy of the def. |
duke@435 | 320 | Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) { |
duke@435 | 321 | // The input live ranges will be stretched to the site of the new |
duke@435 | 322 | // instruction. They might be stretched past a def and will thus |
duke@435 | 323 | // have the old and new values of the same live range alive at the |
duke@435 | 324 | // same time - a definite no-no. Split out private copies of |
duke@435 | 325 | // the inputs. |
duke@435 | 326 | if( def->req() > 1 ) { |
duke@435 | 327 | for( uint i = 1; i < def->req(); i++ ) { |
duke@435 | 328 | Node *in = def->in(i); |
duke@435 | 329 | // Check for single-def (LRG cannot redefined) |
neliasso@4949 | 330 | uint lidx = _lrg_map.live_range_id(in); |
neliasso@4949 | 331 | if (lidx >= _lrg_map.max_lrg_id()) { |
neliasso@4949 | 332 | continue; // Value is a recent spill-copy |
neliasso@4949 | 333 | } |
neliasso@4949 | 334 | if (lrgs(lidx).is_singledef()) { |
neliasso@4949 | 335 | continue; |
neliasso@4949 | 336 | } |
duke@435 | 337 | |
adlertz@5509 | 338 | Block *b_def = _cfg.get_block_for_node(def); |
duke@435 | 339 | int idx_def = b_def->find_node(def); |
duke@435 | 340 | Node *in_spill = get_spillcopy_wide( in, def, i ); |
duke@435 | 341 | if( !in_spill ) return 0; // Bailed out |
duke@435 | 342 | insert_proj(b_def,idx_def,in_spill,maxlrg++); |
duke@435 | 343 | if( b_def == b ) |
duke@435 | 344 | insidx++; |
duke@435 | 345 | def->set_req(i,in_spill); |
duke@435 | 346 | } |
duke@435 | 347 | } |
duke@435 | 348 | |
kvn@2048 | 349 | Node *spill = clone_node(def, b, C); |
kvn@2048 | 350 | if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { |
duke@435 | 351 | // Check when generating nodes |
duke@435 | 352 | return 0; |
duke@435 | 353 | } |
duke@435 | 354 | |
duke@435 | 355 | // See if any inputs are currently being spilled, and take the |
duke@435 | 356 | // latest copy of spilled inputs. |
duke@435 | 357 | if( spill->req() > 1 ) { |
duke@435 | 358 | for( uint i = 1; i < spill->req(); i++ ) { |
duke@435 | 359 | Node *in = spill->in(i); |
neliasso@4949 | 360 | uint lidx = _lrg_map.find_id(in); |
duke@435 | 361 | |
duke@435 | 362 | // Walk backwards thru spill copy node intermediates |
never@730 | 363 | if (walkThru) { |
neliasso@4949 | 364 | while (in->is_SpillCopy() && lidx >= _lrg_map.max_lrg_id()) { |
duke@435 | 365 | in = in->in(1); |
neliasso@4949 | 366 | lidx = _lrg_map.find_id(in); |
duke@435 | 367 | } |
duke@435 | 368 | |
neliasso@4949 | 369 | if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_multidef()) { |
never@730 | 370 | // walkThru found a multidef LRG, which is unsafe to use, so |
never@730 | 371 | // just keep the original def used in the clone. |
never@730 | 372 | in = spill->in(i); |
neliasso@4949 | 373 | lidx = _lrg_map.find_id(in); |
never@730 | 374 | } |
never@730 | 375 | } |
never@730 | 376 | |
neliasso@4949 | 377 | if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).reg() >= LRG::SPILL_REG) { |
duke@435 | 378 | Node *rdef = Reachblock[lrg2reach[lidx]]; |
neliasso@4949 | 379 | if (rdef) { |
neliasso@4949 | 380 | spill->set_req(i, rdef); |
neliasso@4949 | 381 | } |
duke@435 | 382 | } |
duke@435 | 383 | } |
duke@435 | 384 | } |
duke@435 | 385 | |
duke@435 | 386 | |
duke@435 | 387 | assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" ); |
duke@435 | 388 | // Rematerialized op is def->spilled+1 |
duke@435 | 389 | set_was_spilled(spill); |
duke@435 | 390 | if( _spilled_once.test(def->_idx) ) |
duke@435 | 391 | set_was_spilled(spill); |
duke@435 | 392 | |
duke@435 | 393 | insert_proj( b, insidx, spill, maxlrg++ ); |
duke@435 | 394 | #ifdef ASSERT |
duke@435 | 395 | // Increment the counter for this lrg |
duke@435 | 396 | splits.at_put(slidx, splits.at(slidx)+1); |
duke@435 | 397 | #endif |
duke@435 | 398 | // See if the cloned def kills any flags, and copy those kills as well |
duke@435 | 399 | uint i = insidx+1; |
kvn@5543 | 400 | int found_projs = clone_projs( b, i, def, spill, maxlrg); |
kvn@5543 | 401 | if (found_projs > 0) { |
duke@435 | 402 | // Adjust the point where we go hi-pressure |
kvn@5543 | 403 | if (i <= b->_ihrp_index) { |
kvn@5543 | 404 | b->_ihrp_index += found_projs; |
kvn@5543 | 405 | } |
kvn@5543 | 406 | if (i <= b->_fhrp_index) { |
kvn@5543 | 407 | b->_fhrp_index += found_projs; |
kvn@5543 | 408 | } |
duke@435 | 409 | } |
duke@435 | 410 | |
duke@435 | 411 | return spill; |
duke@435 | 412 | } |
duke@435 | 413 | |
duke@435 | 414 | //------------------------------is_high_pressure------------------------------- |
duke@435 | 415 | // Function to compute whether or not this live range is "high pressure" |
duke@435 | 416 | // in this block - whether it spills eagerly or not. |
duke@435 | 417 | bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) { |
duke@435 | 418 | if( lrg->_was_spilled1 ) return true; |
duke@435 | 419 | // Forced spilling due to conflict? Then split only at binding uses |
duke@435 | 420 | // or defs, not for supposed capacity problems. |
duke@435 | 421 | // CNC - Turned off 7/8/99, causes too much spilling |
duke@435 | 422 | // if( lrg->_is_bound ) return false; |
duke@435 | 423 | |
kvn@3882 | 424 | // Use float pressure numbers for vectors. |
kvn@3882 | 425 | bool is_float_or_vector = lrg->_is_float || lrg->_is_vector; |
duke@435 | 426 | // Not yet reached the high-pressure cutoff point, so low pressure |
kvn@3882 | 427 | uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index; |
duke@435 | 428 | if( insidx < hrp_idx ) return false; |
duke@435 | 429 | // Register pressure for the block as a whole depends on reg class |
kvn@3882 | 430 | int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure; |
duke@435 | 431 | // Bound live ranges will split at the binding points first; |
duke@435 | 432 | // Intermediate splits should assume the live range's register set |
duke@435 | 433 | // got "freed up" and that num_regs will become INT_PRESSURE. |
kvn@3882 | 434 | int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE; |
duke@435 | 435 | // Effective register pressure limit. |
duke@435 | 436 | int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs()) |
duke@435 | 437 | ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres; |
duke@435 | 438 | // High pressure if block pressure requires more register freedom |
duke@435 | 439 | // than live range has. |
duke@435 | 440 | return block_pres >= lrg_pres; |
duke@435 | 441 | } |
duke@435 | 442 | |
duke@435 | 443 | |
duke@435 | 444 | //------------------------------prompt_use--------------------------------- |
duke@435 | 445 | // True if lidx is used before any real register is def'd in the block |
duke@435 | 446 | bool PhaseChaitin::prompt_use( Block *b, uint lidx ) { |
neliasso@4949 | 447 | if (lrgs(lidx)._was_spilled2) { |
neliasso@4949 | 448 | return false; |
neliasso@4949 | 449 | } |
duke@435 | 450 | |
duke@435 | 451 | // Scan block for 1st use. |
duke@435 | 452 | for( uint i = 1; i <= b->end_idx(); i++ ) { |
adlertz@5635 | 453 | Node *n = b->get_node(i); |
duke@435 | 454 | // Ignore PHI use, these can be up or down |
neliasso@4949 | 455 | if (n->is_Phi()) { |
neliasso@4949 | 456 | continue; |
neliasso@4949 | 457 | } |
neliasso@4949 | 458 | for (uint j = 1; j < n->req(); j++) { |
neliasso@4949 | 459 | if (_lrg_map.find_id(n->in(j)) == lidx) { |
duke@435 | 460 | return true; // Found 1st use! |
neliasso@4949 | 461 | } |
neliasso@4949 | 462 | } |
neliasso@4949 | 463 | if (n->out_RegMask().is_NotEmpty()) { |
neliasso@4949 | 464 | return false; |
neliasso@4949 | 465 | } |
duke@435 | 466 | } |
duke@435 | 467 | return false; |
duke@435 | 468 | } |
duke@435 | 469 | |
duke@435 | 470 | //------------------------------Split-------------------------------------- |
duke@435 | 471 | //----------Split Routine---------- |
duke@435 | 472 | // ***** NEW SPLITTING HEURISTIC ***** |
duke@435 | 473 | // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there. |
duke@435 | 474 | // Else, no split unless there is a HRP block between a DEF and |
duke@435 | 475 | // one of its uses, and then split at the HRP block. |
duke@435 | 476 | // |
duke@435 | 477 | // USES: If USE is in HRP, split at use to leave main LRG on stack. |
duke@435 | 478 | // Else, hoist LRG back up to register only (ie - split is also DEF) |
duke@435 | 479 | // We will compute a new maxlrg as we go |
kvn@4019 | 480 | uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) { |
duke@435 | 481 | NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); ) |
duke@435 | 482 | |
kvn@4019 | 483 | // Free thread local resources used by this method on exit. |
kvn@4019 | 484 | ResourceMark rm(split_arena); |
kvn@4019 | 485 | |
duke@435 | 486 | uint bidx, pidx, slidx, insidx, inpidx, twoidx; |
duke@435 | 487 | uint non_phi = 1, spill_cnt = 0; |
duke@435 | 488 | Node **Reachblock; |
duke@435 | 489 | Node *n1, *n2, *n3; |
duke@435 | 490 | Node_List *defs,*phis; |
duke@435 | 491 | bool *UPblock; |
duke@435 | 492 | bool u1, u2, u3; |
duke@435 | 493 | Block *b, *pred; |
duke@435 | 494 | PhiNode *phi; |
neliasso@4949 | 495 | GrowableArray<uint> lidxs(split_arena, maxlrg, 0, 0); |
duke@435 | 496 | |
duke@435 | 497 | // Array of counters to count splits per live range |
neliasso@4949 | 498 | GrowableArray<uint> splits(split_arena, maxlrg, 0, 0); |
kvn@4019 | 499 | |
kvn@4019 | 500 | #define NEW_SPLIT_ARRAY(type, size)\ |
kvn@4019 | 501 | (type*) split_arena->allocate_bytes((size) * sizeof(type)) |
duke@435 | 502 | |
duke@435 | 503 | //----------Setup Code---------- |
duke@435 | 504 | // Create a convenient mapping from lrg numbers to reaches/leaves indices |
neliasso@4949 | 505 | uint *lrg2reach = NEW_SPLIT_ARRAY(uint, maxlrg); |
duke@435 | 506 | // Keep track of DEFS & Phis for later passes |
duke@435 | 507 | defs = new Node_List(); |
duke@435 | 508 | phis = new Node_List(); |
duke@435 | 509 | // Gather info on which LRG's are spilling, and build maps |
neliasso@4949 | 510 | for (bidx = 1; bidx < maxlrg; bidx++) { |
neliasso@4949 | 511 | if (lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG) { |
duke@435 | 512 | assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color"); |
duke@435 | 513 | lrg2reach[bidx] = spill_cnt; |
duke@435 | 514 | spill_cnt++; |
duke@435 | 515 | lidxs.append(bidx); |
duke@435 | 516 | #ifdef ASSERT |
duke@435 | 517 | // Initialize the split counts to zero |
duke@435 | 518 | splits.append(0); |
duke@435 | 519 | #endif |
duke@435 | 520 | #ifndef PRODUCT |
duke@435 | 521 | if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 ) |
duke@435 | 522 | tty->print_cr("Warning, 2nd spill of L%d",bidx); |
duke@435 | 523 | #endif |
duke@435 | 524 | } |
duke@435 | 525 | } |
duke@435 | 526 | |
duke@435 | 527 | // Create side arrays for propagating reaching defs info. |
duke@435 | 528 | // Each block needs a node pointer for each spilling live range for the |
duke@435 | 529 | // Def which is live into the block. Phi nodes handle multiple input |
duke@435 | 530 | // Defs by querying the output of their predecessor blocks and resolving |
duke@435 | 531 | // them to a single Def at the phi. The pointer is updated for each |
duke@435 | 532 | // Def in the block, and then becomes the output for the block when |
duke@435 | 533 | // processing of the block is complete. We also need to track whether |
duke@435 | 534 | // a Def is UP or DOWN. UP means that it should get a register (ie - |
duke@435 | 535 | // it is always in LRP regions), and DOWN means that it is probably |
duke@435 | 536 | // on the stack (ie - it crosses HRP regions). |
adlertz@5539 | 537 | Node ***Reaches = NEW_SPLIT_ARRAY( Node**, _cfg.number_of_blocks() + 1); |
adlertz@5539 | 538 | bool **UP = NEW_SPLIT_ARRAY( bool*, _cfg.number_of_blocks() + 1); |
kvn@4019 | 539 | Node **debug_defs = NEW_SPLIT_ARRAY( Node*, spill_cnt ); |
kvn@4019 | 540 | VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt ); |
duke@435 | 541 | |
duke@435 | 542 | // Initialize Reaches & UP |
adlertz@5539 | 543 | for (bidx = 0; bidx < _cfg.number_of_blocks() + 1; bidx++) { |
kvn@4019 | 544 | Reaches[bidx] = NEW_SPLIT_ARRAY( Node*, spill_cnt ); |
kvn@4019 | 545 | UP[bidx] = NEW_SPLIT_ARRAY( bool, spill_cnt ); |
duke@435 | 546 | Node **Reachblock = Reaches[bidx]; |
duke@435 | 547 | bool *UPblock = UP[bidx]; |
duke@435 | 548 | for( slidx = 0; slidx < spill_cnt; slidx++ ) { |
duke@435 | 549 | UPblock[slidx] = true; // Assume they start in registers |
duke@435 | 550 | Reachblock[slidx] = NULL; // Assume that no def is present |
duke@435 | 551 | } |
duke@435 | 552 | } |
duke@435 | 553 | |
kvn@4019 | 554 | #undef NEW_SPLIT_ARRAY |
kvn@4019 | 555 | |
duke@435 | 556 | // Initialize to array of empty vectorsets |
duke@435 | 557 | for( slidx = 0; slidx < spill_cnt; slidx++ ) |
kvn@4019 | 558 | UP_entry[slidx] = new VectorSet(split_arena); |
duke@435 | 559 | |
duke@435 | 560 | //----------PASS 1---------- |
duke@435 | 561 | //----------Propagation & Node Insertion Code---------- |
duke@435 | 562 | // Walk the Blocks in RPO for DEF & USE info |
adlertz@5539 | 563 | for( bidx = 0; bidx < _cfg.number_of_blocks(); bidx++ ) { |
duke@435 | 564 | |
duke@435 | 565 | if (C->check_node_count(spill_cnt, out_of_nodes)) { |
duke@435 | 566 | return 0; |
duke@435 | 567 | } |
duke@435 | 568 | |
adlertz@5539 | 569 | b = _cfg.get_block(bidx); |
duke@435 | 570 | // Reaches & UP arrays for this block |
duke@435 | 571 | Reachblock = Reaches[b->_pre_order]; |
duke@435 | 572 | UPblock = UP[b->_pre_order]; |
duke@435 | 573 | // Reset counter of start of non-Phi nodes in block |
duke@435 | 574 | non_phi = 1; |
duke@435 | 575 | //----------Block Entry Handling---------- |
duke@435 | 576 | // Check for need to insert a new phi |
duke@435 | 577 | // Cycle through this block's predecessors, collecting Reaches |
duke@435 | 578 | // info for each spilled LRG. If they are identical, no phi is |
duke@435 | 579 | // needed. If they differ, check for a phi, and insert if missing, |
duke@435 | 580 | // or update edges if present. Set current block's Reaches set to |
duke@435 | 581 | // be either the phi's or the reaching def, as appropriate. |
duke@435 | 582 | // If no Phi is needed, check if the LRG needs to spill on entry |
duke@435 | 583 | // to the block due to HRP. |
duke@435 | 584 | for( slidx = 0; slidx < spill_cnt; slidx++ ) { |
duke@435 | 585 | // Grab the live range number |
duke@435 | 586 | uint lidx = lidxs.at(slidx); |
duke@435 | 587 | // Do not bother splitting or putting in Phis for single-def |
duke@435 | 588 | // rematerialized live ranges. This happens alot to constants |
duke@435 | 589 | // with long live ranges. |
never@730 | 590 | if( lrgs(lidx).is_singledef() && |
duke@435 | 591 | lrgs(lidx)._def->rematerialize() ) { |
duke@435 | 592 | // reset the Reaches & UP entries |
duke@435 | 593 | Reachblock[slidx] = lrgs(lidx)._def; |
duke@435 | 594 | UPblock[slidx] = true; |
duke@435 | 595 | // Record following instruction in case 'n' rematerializes and |
duke@435 | 596 | // kills flags |
adlertz@5509 | 597 | Block *pred1 = _cfg.get_block_for_node(b->pred(1)); |
duke@435 | 598 | continue; |
duke@435 | 599 | } |
duke@435 | 600 | |
duke@435 | 601 | // Initialize needs_phi and needs_split |
duke@435 | 602 | bool needs_phi = false; |
duke@435 | 603 | bool needs_split = false; |
kvn@765 | 604 | bool has_phi = false; |
duke@435 | 605 | // Walk the predecessor blocks to check inputs for that live range |
duke@435 | 606 | // Grab predecessor block header |
duke@435 | 607 | n1 = b->pred(1); |
duke@435 | 608 | // Grab the appropriate reaching def info for inpidx |
adlertz@5509 | 609 | pred = _cfg.get_block_for_node(n1); |
duke@435 | 610 | pidx = pred->_pre_order; |
duke@435 | 611 | Node **Ltmp = Reaches[pidx]; |
duke@435 | 612 | bool *Utmp = UP[pidx]; |
duke@435 | 613 | n1 = Ltmp[slidx]; |
duke@435 | 614 | u1 = Utmp[slidx]; |
duke@435 | 615 | // Initialize node for saving type info |
duke@435 | 616 | n3 = n1; |
duke@435 | 617 | u3 = u1; |
duke@435 | 618 | |
duke@435 | 619 | // Compare inputs to see if a Phi is needed |
duke@435 | 620 | for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) { |
duke@435 | 621 | // Grab predecessor block headers |
duke@435 | 622 | n2 = b->pred(inpidx); |
duke@435 | 623 | // Grab the appropriate reaching def info for inpidx |
adlertz@5509 | 624 | pred = _cfg.get_block_for_node(n2); |
duke@435 | 625 | pidx = pred->_pre_order; |
duke@435 | 626 | Ltmp = Reaches[pidx]; |
duke@435 | 627 | Utmp = UP[pidx]; |
duke@435 | 628 | n2 = Ltmp[slidx]; |
duke@435 | 629 | u2 = Utmp[slidx]; |
duke@435 | 630 | // For each LRG, decide if a phi is necessary |
duke@435 | 631 | if( n1 != n2 ) { |
duke@435 | 632 | needs_phi = true; |
duke@435 | 633 | } |
duke@435 | 634 | // See if the phi has mismatched inputs, UP vs. DOWN |
duke@435 | 635 | if( n1 && n2 && (u1 != u2) ) { |
duke@435 | 636 | needs_split = true; |
duke@435 | 637 | } |
duke@435 | 638 | // Move n2/u2 to n1/u1 for next iteration |
duke@435 | 639 | n1 = n2; |
duke@435 | 640 | u1 = u2; |
duke@435 | 641 | // Preserve a non-NULL predecessor for later type referencing |
duke@435 | 642 | if( (n3 == NULL) && (n2 != NULL) ){ |
duke@435 | 643 | n3 = n2; |
duke@435 | 644 | u3 = u2; |
duke@435 | 645 | } |
duke@435 | 646 | } // End for all potential Phi inputs |
duke@435 | 647 | |
kvn@765 | 648 | // check block for appropriate phinode & update edges |
kvn@765 | 649 | for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { |
adlertz@5635 | 650 | n1 = b->get_node(insidx); |
kvn@765 | 651 | // bail if this is not a phi |
kvn@765 | 652 | phi = n1->is_Phi() ? n1->as_Phi() : NULL; |
kvn@765 | 653 | if( phi == NULL ) { |
kvn@765 | 654 | // Keep track of index of first non-PhiNode instruction in block |
kvn@765 | 655 | non_phi = insidx; |
kvn@765 | 656 | // break out of the for loop as we have handled all phi nodes |
kvn@765 | 657 | break; |
kvn@765 | 658 | } |
kvn@765 | 659 | // must be looking at a phi |
neliasso@4949 | 660 | if (_lrg_map.find_id(n1) == lidxs.at(slidx)) { |
kvn@765 | 661 | // found the necessary phi |
kvn@765 | 662 | needs_phi = false; |
kvn@765 | 663 | has_phi = true; |
kvn@765 | 664 | // initialize the Reaches entry for this LRG |
kvn@765 | 665 | Reachblock[slidx] = phi; |
kvn@765 | 666 | break; |
kvn@765 | 667 | } // end if found correct phi |
kvn@765 | 668 | } // end for all phi's |
kvn@765 | 669 | |
kvn@765 | 670 | // If a phi is needed or exist, check for it |
kvn@765 | 671 | if( needs_phi || has_phi ) { |
duke@435 | 672 | // add new phinode if one not already found |
duke@435 | 673 | if( needs_phi ) { |
duke@435 | 674 | // create a new phi node and insert it into the block |
duke@435 | 675 | // type is taken from left over pointer to a predecessor |
duke@435 | 676 | assert(n3,"No non-NULL reaching DEF for a Phi"); |
kvn@4115 | 677 | phi = new (C) PhiNode(b->head(), n3->bottom_type()); |
duke@435 | 678 | // initialize the Reaches entry for this LRG |
duke@435 | 679 | Reachblock[slidx] = phi; |
duke@435 | 680 | |
duke@435 | 681 | // add node to block & node_to_block mapping |
neliasso@4949 | 682 | insert_proj(b, insidx++, phi, maxlrg++); |
duke@435 | 683 | non_phi++; |
duke@435 | 684 | // Reset new phi's mapping to be the spilling live range |
neliasso@4949 | 685 | _lrg_map.map(phi->_idx, lidx); |
neliasso@4949 | 686 | assert(_lrg_map.find_id(phi) == lidx, "Bad update on Union-Find mapping"); |
duke@435 | 687 | } // end if not found correct phi |
duke@435 | 688 | // Here you have either found or created the Phi, so record it |
duke@435 | 689 | assert(phi != NULL,"Must have a Phi Node here"); |
duke@435 | 690 | phis->push(phi); |
duke@435 | 691 | // PhiNodes should either force the LRG UP or DOWN depending |
duke@435 | 692 | // on its inputs and the register pressure in the Phi's block. |
duke@435 | 693 | UPblock[slidx] = true; // Assume new DEF is UP |
duke@435 | 694 | // If entering a high-pressure area with no immediate use, |
duke@435 | 695 | // assume Phi is DOWN |
duke@435 | 696 | if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) ) |
duke@435 | 697 | UPblock[slidx] = false; |
duke@435 | 698 | // If we are not split up/down and all inputs are down, then we |
duke@435 | 699 | // are down |
duke@435 | 700 | if( !needs_split && !u3 ) |
duke@435 | 701 | UPblock[slidx] = false; |
duke@435 | 702 | } // end if phi is needed |
duke@435 | 703 | |
duke@435 | 704 | // Do not need a phi, so grab the reaching DEF |
duke@435 | 705 | else { |
duke@435 | 706 | // Grab predecessor block header |
duke@435 | 707 | n1 = b->pred(1); |
duke@435 | 708 | // Grab the appropriate reaching def info for k |
adlertz@5509 | 709 | pred = _cfg.get_block_for_node(n1); |
duke@435 | 710 | pidx = pred->_pre_order; |
duke@435 | 711 | Node **Ltmp = Reaches[pidx]; |
duke@435 | 712 | bool *Utmp = UP[pidx]; |
duke@435 | 713 | // reset the Reaches & UP entries |
duke@435 | 714 | Reachblock[slidx] = Ltmp[slidx]; |
duke@435 | 715 | UPblock[slidx] = Utmp[slidx]; |
duke@435 | 716 | } // end else no Phi is needed |
duke@435 | 717 | } // end for all spilling live ranges |
duke@435 | 718 | // DEBUG |
duke@435 | 719 | #ifndef PRODUCT |
duke@435 | 720 | if(trace_spilling()) { |
duke@435 | 721 | tty->print("/`\nBlock %d: ", b->_pre_order); |
duke@435 | 722 | tty->print("Reaching Definitions after Phi handling\n"); |
duke@435 | 723 | for( uint x = 0; x < spill_cnt; x++ ) { |
duke@435 | 724 | tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]); |
duke@435 | 725 | if( Reachblock[x] ) |
duke@435 | 726 | Reachblock[x]->dump(); |
duke@435 | 727 | else |
duke@435 | 728 | tty->print("Undefined\n"); |
duke@435 | 729 | } |
duke@435 | 730 | } |
duke@435 | 731 | #endif |
duke@435 | 732 | |
duke@435 | 733 | //----------Non-Phi Node Splitting---------- |
duke@435 | 734 | // Since phi-nodes have now been handled, the Reachblock array for this |
duke@435 | 735 | // block is initialized with the correct starting value for the defs which |
duke@435 | 736 | // reach non-phi instructions in this block. Thus, process non-phi |
duke@435 | 737 | // instructions normally, inserting SpillCopy nodes for all spill |
duke@435 | 738 | // locations. |
duke@435 | 739 | |
duke@435 | 740 | // Memoize any DOWN reaching definitions for use as DEBUG info |
duke@435 | 741 | for( insidx = 0; insidx < spill_cnt; insidx++ ) { |
duke@435 | 742 | debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx]; |
duke@435 | 743 | if( UPblock[insidx] ) // Memoize UP decision at block start |
duke@435 | 744 | UP_entry[insidx]->set( b->_pre_order ); |
duke@435 | 745 | } |
duke@435 | 746 | |
duke@435 | 747 | //----------Walk Instructions in the Block and Split---------- |
duke@435 | 748 | // For all non-phi instructions in the block |
duke@435 | 749 | for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { |
adlertz@5635 | 750 | Node *n = b->get_node(insidx); |
duke@435 | 751 | // Find the defining Node's live range index |
neliasso@4949 | 752 | uint defidx = _lrg_map.find_id(n); |
duke@435 | 753 | uint cnt = n->req(); |
duke@435 | 754 | |
neliasso@4949 | 755 | if (n->is_Phi()) { |
duke@435 | 756 | // Skip phi nodes after removing dead copies. |
neliasso@4949 | 757 | if (defidx < _lrg_map.max_lrg_id()) { |
duke@435 | 758 | // Check for useless Phis. These appear if we spill, then |
duke@435 | 759 | // coalesce away copies. Dont touch Phis in spilling live |
duke@435 | 760 | // ranges; they are busy getting modifed in this pass. |
duke@435 | 761 | if( lrgs(defidx).reg() < LRG::SPILL_REG ) { |
duke@435 | 762 | uint i; |
duke@435 | 763 | Node *u = NULL; |
duke@435 | 764 | // Look for the Phi merging 2 unique inputs |
duke@435 | 765 | for( i = 1; i < cnt; i++ ) { |
duke@435 | 766 | // Ignore repeats and self |
duke@435 | 767 | if( n->in(i) != u && n->in(i) != n ) { |
duke@435 | 768 | // Found a unique input |
duke@435 | 769 | if( u != NULL ) // If it's the 2nd, bail out |
duke@435 | 770 | break; |
duke@435 | 771 | u = n->in(i); // Else record it |
duke@435 | 772 | } |
duke@435 | 773 | } |
duke@435 | 774 | assert( u, "at least 1 valid input expected" ); |
neliasso@4949 | 775 | if (i >= cnt) { // Found one unique input |
neliasso@4949 | 776 | assert(_lrg_map.find_id(n) == _lrg_map.find_id(u), "should be the same lrg"); |
duke@435 | 777 | n->replace_by(u); // Then replace with unique input |
bharadwaj@4315 | 778 | n->disconnect_inputs(NULL, C); |
adlertz@5635 | 779 | b->remove_node(insidx); |
duke@435 | 780 | insidx--; |
duke@435 | 781 | b->_ihrp_index--; |
duke@435 | 782 | b->_fhrp_index--; |
duke@435 | 783 | } |
duke@435 | 784 | } |
duke@435 | 785 | } |
duke@435 | 786 | continue; |
duke@435 | 787 | } |
duke@435 | 788 | assert( insidx > b->_ihrp_index || |
duke@435 | 789 | (b->_reg_pressure < (uint)INTPRESSURE) || |
duke@435 | 790 | b->_ihrp_index > 4000000 || |
duke@435 | 791 | b->_ihrp_index >= b->end_idx() || |
adlertz@5635 | 792 | !b->get_node(b->_ihrp_index)->is_Proj(), "" ); |
duke@435 | 793 | assert( insidx > b->_fhrp_index || |
duke@435 | 794 | (b->_freg_pressure < (uint)FLOATPRESSURE) || |
duke@435 | 795 | b->_fhrp_index > 4000000 || |
duke@435 | 796 | b->_fhrp_index >= b->end_idx() || |
adlertz@5635 | 797 | !b->get_node(b->_fhrp_index)->is_Proj(), "" ); |
duke@435 | 798 | |
duke@435 | 799 | // ********** Handle Crossing HRP Boundry ********** |
duke@435 | 800 | if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) { |
duke@435 | 801 | for( slidx = 0; slidx < spill_cnt; slidx++ ) { |
twisti@1040 | 802 | // Check for need to split at HRP boundary - split if UP |
duke@435 | 803 | n1 = Reachblock[slidx]; |
duke@435 | 804 | // bail out if no reaching DEF |
duke@435 | 805 | if( n1 == NULL ) continue; |
duke@435 | 806 | // bail out if live range is 'isolated' around inner loop |
duke@435 | 807 | uint lidx = lidxs.at(slidx); |
duke@435 | 808 | // If live range is currently UP |
duke@435 | 809 | if( UPblock[slidx] ) { |
duke@435 | 810 | // set location to insert spills at |
duke@435 | 811 | // SPLIT DOWN HERE - NO CISC SPILL |
duke@435 | 812 | if( is_high_pressure( b, &lrgs(lidx), insidx ) && |
duke@435 | 813 | !n1->rematerialize() ) { |
duke@435 | 814 | // If there is already a valid stack definition available, use it |
duke@435 | 815 | if( debug_defs[slidx] != NULL ) { |
duke@435 | 816 | Reachblock[slidx] = debug_defs[slidx]; |
duke@435 | 817 | } |
duke@435 | 818 | else { |
duke@435 | 819 | // Insert point is just past last use or def in the block |
duke@435 | 820 | int insert_point = insidx-1; |
duke@435 | 821 | while( insert_point > 0 ) { |
adlertz@5635 | 822 | Node *n = b->get_node(insert_point); |
duke@435 | 823 | // Hit top of block? Quit going backwards |
neliasso@4949 | 824 | if (n->is_Phi()) { |
neliasso@4949 | 825 | break; |
neliasso@4949 | 826 | } |
duke@435 | 827 | // Found a def? Better split after it. |
neliasso@4949 | 828 | if (_lrg_map.live_range_id(n) == lidx) { |
neliasso@4949 | 829 | break; |
neliasso@4949 | 830 | } |
duke@435 | 831 | // Look for a use |
duke@435 | 832 | uint i; |
neliasso@4949 | 833 | for( i = 1; i < n->req(); i++ ) { |
neliasso@4949 | 834 | if (_lrg_map.live_range_id(n->in(i)) == lidx) { |
duke@435 | 835 | break; |
neliasso@4949 | 836 | } |
neliasso@4949 | 837 | } |
duke@435 | 838 | // Found a use? Better split after it. |
neliasso@4949 | 839 | if (i < n->req()) { |
neliasso@4949 | 840 | break; |
neliasso@4949 | 841 | } |
duke@435 | 842 | insert_point--; |
duke@435 | 843 | } |
kvn@3882 | 844 | uint orig_eidx = b->end_idx(); |
duke@435 | 845 | maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx); |
duke@435 | 846 | // If it wasn't split bail |
duke@435 | 847 | if (!maxlrg) { |
duke@435 | 848 | return 0; |
duke@435 | 849 | } |
kvn@3882 | 850 | // Spill of NULL check mem op goes into the following block. |
neliasso@4949 | 851 | if (b->end_idx() > orig_eidx) { |
kvn@3882 | 852 | insidx++; |
neliasso@4949 | 853 | } |
duke@435 | 854 | } |
duke@435 | 855 | // This is a new DEF, so update UP |
duke@435 | 856 | UPblock[slidx] = false; |
duke@435 | 857 | #ifndef PRODUCT |
duke@435 | 858 | // DEBUG |
duke@435 | 859 | if( trace_spilling() ) { |
duke@435 | 860 | tty->print("\nNew Split DOWN DEF of Spill Idx "); |
duke@435 | 861 | tty->print("%d, UP %d:\n",slidx,false); |
duke@435 | 862 | n1->dump(); |
duke@435 | 863 | } |
duke@435 | 864 | #endif |
duke@435 | 865 | } |
duke@435 | 866 | } // end if LRG is UP |
duke@435 | 867 | } // end for all spilling live ranges |
adlertz@5635 | 868 | assert( b->get_node(insidx) == n, "got insidx set incorrectly" ); |
duke@435 | 869 | } // end if crossing HRP Boundry |
duke@435 | 870 | |
duke@435 | 871 | // If the LRG index is oob, then this is a new spillcopy, skip it. |
neliasso@4949 | 872 | if (defidx >= _lrg_map.max_lrg_id()) { |
duke@435 | 873 | continue; |
duke@435 | 874 | } |
duke@435 | 875 | LRG &deflrg = lrgs(defidx); |
duke@435 | 876 | uint copyidx = n->is_Copy(); |
duke@435 | 877 | // Remove coalesced copy from CFG |
neliasso@4949 | 878 | if (copyidx && defidx == _lrg_map.live_range_id(n->in(copyidx))) { |
duke@435 | 879 | n->replace_by( n->in(copyidx) ); |
duke@435 | 880 | n->set_req( copyidx, NULL ); |
adlertz@5635 | 881 | b->remove_node(insidx--); |
duke@435 | 882 | b->_ihrp_index--; // Adjust the point where we go hi-pressure |
duke@435 | 883 | b->_fhrp_index--; |
duke@435 | 884 | continue; |
duke@435 | 885 | } |
duke@435 | 886 | |
duke@435 | 887 | #define DERIVED 0 |
duke@435 | 888 | |
duke@435 | 889 | // ********** Handle USES ********** |
duke@435 | 890 | bool nullcheck = false; |
duke@435 | 891 | // Implicit null checks never use the spilled value |
duke@435 | 892 | if( n->is_MachNullCheck() ) |
duke@435 | 893 | nullcheck = true; |
duke@435 | 894 | if( !nullcheck ) { |
duke@435 | 895 | // Search all inputs for a Spill-USE |
duke@435 | 896 | JVMState* jvms = n->jvms(); |
duke@435 | 897 | uint oopoff = jvms ? jvms->oopoff() : cnt; |
duke@435 | 898 | uint old_last = cnt - 1; |
duke@435 | 899 | for( inpidx = 1; inpidx < cnt; inpidx++ ) { |
duke@435 | 900 | // Derived/base pairs may be added to our inputs during this loop. |
duke@435 | 901 | // If inpidx > old_last, then one of these new inputs is being |
duke@435 | 902 | // handled. Skip the derived part of the pair, but process |
duke@435 | 903 | // the base like any other input. |
neliasso@4949 | 904 | if (inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED) { |
duke@435 | 905 | continue; // skip derived_debug added below |
duke@435 | 906 | } |
duke@435 | 907 | // Get lidx of input |
neliasso@4949 | 908 | uint useidx = _lrg_map.find_id(n->in(inpidx)); |
duke@435 | 909 | // Not a brand-new split, and it is a spill use |
neliasso@4949 | 910 | if (useidx < _lrg_map.max_lrg_id() && lrgs(useidx).reg() >= LRG::SPILL_REG) { |
duke@435 | 911 | // Check for valid reaching DEF |
duke@435 | 912 | slidx = lrg2reach[useidx]; |
duke@435 | 913 | Node *def = Reachblock[slidx]; |
duke@435 | 914 | assert( def != NULL, "Using Undefined Value in Split()\n"); |
duke@435 | 915 | |
duke@435 | 916 | // (+++) %%%% remove this in favor of pre-pass in matcher.cpp |
duke@435 | 917 | // monitor references do not care where they live, so just hook |
duke@435 | 918 | if ( jvms && jvms->is_monitor_use(inpidx) ) { |
duke@435 | 919 | // The effect of this clone is to drop the node out of the block, |
duke@435 | 920 | // so that the allocator does not see it anymore, and therefore |
duke@435 | 921 | // does not attempt to assign it a register. |
kvn@2048 | 922 | def = clone_node(def, b, C); |
kvn@2048 | 923 | if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { |
kvn@2048 | 924 | return 0; |
kvn@2048 | 925 | } |
neliasso@4949 | 926 | _lrg_map.extend(def->_idx, 0); |
adlertz@5509 | 927 | _cfg.map_node_to_block(def, b); |
duke@435 | 928 | n->set_req(inpidx, def); |
duke@435 | 929 | continue; |
duke@435 | 930 | } |
duke@435 | 931 | |
duke@435 | 932 | // Rematerializable? Then clone def at use site instead |
duke@435 | 933 | // of store/load |
duke@435 | 934 | if( def->rematerialize() ) { |
adlertz@5635 | 935 | int old_size = b->number_of_nodes(); |
duke@435 | 936 | def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true ); |
duke@435 | 937 | if( !def ) return 0; // Bail out |
adlertz@5635 | 938 | insidx += b->number_of_nodes()-old_size; |
duke@435 | 939 | } |
duke@435 | 940 | |
duke@435 | 941 | MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL; |
duke@435 | 942 | // Base pointers and oopmap references do not care where they live. |
duke@435 | 943 | if ((inpidx >= oopoff) || |
duke@435 | 944 | (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) { |
duke@435 | 945 | if (def->rematerialize() && lrgs(useidx)._was_spilled2) { |
duke@435 | 946 | // This def has been rematerialized a couple of times without |
duke@435 | 947 | // progress. It doesn't care if it lives UP or DOWN, so |
duke@435 | 948 | // spill it down now. |
duke@435 | 949 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); |
duke@435 | 950 | // If it wasn't split bail |
duke@435 | 951 | if (!maxlrg) { |
duke@435 | 952 | return 0; |
duke@435 | 953 | } |
duke@435 | 954 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 955 | } else { |
duke@435 | 956 | // Just hook the def edge |
duke@435 | 957 | n->set_req(inpidx, def); |
duke@435 | 958 | } |
duke@435 | 959 | |
duke@435 | 960 | if (inpidx >= oopoff) { |
duke@435 | 961 | // After oopoff, we have derived/base pairs. We must mention all |
duke@435 | 962 | // derived pointers here as derived/base pairs for GC. If the |
duke@435 | 963 | // derived value is spilling and we have a copy both in Reachblock |
duke@435 | 964 | // (called here 'def') and debug_defs[slidx] we need to mention |
duke@435 | 965 | // both in derived/base pairs or kill one. |
duke@435 | 966 | Node *derived_debug = debug_defs[slidx]; |
duke@435 | 967 | if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base? |
duke@435 | 968 | mach && mach->ideal_Opcode() != Op_Halt && |
duke@435 | 969 | derived_debug != NULL && |
duke@435 | 970 | derived_debug != def ) { // Actual 2nd value appears |
duke@435 | 971 | // We have already set 'def' as a derived value. |
duke@435 | 972 | // Also set debug_defs[slidx] as a derived value. |
duke@435 | 973 | uint k; |
duke@435 | 974 | for( k = oopoff; k < cnt; k += 2 ) |
duke@435 | 975 | if( n->in(k) == derived_debug ) |
duke@435 | 976 | break; // Found an instance of debug derived |
duke@435 | 977 | if( k == cnt ) {// No instance of debug_defs[slidx] |
duke@435 | 978 | // Add a derived/base pair to cover the debug info. |
duke@435 | 979 | // We have to process the added base later since it is not |
duke@435 | 980 | // handled yet at this point but skip derived part. |
duke@435 | 981 | assert(((n->req() - oopoff) & 1) == DERIVED, |
duke@435 | 982 | "must match skip condition above"); |
duke@435 | 983 | n->add_req( derived_debug ); // this will be skipped above |
duke@435 | 984 | n->add_req( n->in(inpidx+1) ); // this will be processed |
duke@435 | 985 | // Increment cnt to handle added input edges on |
duke@435 | 986 | // subsequent iterations. |
duke@435 | 987 | cnt += 2; |
duke@435 | 988 | } |
duke@435 | 989 | } |
duke@435 | 990 | } |
duke@435 | 991 | continue; |
duke@435 | 992 | } |
duke@435 | 993 | // Special logic for DEBUG info |
duke@435 | 994 | if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) { |
duke@435 | 995 | uint debug_start = jvms->debug_start(); |
duke@435 | 996 | // If this is debug info use & there is a reaching DOWN def |
duke@435 | 997 | if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) { |
duke@435 | 998 | assert(inpidx < oopoff, "handle only debug info here"); |
duke@435 | 999 | // Just hook it in & move on |
duke@435 | 1000 | n->set_req(inpidx, debug_defs[slidx]); |
duke@435 | 1001 | // (Note that this can make two sides of a split live at the |
duke@435 | 1002 | // same time: The debug def on stack, and another def in a |
duke@435 | 1003 | // register. The GC needs to know about both of them, but any |
duke@435 | 1004 | // derived pointers after oopoff will refer to only one of the |
duke@435 | 1005 | // two defs and the GC would therefore miss the other. Thus |
duke@435 | 1006 | // this hack is only allowed for debug info which is Java state |
duke@435 | 1007 | // and therefore never a derived pointer.) |
duke@435 | 1008 | continue; |
duke@435 | 1009 | } |
duke@435 | 1010 | } |
duke@435 | 1011 | // Grab register mask info |
duke@435 | 1012 | const RegMask &dmask = def->out_RegMask(); |
duke@435 | 1013 | const RegMask &umask = n->in_RegMask(inpidx); |
kvn@3882 | 1014 | bool is_vect = RegMask::is_vector(def->ideal_reg()); |
duke@435 | 1015 | assert(inpidx < oopoff, "cannot use-split oop map info"); |
duke@435 | 1016 | |
duke@435 | 1017 | bool dup = UPblock[slidx]; |
duke@435 | 1018 | bool uup = umask.is_UP(); |
duke@435 | 1019 | |
duke@435 | 1020 | // Need special logic to handle bound USES. Insert a split at this |
duke@435 | 1021 | // bound use if we can't rematerialize the def, or if we need the |
duke@435 | 1022 | // split to form a misaligned pair. |
duke@435 | 1023 | if( !umask.is_AllStack() && |
duke@435 | 1024 | (int)umask.Size() <= lrgs(useidx).num_regs() && |
duke@435 | 1025 | (!def->rematerialize() || |
kvn@3882 | 1026 | !is_vect && umask.is_misaligned_pair())) { |
duke@435 | 1027 | // These need a Split regardless of overlap or pressure |
duke@435 | 1028 | // SPLIT - NO DEF - NO CISC SPILL |
duke@435 | 1029 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); |
duke@435 | 1030 | // If it wasn't split bail |
duke@435 | 1031 | if (!maxlrg) { |
duke@435 | 1032 | return 0; |
duke@435 | 1033 | } |
duke@435 | 1034 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 1035 | continue; |
duke@435 | 1036 | } |
never@2085 | 1037 | |
kvn@3040 | 1038 | if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) { |
never@2085 | 1039 | // The use at the call can force the def down so insert |
never@2085 | 1040 | // a split before the use to allow the def more freedom. |
never@2085 | 1041 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); |
never@2085 | 1042 | // If it wasn't split bail |
never@2085 | 1043 | if (!maxlrg) { |
never@2085 | 1044 | return 0; |
never@2085 | 1045 | } |
never@2085 | 1046 | insidx++; // Reset iterator to skip USE side split |
never@2085 | 1047 | continue; |
never@2085 | 1048 | } |
never@2085 | 1049 | |
duke@435 | 1050 | // Here is the logic chart which describes USE Splitting: |
duke@435 | 1051 | // 0 = false or DOWN, 1 = true or UP |
duke@435 | 1052 | // |
duke@435 | 1053 | // Overlap | DEF | USE | Action |
duke@435 | 1054 | //------------------------------------------------------- |
duke@435 | 1055 | // 0 | 0 | 0 | Copy - mem -> mem |
duke@435 | 1056 | // 0 | 0 | 1 | Split-UP - Check HRP |
duke@435 | 1057 | // 0 | 1 | 0 | Split-DOWN - Debug Info? |
duke@435 | 1058 | // 0 | 1 | 1 | Copy - reg -> reg |
duke@435 | 1059 | // 1 | 0 | 0 | Reset Input Edge (no Split) |
duke@435 | 1060 | // 1 | 0 | 1 | Split-UP - Check HRP |
duke@435 | 1061 | // 1 | 1 | 0 | Split-DOWN - Debug Info? |
duke@435 | 1062 | // 1 | 1 | 1 | Reset Input Edge (no Split) |
duke@435 | 1063 | // |
duke@435 | 1064 | // So, if (dup == uup), then overlap test determines action, |
duke@435 | 1065 | // with true being no split, and false being copy. Else, |
duke@435 | 1066 | // if DEF is DOWN, Split-UP, and check HRP to decide on |
duke@435 | 1067 | // resetting DEF. Finally if DEF is UP, Split-DOWN, with |
duke@435 | 1068 | // special handling for Debug Info. |
duke@435 | 1069 | if( dup == uup ) { |
duke@435 | 1070 | if( dmask.overlap(umask) ) { |
duke@435 | 1071 | // Both are either up or down, and there is overlap, No Split |
duke@435 | 1072 | n->set_req(inpidx, def); |
duke@435 | 1073 | } |
duke@435 | 1074 | else { // Both are either up or down, and there is no overlap |
duke@435 | 1075 | if( dup ) { // If UP, reg->reg copy |
duke@435 | 1076 | // COPY ACROSS HERE - NO DEF - NO CISC SPILL |
duke@435 | 1077 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); |
duke@435 | 1078 | // If it wasn't split bail |
duke@435 | 1079 | if (!maxlrg) { |
duke@435 | 1080 | return 0; |
duke@435 | 1081 | } |
duke@435 | 1082 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 1083 | } |
duke@435 | 1084 | else { // DOWN, mem->mem copy |
duke@435 | 1085 | // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL |
duke@435 | 1086 | // First Split-UP to move value into Register |
duke@435 | 1087 | uint def_ideal = def->ideal_reg(); |
duke@435 | 1088 | const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; |
duke@435 | 1089 | Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); |
duke@435 | 1090 | insert_proj( b, insidx, spill, maxlrg ); |
duke@435 | 1091 | // Then Split-DOWN as if previous Split was DEF |
duke@435 | 1092 | maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); |
duke@435 | 1093 | // If it wasn't split bail |
duke@435 | 1094 | if (!maxlrg) { |
duke@435 | 1095 | return 0; |
duke@435 | 1096 | } |
duke@435 | 1097 | insidx += 2; // Reset iterator to skip USE side splits |
duke@435 | 1098 | } |
duke@435 | 1099 | } // End else no overlap |
duke@435 | 1100 | } // End if dup == uup |
duke@435 | 1101 | // dup != uup, so check dup for direction of Split |
duke@435 | 1102 | else { |
duke@435 | 1103 | if( dup ) { // If UP, Split-DOWN and check Debug Info |
duke@435 | 1104 | // If this node is already a SpillCopy, just patch the edge |
duke@435 | 1105 | // except the case of spilling to stack. |
duke@435 | 1106 | if( n->is_SpillCopy() ) { |
duke@435 | 1107 | RegMask tmp_rm(umask); |
duke@435 | 1108 | tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask); |
duke@435 | 1109 | if( dmask.overlap(tmp_rm) ) { |
duke@435 | 1110 | if( def != n->in(inpidx) ) { |
duke@435 | 1111 | n->set_req(inpidx, def); |
duke@435 | 1112 | } |
duke@435 | 1113 | continue; |
duke@435 | 1114 | } |
duke@435 | 1115 | } |
duke@435 | 1116 | // COPY DOWN HERE - NO DEF - NO CISC SPILL |
duke@435 | 1117 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); |
duke@435 | 1118 | // If it wasn't split bail |
duke@435 | 1119 | if (!maxlrg) { |
duke@435 | 1120 | return 0; |
duke@435 | 1121 | } |
duke@435 | 1122 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 1123 | // Check for debug-info split. Capture it for later |
duke@435 | 1124 | // debug splits of the same value |
duke@435 | 1125 | if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff) |
duke@435 | 1126 | debug_defs[slidx] = n->in(inpidx); |
duke@435 | 1127 | |
duke@435 | 1128 | } |
duke@435 | 1129 | else { // DOWN, Split-UP and check register pressure |
duke@435 | 1130 | if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { |
duke@435 | 1131 | // COPY UP HERE - NO DEF - CISC SPILL |
duke@435 | 1132 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); |
duke@435 | 1133 | // If it wasn't split bail |
duke@435 | 1134 | if (!maxlrg) { |
duke@435 | 1135 | return 0; |
duke@435 | 1136 | } |
duke@435 | 1137 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 1138 | } else { // LRP |
duke@435 | 1139 | // COPY UP HERE - WITH DEF - NO CISC SPILL |
duke@435 | 1140 | maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); |
duke@435 | 1141 | // If it wasn't split bail |
duke@435 | 1142 | if (!maxlrg) { |
duke@435 | 1143 | return 0; |
duke@435 | 1144 | } |
duke@435 | 1145 | // Flag this lift-up in a low-pressure block as |
duke@435 | 1146 | // already-spilled, so if it spills again it will |
duke@435 | 1147 | // spill hard (instead of not spilling hard and |
duke@435 | 1148 | // coalescing away). |
duke@435 | 1149 | set_was_spilled(n->in(inpidx)); |
duke@435 | 1150 | // Since this is a new DEF, update Reachblock & UP |
duke@435 | 1151 | Reachblock[slidx] = n->in(inpidx); |
duke@435 | 1152 | UPblock[slidx] = true; |
duke@435 | 1153 | insidx++; // Reset iterator to skip USE side split |
duke@435 | 1154 | } |
duke@435 | 1155 | } // End else DOWN |
duke@435 | 1156 | } // End dup != uup |
duke@435 | 1157 | } // End if Spill USE |
duke@435 | 1158 | } // End For All Inputs |
duke@435 | 1159 | } // End If not nullcheck |
duke@435 | 1160 | |
duke@435 | 1161 | // ********** Handle DEFS ********** |
duke@435 | 1162 | // DEFS either Split DOWN in HRP regions or when the LRG is bound, or |
duke@435 | 1163 | // just reset the Reaches info in LRP regions. DEFS must always update |
duke@435 | 1164 | // UP info. |
duke@435 | 1165 | if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled? |
duke@435 | 1166 | uint slidx = lrg2reach[defidx]; |
duke@435 | 1167 | // Add to defs list for later assignment of new live range number |
duke@435 | 1168 | defs->push(n); |
duke@435 | 1169 | // Set a flag on the Node indicating it has already spilled. |
duke@435 | 1170 | // Only do it for capacity spills not conflict spills. |
duke@435 | 1171 | if( !deflrg._direct_conflict ) |
duke@435 | 1172 | set_was_spilled(n); |
duke@435 | 1173 | assert(!n->is_Phi(),"Cannot insert Phi into DEFS list"); |
duke@435 | 1174 | // Grab UP info for DEF |
duke@435 | 1175 | const RegMask &dmask = n->out_RegMask(); |
duke@435 | 1176 | bool defup = dmask.is_UP(); |
kvn@3882 | 1177 | int ireg = n->ideal_reg(); |
kvn@3882 | 1178 | bool is_vect = RegMask::is_vector(ireg); |
duke@435 | 1179 | // Only split at Def if this is a HRP block or bound (and spilled once) |
duke@435 | 1180 | if( !n->rematerialize() && |
kvn@3882 | 1181 | (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) && |
kvn@3882 | 1182 | (deflrg._direct_conflict || deflrg._must_spill)) || |
duke@435 | 1183 | // Check for LRG being up in a register and we are inside a high |
duke@435 | 1184 | // pressure area. Spill it down immediately. |
duke@435 | 1185 | (defup && is_high_pressure(b,&deflrg,insidx))) ) { |
duke@435 | 1186 | assert( !n->rematerialize(), "" ); |
duke@435 | 1187 | assert( !n->is_SpillCopy(), "" ); |
duke@435 | 1188 | // Do a split at the def site. |
duke@435 | 1189 | maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx ); |
duke@435 | 1190 | // If it wasn't split bail |
duke@435 | 1191 | if (!maxlrg) { |
duke@435 | 1192 | return 0; |
duke@435 | 1193 | } |
duke@435 | 1194 | // Split DEF's Down |
duke@435 | 1195 | UPblock[slidx] = 0; |
duke@435 | 1196 | #ifndef PRODUCT |
duke@435 | 1197 | // DEBUG |
duke@435 | 1198 | if( trace_spilling() ) { |
duke@435 | 1199 | tty->print("\nNew Split DOWN DEF of Spill Idx "); |
duke@435 | 1200 | tty->print("%d, UP %d:\n",slidx,false); |
duke@435 | 1201 | n->dump(); |
duke@435 | 1202 | } |
duke@435 | 1203 | #endif |
duke@435 | 1204 | } |
duke@435 | 1205 | else { // Neither bound nor HRP, must be LRP |
duke@435 | 1206 | // otherwise, just record the def |
duke@435 | 1207 | Reachblock[slidx] = n; |
duke@435 | 1208 | // UP should come from the outRegmask() of the DEF |
duke@435 | 1209 | UPblock[slidx] = defup; |
duke@435 | 1210 | // Update debug list of reaching down definitions, kill if DEF is UP |
duke@435 | 1211 | debug_defs[slidx] = defup ? NULL : n; |
duke@435 | 1212 | #ifndef PRODUCT |
duke@435 | 1213 | // DEBUG |
duke@435 | 1214 | if( trace_spilling() ) { |
duke@435 | 1215 | tty->print("\nNew DEF of Spill Idx "); |
duke@435 | 1216 | tty->print("%d, UP %d:\n",slidx,defup); |
duke@435 | 1217 | n->dump(); |
duke@435 | 1218 | } |
duke@435 | 1219 | #endif |
duke@435 | 1220 | } // End else LRP |
duke@435 | 1221 | } // End if spill def |
duke@435 | 1222 | |
duke@435 | 1223 | // ********** Split Left Over Mem-Mem Moves ********** |
duke@435 | 1224 | // Check for mem-mem copies and split them now. Do not do this |
duke@435 | 1225 | // to copies about to be spilled; they will be Split shortly. |
neliasso@4949 | 1226 | if (copyidx) { |
duke@435 | 1227 | Node *use = n->in(copyidx); |
neliasso@4949 | 1228 | uint useidx = _lrg_map.find_id(use); |
neliasso@4949 | 1229 | if (useidx < _lrg_map.max_lrg_id() && // This is not a new split |
duke@435 | 1230 | OptoReg::is_stack(deflrg.reg()) && |
duke@435 | 1231 | deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack |
duke@435 | 1232 | LRG &uselrg = lrgs(useidx); |
duke@435 | 1233 | if( OptoReg::is_stack(uselrg.reg()) && |
duke@435 | 1234 | uselrg.reg() < LRG::SPILL_REG && // USE is from stack |
duke@435 | 1235 | deflrg.reg() != uselrg.reg() ) { // Not trivially removed |
coleenp@4037 | 1236 | uint def_ideal_reg = n->bottom_type()->ideal_reg(); |
duke@435 | 1237 | const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg]; |
duke@435 | 1238 | const RegMask &use_rm = n->in_RegMask(copyidx); |
duke@435 | 1239 | if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL |
duke@435 | 1240 | if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes |
duke@435 | 1241 | return 0; |
duke@435 | 1242 | } |
duke@435 | 1243 | Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); |
duke@435 | 1244 | n->set_req(copyidx,spill); |
duke@435 | 1245 | n->as_MachSpillCopy()->set_in_RegMask(def_rm); |
duke@435 | 1246 | // Put the spill just before the copy |
duke@435 | 1247 | insert_proj( b, insidx++, spill, maxlrg++ ); |
duke@435 | 1248 | } |
duke@435 | 1249 | } |
duke@435 | 1250 | } |
duke@435 | 1251 | } |
duke@435 | 1252 | } // End For All Instructions in Block - Non-PHI Pass |
duke@435 | 1253 | |
duke@435 | 1254 | // Check if each LRG is live out of this block so as not to propagate |
duke@435 | 1255 | // beyond the last use of a LRG. |
duke@435 | 1256 | for( slidx = 0; slidx < spill_cnt; slidx++ ) { |
duke@435 | 1257 | uint defidx = lidxs.at(slidx); |
duke@435 | 1258 | IndexSet *liveout = _live->live(b); |
duke@435 | 1259 | if( !liveout->member(defidx) ) { |
duke@435 | 1260 | #ifdef ASSERT |
duke@435 | 1261 | // The index defidx is not live. Check the liveout array to ensure that |
duke@435 | 1262 | // it contains no members which compress to defidx. Finding such an |
duke@435 | 1263 | // instance may be a case to add liveout adjustment in compress_uf_map(). |
duke@435 | 1264 | // See 5063219. |
duke@435 | 1265 | uint member; |
duke@435 | 1266 | IndexSetIterator isi(liveout); |
duke@435 | 1267 | while ((member = isi.next()) != 0) { |
neliasso@4949 | 1268 | assert(defidx != _lrg_map.find_const(member), "Live out member has not been compressed"); |
duke@435 | 1269 | } |
duke@435 | 1270 | #endif |
duke@435 | 1271 | Reachblock[slidx] = NULL; |
duke@435 | 1272 | } else { |
duke@435 | 1273 | assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value"); |
duke@435 | 1274 | } |
duke@435 | 1275 | } |
duke@435 | 1276 | #ifndef PRODUCT |
duke@435 | 1277 | if( trace_spilling() ) |
duke@435 | 1278 | b->dump(); |
duke@435 | 1279 | #endif |
duke@435 | 1280 | } // End For All Blocks |
duke@435 | 1281 | |
duke@435 | 1282 | //----------PASS 2---------- |
duke@435 | 1283 | // Reset all DEF live range numbers here |
duke@435 | 1284 | for( insidx = 0; insidx < defs->size(); insidx++ ) { |
duke@435 | 1285 | // Grab the def |
duke@435 | 1286 | n1 = defs->at(insidx); |
duke@435 | 1287 | // Set new lidx for DEF |
duke@435 | 1288 | new_lrg(n1, maxlrg++); |
duke@435 | 1289 | } |
duke@435 | 1290 | //----------Phi Node Splitting---------- |
duke@435 | 1291 | // Clean up a phi here, and assign a new live range number |
duke@435 | 1292 | // Cycle through this block's predecessors, collecting Reaches |
duke@435 | 1293 | // info for each spilled LRG and update edges. |
duke@435 | 1294 | // Walk the phis list to patch inputs, split phis, and name phis |
never@2358 | 1295 | uint lrgs_before_phi_split = maxlrg; |
duke@435 | 1296 | for( insidx = 0; insidx < phis->size(); insidx++ ) { |
duke@435 | 1297 | Node *phi = phis->at(insidx); |
duke@435 | 1298 | assert(phi->is_Phi(),"This list must only contain Phi Nodes"); |
adlertz@5509 | 1299 | Block *b = _cfg.get_block_for_node(phi); |
duke@435 | 1300 | // Grab the live range number |
neliasso@4949 | 1301 | uint lidx = _lrg_map.find_id(phi); |
duke@435 | 1302 | uint slidx = lrg2reach[lidx]; |
duke@435 | 1303 | // Update node to lidx map |
duke@435 | 1304 | new_lrg(phi, maxlrg++); |
duke@435 | 1305 | // Get PASS1's up/down decision for the block. |
duke@435 | 1306 | int phi_up = !!UP_entry[slidx]->test(b->_pre_order); |
duke@435 | 1307 | |
duke@435 | 1308 | // Force down if double-spilling live range |
duke@435 | 1309 | if( lrgs(lidx)._was_spilled1 ) |
duke@435 | 1310 | phi_up = false; |
duke@435 | 1311 | |
duke@435 | 1312 | // When splitting a Phi we an split it normal or "inverted". |
duke@435 | 1313 | // An inverted split makes the splits target the Phi's UP/DOWN |
duke@435 | 1314 | // sense inverted; then the Phi is followed by a final def-side |
duke@435 | 1315 | // split to invert back. It changes which blocks the spill code |
duke@435 | 1316 | // goes in. |
duke@435 | 1317 | |
duke@435 | 1318 | // Walk the predecessor blocks and assign the reaching def to the Phi. |
duke@435 | 1319 | // Split Phi nodes by placing USE side splits wherever the reaching |
duke@435 | 1320 | // DEF has the wrong UP/DOWN value. |
duke@435 | 1321 | for( uint i = 1; i < b->num_preds(); i++ ) { |
duke@435 | 1322 | // Get predecessor block pre-order number |
adlertz@5509 | 1323 | Block *pred = _cfg.get_block_for_node(b->pred(i)); |
duke@435 | 1324 | pidx = pred->_pre_order; |
duke@435 | 1325 | // Grab reaching def |
duke@435 | 1326 | Node *def = Reaches[pidx][slidx]; |
duke@435 | 1327 | assert( def, "must have reaching def" ); |
duke@435 | 1328 | // If input up/down sense and reg-pressure DISagree |
adlertz@5227 | 1329 | if (def->rematerialize() && contains_no_live_range_input(def)) { |
never@2358 | 1330 | // Place the rematerialized node above any MSCs created during |
never@2358 | 1331 | // phi node splitting. end_idx points at the insertion point |
never@2358 | 1332 | // so look at the node before it. |
never@2358 | 1333 | int insert = pred->end_idx(); |
never@2358 | 1334 | while (insert >= 1 && |
adlertz@5635 | 1335 | pred->get_node(insert - 1)->is_SpillCopy() && |
adlertz@5635 | 1336 | _lrg_map.find(pred->get_node(insert - 1)) >= lrgs_before_phi_split) { |
never@2358 | 1337 | insert--; |
never@2358 | 1338 | } |
neliasso@4949 | 1339 | def = split_Rematerialize(def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false); |
neliasso@4949 | 1340 | if (!def) { |
neliasso@4949 | 1341 | return 0; // Bail out |
neliasso@4949 | 1342 | } |
duke@435 | 1343 | } |
duke@435 | 1344 | // Update the Phi's input edge array |
duke@435 | 1345 | phi->set_req(i,def); |
duke@435 | 1346 | // Grab the UP/DOWN sense for the input |
duke@435 | 1347 | u1 = UP[pidx][slidx]; |
duke@435 | 1348 | if( u1 != (phi_up != 0)) { |
duke@435 | 1349 | maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); |
duke@435 | 1350 | // If it wasn't split bail |
duke@435 | 1351 | if (!maxlrg) { |
duke@435 | 1352 | return 0; |
duke@435 | 1353 | } |
duke@435 | 1354 | } |
duke@435 | 1355 | } // End for all inputs to the Phi |
duke@435 | 1356 | } // End for all Phi Nodes |
duke@435 | 1357 | // Update _maxlrg to save Union asserts |
neliasso@4949 | 1358 | _lrg_map.set_max_lrg_id(maxlrg); |
duke@435 | 1359 | |
duke@435 | 1360 | |
duke@435 | 1361 | //----------PASS 3---------- |
duke@435 | 1362 | // Pass over all Phi's to union the live ranges |
duke@435 | 1363 | for( insidx = 0; insidx < phis->size(); insidx++ ) { |
duke@435 | 1364 | Node *phi = phis->at(insidx); |
duke@435 | 1365 | assert(phi->is_Phi(),"This list must only contain Phi Nodes"); |
duke@435 | 1366 | // Walk all inputs to Phi and Union input live range with Phi live range |
duke@435 | 1367 | for( uint i = 1; i < phi->req(); i++ ) { |
duke@435 | 1368 | // Grab the input node |
duke@435 | 1369 | Node *n = phi->in(i); |
neliasso@4949 | 1370 | assert(n, "node should exist"); |
neliasso@4949 | 1371 | uint lidx = _lrg_map.find(n); |
neliasso@4949 | 1372 | uint pidx = _lrg_map.find(phi); |
neliasso@4949 | 1373 | if (lidx < pidx) { |
duke@435 | 1374 | Union(n, phi); |
neliasso@4949 | 1375 | } |
neliasso@4949 | 1376 | else if(lidx > pidx) { |
duke@435 | 1377 | Union(phi, n); |
neliasso@4949 | 1378 | } |
duke@435 | 1379 | } // End for all inputs to the Phi Node |
duke@435 | 1380 | } // End for all Phi Nodes |
duke@435 | 1381 | // Now union all two address instructions |
neliasso@4949 | 1382 | for (insidx = 0; insidx < defs->size(); insidx++) { |
duke@435 | 1383 | // Grab the def |
duke@435 | 1384 | n1 = defs->at(insidx); |
duke@435 | 1385 | // Set new lidx for DEF & handle 2-addr instructions |
neliasso@4949 | 1386 | if (n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0)) { |
neliasso@4949 | 1387 | assert(_lrg_map.find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index"); |
duke@435 | 1388 | // Union the input and output live ranges |
neliasso@4949 | 1389 | uint lr1 = _lrg_map.find(n1); |
neliasso@4949 | 1390 | uint lr2 = _lrg_map.find(n1->in(twoidx)); |
neliasso@4949 | 1391 | if (lr1 < lr2) { |
duke@435 | 1392 | Union(n1, n1->in(twoidx)); |
neliasso@4949 | 1393 | } |
neliasso@4949 | 1394 | else if (lr1 > lr2) { |
duke@435 | 1395 | Union(n1->in(twoidx), n1); |
neliasso@4949 | 1396 | } |
duke@435 | 1397 | } // End if two address |
duke@435 | 1398 | } // End for all defs |
duke@435 | 1399 | // DEBUG |
duke@435 | 1400 | #ifdef ASSERT |
duke@435 | 1401 | // Validate all live range index assignments |
adlertz@5539 | 1402 | for (bidx = 0; bidx < _cfg.number_of_blocks(); bidx++) { |
adlertz@5539 | 1403 | b = _cfg.get_block(bidx); |
neliasso@4949 | 1404 | for (insidx = 0; insidx <= b->end_idx(); insidx++) { |
adlertz@5635 | 1405 | Node *n = b->get_node(insidx); |
neliasso@4949 | 1406 | uint defidx = _lrg_map.find(n); |
neliasso@4949 | 1407 | assert(defidx < _lrg_map.max_lrg_id(), "Bad live range index in Split"); |
duke@435 | 1408 | assert(defidx < maxlrg,"Bad live range index in Split"); |
duke@435 | 1409 | } |
duke@435 | 1410 | } |
duke@435 | 1411 | // Issue a warning if splitting made no progress |
duke@435 | 1412 | int noprogress = 0; |
neliasso@4949 | 1413 | for (slidx = 0; slidx < spill_cnt; slidx++) { |
neliasso@4949 | 1414 | if (PrintOpto && WizardMode && splits.at(slidx) == 0) { |
duke@435 | 1415 | tty->print_cr("Failed to split live range %d", lidxs.at(slidx)); |
duke@435 | 1416 | //BREAKPOINT; |
duke@435 | 1417 | } |
duke@435 | 1418 | else { |
duke@435 | 1419 | noprogress++; |
duke@435 | 1420 | } |
duke@435 | 1421 | } |
duke@435 | 1422 | if(!noprogress) { |
duke@435 | 1423 | tty->print_cr("Failed to make progress in Split"); |
duke@435 | 1424 | //BREAKPOINT; |
duke@435 | 1425 | } |
duke@435 | 1426 | #endif |
duke@435 | 1427 | // Return updated count of live ranges |
duke@435 | 1428 | return maxlrg; |
duke@435 | 1429 | } |