Mon, 04 Nov 2013 21:59:54 +0100
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
Summary: String.equals() intrinsic shouldn't use integer length input in pointer arithmetic without an i2l.
Reviewed-by: kvn, twisti
duke@435 | 1 | /* |
stefank@2314 | 2 | * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP |
stefank@2314 | 26 | #define CPU_SPARC_VM_REGISTER_SPARC_HPP |
stefank@2314 | 27 | |
stefank@2314 | 28 | #include "asm/register.hpp" |
stefank@2314 | 29 | #include "vm_version_sparc.hpp" |
stefank@2314 | 30 | |
duke@435 | 31 | // forward declaration |
duke@435 | 32 | class Address; |
duke@435 | 33 | class VMRegImpl; |
duke@435 | 34 | typedef VMRegImpl* VMReg; |
duke@435 | 35 | |
duke@435 | 36 | |
duke@435 | 37 | // Use Register as shortcut |
duke@435 | 38 | class RegisterImpl; |
duke@435 | 39 | typedef RegisterImpl* Register; |
duke@435 | 40 | |
duke@435 | 41 | |
duke@435 | 42 | inline Register as_Register(int encoding) { |
duke@435 | 43 | return (Register)(intptr_t) encoding; |
duke@435 | 44 | } |
duke@435 | 45 | |
duke@435 | 46 | // The implementation of integer registers for the SPARC architecture |
duke@435 | 47 | class RegisterImpl: public AbstractRegisterImpl { |
duke@435 | 48 | public: |
duke@435 | 49 | enum { |
duke@435 | 50 | log_set_size = 3, // the number of bits to encode the set register number |
duke@435 | 51 | number_of_sets = 4, // the number of registers sets (in, local, out, global) |
duke@435 | 52 | number_of_registers = number_of_sets << log_set_size, |
duke@435 | 53 | |
duke@435 | 54 | iset_no = 3, ibase = iset_no << log_set_size, // the in register set |
duke@435 | 55 | lset_no = 2, lbase = lset_no << log_set_size, // the local register set |
duke@435 | 56 | oset_no = 1, obase = oset_no << log_set_size, // the output register set |
duke@435 | 57 | gset_no = 0, gbase = gset_no << log_set_size // the global register set |
duke@435 | 58 | }; |
duke@435 | 59 | |
duke@435 | 60 | |
duke@435 | 61 | friend Register as_Register(int encoding); |
duke@435 | 62 | // set specific construction |
duke@435 | 63 | friend Register as_iRegister(int number); |
duke@435 | 64 | friend Register as_lRegister(int number); |
duke@435 | 65 | friend Register as_oRegister(int number); |
duke@435 | 66 | friend Register as_gRegister(int number); |
duke@435 | 67 | |
duke@435 | 68 | VMReg as_VMReg(); |
duke@435 | 69 | |
duke@435 | 70 | // accessors |
duke@435 | 71 | int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
duke@435 | 72 | const char* name() const; |
duke@435 | 73 | |
duke@435 | 74 | // testers |
duke@435 | 75 | bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); } |
duke@435 | 76 | bool is_even() const { return (encoding() & 1) == 0; } |
duke@435 | 77 | bool is_in() const { return (encoding() >> log_set_size) == iset_no; } |
duke@435 | 78 | bool is_local() const { return (encoding() >> log_set_size) == lset_no; } |
duke@435 | 79 | bool is_out() const { return (encoding() >> log_set_size) == oset_no; } |
duke@435 | 80 | bool is_global() const { return (encoding() >> log_set_size) == gset_no; } |
duke@435 | 81 | |
duke@435 | 82 | // derived registers, offsets, and addresses |
duke@435 | 83 | Register successor() const { return as_Register(encoding() + 1); } |
duke@435 | 84 | |
duke@435 | 85 | int input_number() const { |
duke@435 | 86 | assert(is_in(), "must be input register"); |
duke@435 | 87 | return encoding() - ibase; |
duke@435 | 88 | } |
duke@435 | 89 | |
duke@435 | 90 | Register after_save() const { |
duke@435 | 91 | assert(is_out() || is_global(), "register not visible after save"); |
duke@435 | 92 | return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this; |
duke@435 | 93 | } |
duke@435 | 94 | |
duke@435 | 95 | Register after_restore() const { |
duke@435 | 96 | assert(is_in() || is_global(), "register not visible after restore"); |
duke@435 | 97 | return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this; |
duke@435 | 98 | } |
duke@435 | 99 | |
duke@435 | 100 | int sp_offset_in_saved_window() const { |
duke@435 | 101 | assert(is_in() || is_local(), "only i and l registers are saved in frame"); |
duke@435 | 102 | return encoding() - lbase; |
duke@435 | 103 | } |
duke@435 | 104 | |
duke@435 | 105 | inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp |
duke@435 | 106 | }; |
duke@435 | 107 | |
duke@435 | 108 | |
duke@435 | 109 | // set specific construction |
duke@435 | 110 | inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); } |
duke@435 | 111 | inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); } |
duke@435 | 112 | inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); } |
duke@435 | 113 | inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); } |
duke@435 | 114 | |
duke@435 | 115 | // The integer registers of the SPARC architecture |
duke@435 | 116 | |
duke@435 | 117 | CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1)); |
duke@435 | 118 | |
duke@435 | 119 | CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0)); |
duke@435 | 120 | CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1)); |
duke@435 | 121 | CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2)); |
duke@435 | 122 | CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3)); |
duke@435 | 123 | CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4)); |
duke@435 | 124 | CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5)); |
duke@435 | 125 | CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6)); |
duke@435 | 126 | CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7)); |
duke@435 | 127 | |
duke@435 | 128 | CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0)); |
duke@435 | 129 | CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1)); |
duke@435 | 130 | CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2)); |
duke@435 | 131 | CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3)); |
duke@435 | 132 | CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4)); |
duke@435 | 133 | CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5)); |
duke@435 | 134 | CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6)); |
duke@435 | 135 | CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7)); |
duke@435 | 136 | |
duke@435 | 137 | CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0)); |
duke@435 | 138 | CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1)); |
duke@435 | 139 | CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2)); |
duke@435 | 140 | CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3)); |
duke@435 | 141 | CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4)); |
duke@435 | 142 | CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5)); |
duke@435 | 143 | CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6)); |
duke@435 | 144 | CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7)); |
duke@435 | 145 | |
duke@435 | 146 | CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0)); |
duke@435 | 147 | CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1)); |
duke@435 | 148 | CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2)); |
duke@435 | 149 | CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3)); |
duke@435 | 150 | CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4)); |
duke@435 | 151 | CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5)); |
duke@435 | 152 | CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6)); |
duke@435 | 153 | CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7)); |
duke@435 | 154 | |
duke@435 | 155 | CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6)); |
duke@435 | 156 | CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6)); |
duke@435 | 157 | |
duke@435 | 158 | // |
duke@435 | 159 | // Because sparc has so many registers, #define'ing values for the is |
duke@435 | 160 | // beneficial in code size and the cost of some of the dangers of |
duke@435 | 161 | // defines. We don't use them on Intel because win32 uses asm |
duke@435 | 162 | // directives which use the same names for registers as Hotspot does, |
duke@435 | 163 | // so #defines would screw up the inline assembly. If a particular |
duke@435 | 164 | // file has a problem with these defines then it's possible to turn |
duke@435 | 165 | // them off in that file by defining DONT_USE_REGISTER_DEFINES. |
duke@435 | 166 | // register_definition_sparc.cpp does that so that it's able to |
duke@435 | 167 | // provide real definitions of these registers for use in debuggers |
duke@435 | 168 | // and such. |
duke@435 | 169 | // |
duke@435 | 170 | |
duke@435 | 171 | #ifndef DONT_USE_REGISTER_DEFINES |
duke@435 | 172 | #define noreg ((Register)(noreg_RegisterEnumValue)) |
duke@435 | 173 | |
duke@435 | 174 | #define G0 ((Register)(G0_RegisterEnumValue)) |
duke@435 | 175 | #define G1 ((Register)(G1_RegisterEnumValue)) |
duke@435 | 176 | #define G2 ((Register)(G2_RegisterEnumValue)) |
duke@435 | 177 | #define G3 ((Register)(G3_RegisterEnumValue)) |
duke@435 | 178 | #define G4 ((Register)(G4_RegisterEnumValue)) |
duke@435 | 179 | #define G5 ((Register)(G5_RegisterEnumValue)) |
duke@435 | 180 | #define G6 ((Register)(G6_RegisterEnumValue)) |
duke@435 | 181 | #define G7 ((Register)(G7_RegisterEnumValue)) |
duke@435 | 182 | |
duke@435 | 183 | #define O0 ((Register)(O0_RegisterEnumValue)) |
duke@435 | 184 | #define O1 ((Register)(O1_RegisterEnumValue)) |
duke@435 | 185 | #define O2 ((Register)(O2_RegisterEnumValue)) |
duke@435 | 186 | #define O3 ((Register)(O3_RegisterEnumValue)) |
duke@435 | 187 | #define O4 ((Register)(O4_RegisterEnumValue)) |
duke@435 | 188 | #define O5 ((Register)(O5_RegisterEnumValue)) |
duke@435 | 189 | #define O6 ((Register)(O6_RegisterEnumValue)) |
duke@435 | 190 | #define O7 ((Register)(O7_RegisterEnumValue)) |
duke@435 | 191 | |
duke@435 | 192 | #define L0 ((Register)(L0_RegisterEnumValue)) |
duke@435 | 193 | #define L1 ((Register)(L1_RegisterEnumValue)) |
duke@435 | 194 | #define L2 ((Register)(L2_RegisterEnumValue)) |
duke@435 | 195 | #define L3 ((Register)(L3_RegisterEnumValue)) |
duke@435 | 196 | #define L4 ((Register)(L4_RegisterEnumValue)) |
duke@435 | 197 | #define L5 ((Register)(L5_RegisterEnumValue)) |
duke@435 | 198 | #define L6 ((Register)(L6_RegisterEnumValue)) |
duke@435 | 199 | #define L7 ((Register)(L7_RegisterEnumValue)) |
duke@435 | 200 | |
duke@435 | 201 | #define I0 ((Register)(I0_RegisterEnumValue)) |
duke@435 | 202 | #define I1 ((Register)(I1_RegisterEnumValue)) |
duke@435 | 203 | #define I2 ((Register)(I2_RegisterEnumValue)) |
duke@435 | 204 | #define I3 ((Register)(I3_RegisterEnumValue)) |
duke@435 | 205 | #define I4 ((Register)(I4_RegisterEnumValue)) |
duke@435 | 206 | #define I5 ((Register)(I5_RegisterEnumValue)) |
duke@435 | 207 | #define I6 ((Register)(I6_RegisterEnumValue)) |
duke@435 | 208 | #define I7 ((Register)(I7_RegisterEnumValue)) |
duke@435 | 209 | |
duke@435 | 210 | #define FP ((Register)(FP_RegisterEnumValue)) |
duke@435 | 211 | #define SP ((Register)(SP_RegisterEnumValue)) |
duke@435 | 212 | #endif // DONT_USE_REGISTER_DEFINES |
duke@435 | 213 | |
duke@435 | 214 | // Use FloatRegister as shortcut |
duke@435 | 215 | class FloatRegisterImpl; |
duke@435 | 216 | typedef FloatRegisterImpl* FloatRegister; |
duke@435 | 217 | |
duke@435 | 218 | |
duke@435 | 219 | // construction |
duke@435 | 220 | inline FloatRegister as_FloatRegister(int encoding) { |
duke@435 | 221 | return (FloatRegister)(intptr_t)encoding; |
duke@435 | 222 | } |
duke@435 | 223 | |
duke@435 | 224 | // The implementation of float registers for the SPARC architecture |
duke@435 | 225 | |
duke@435 | 226 | class FloatRegisterImpl: public AbstractRegisterImpl { |
duke@435 | 227 | public: |
duke@435 | 228 | enum { |
duke@435 | 229 | number_of_registers = 64 |
duke@435 | 230 | }; |
duke@435 | 231 | |
duke@435 | 232 | enum Width { |
duke@435 | 233 | S = 1, D = 2, Q = 3 |
duke@435 | 234 | }; |
duke@435 | 235 | |
duke@435 | 236 | // construction |
duke@435 | 237 | VMReg as_VMReg( ); |
duke@435 | 238 | |
duke@435 | 239 | // accessors |
duke@435 | 240 | int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
duke@435 | 241 | |
duke@435 | 242 | public: |
duke@435 | 243 | int encoding(Width w) const { |
duke@435 | 244 | const int c = encoding(); |
duke@435 | 245 | switch (w) { |
duke@435 | 246 | case S: |
duke@435 | 247 | assert(c < 32, "bad single float register"); |
duke@435 | 248 | return c; |
duke@435 | 249 | |
duke@435 | 250 | case D: |
duke@435 | 251 | assert(c < 64 && (c & 1) == 0, "bad double float register"); |
duke@435 | 252 | return (c & 0x1e) | ((c & 0x20) >> 5); |
duke@435 | 253 | |
duke@435 | 254 | case Q: |
duke@435 | 255 | assert(c < 64 && (c & 3) == 0, "bad quad float register"); |
duke@435 | 256 | return (c & 0x1c) | ((c & 0x20) >> 5); |
duke@435 | 257 | } |
duke@435 | 258 | ShouldNotReachHere(); |
duke@435 | 259 | return -1; |
duke@435 | 260 | } |
duke@435 | 261 | |
duke@435 | 262 | bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
duke@435 | 263 | const char* name() const; |
duke@435 | 264 | |
duke@435 | 265 | FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } |
duke@435 | 266 | }; |
duke@435 | 267 | |
duke@435 | 268 | |
duke@435 | 269 | // The float registers of the SPARC architecture |
duke@435 | 270 | |
duke@435 | 271 | CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); |
duke@435 | 272 | |
duke@435 | 273 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0)); |
duke@435 | 274 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1)); |
duke@435 | 275 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2)); |
duke@435 | 276 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3)); |
duke@435 | 277 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4)); |
duke@435 | 278 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5)); |
duke@435 | 279 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6)); |
duke@435 | 280 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7)); |
duke@435 | 281 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8)); |
duke@435 | 282 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9)); |
duke@435 | 283 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10)); |
duke@435 | 284 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11)); |
duke@435 | 285 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12)); |
duke@435 | 286 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13)); |
duke@435 | 287 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14)); |
duke@435 | 288 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15)); |
duke@435 | 289 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16)); |
duke@435 | 290 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17)); |
duke@435 | 291 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18)); |
duke@435 | 292 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19)); |
duke@435 | 293 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20)); |
duke@435 | 294 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21)); |
duke@435 | 295 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22)); |
duke@435 | 296 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23)); |
duke@435 | 297 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24)); |
duke@435 | 298 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25)); |
duke@435 | 299 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26)); |
duke@435 | 300 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27)); |
duke@435 | 301 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28)); |
duke@435 | 302 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29)); |
duke@435 | 303 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30)); |
duke@435 | 304 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31)); |
duke@435 | 305 | |
duke@435 | 306 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32)); |
duke@435 | 307 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34)); |
duke@435 | 308 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36)); |
duke@435 | 309 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38)); |
duke@435 | 310 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40)); |
duke@435 | 311 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42)); |
duke@435 | 312 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44)); |
duke@435 | 313 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46)); |
duke@435 | 314 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48)); |
duke@435 | 315 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50)); |
duke@435 | 316 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52)); |
duke@435 | 317 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54)); |
duke@435 | 318 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56)); |
duke@435 | 319 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58)); |
duke@435 | 320 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60)); |
duke@435 | 321 | CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62)); |
duke@435 | 322 | |
duke@435 | 323 | |
duke@435 | 324 | #ifndef DONT_USE_REGISTER_DEFINES |
duke@435 | 325 | #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) |
duke@435 | 326 | #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue)) |
duke@435 | 327 | #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue)) |
duke@435 | 328 | #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue)) |
duke@435 | 329 | #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue)) |
duke@435 | 330 | #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue)) |
duke@435 | 331 | #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue)) |
duke@435 | 332 | #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue)) |
duke@435 | 333 | #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue)) |
duke@435 | 334 | #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue)) |
duke@435 | 335 | #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue)) |
duke@435 | 336 | #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue)) |
duke@435 | 337 | #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue)) |
duke@435 | 338 | #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue)) |
duke@435 | 339 | #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue)) |
duke@435 | 340 | #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue)) |
duke@435 | 341 | #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue)) |
duke@435 | 342 | #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue)) |
duke@435 | 343 | #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue)) |
duke@435 | 344 | #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue)) |
duke@435 | 345 | #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue)) |
duke@435 | 346 | #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue)) |
duke@435 | 347 | #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue)) |
duke@435 | 348 | #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue)) |
duke@435 | 349 | #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue)) |
duke@435 | 350 | #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue)) |
duke@435 | 351 | #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue)) |
duke@435 | 352 | #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue)) |
duke@435 | 353 | #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue)) |
duke@435 | 354 | #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue)) |
duke@435 | 355 | #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue)) |
duke@435 | 356 | #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue)) |
duke@435 | 357 | #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue)) |
duke@435 | 358 | #define F32 ((FloatRegister)( F32_FloatRegisterEnumValue)) |
duke@435 | 359 | #define F34 ((FloatRegister)( F34_FloatRegisterEnumValue)) |
duke@435 | 360 | #define F36 ((FloatRegister)( F36_FloatRegisterEnumValue)) |
duke@435 | 361 | #define F38 ((FloatRegister)( F38_FloatRegisterEnumValue)) |
duke@435 | 362 | #define F40 ((FloatRegister)( F40_FloatRegisterEnumValue)) |
duke@435 | 363 | #define F42 ((FloatRegister)( F42_FloatRegisterEnumValue)) |
duke@435 | 364 | #define F44 ((FloatRegister)( F44_FloatRegisterEnumValue)) |
duke@435 | 365 | #define F46 ((FloatRegister)( F46_FloatRegisterEnumValue)) |
duke@435 | 366 | #define F48 ((FloatRegister)( F48_FloatRegisterEnumValue)) |
duke@435 | 367 | #define F50 ((FloatRegister)( F50_FloatRegisterEnumValue)) |
duke@435 | 368 | #define F52 ((FloatRegister)( F52_FloatRegisterEnumValue)) |
duke@435 | 369 | #define F54 ((FloatRegister)( F54_FloatRegisterEnumValue)) |
duke@435 | 370 | #define F56 ((FloatRegister)( F56_FloatRegisterEnumValue)) |
duke@435 | 371 | #define F58 ((FloatRegister)( F58_FloatRegisterEnumValue)) |
duke@435 | 372 | #define F60 ((FloatRegister)( F60_FloatRegisterEnumValue)) |
duke@435 | 373 | #define F62 ((FloatRegister)( F62_FloatRegisterEnumValue)) |
duke@435 | 374 | #endif // DONT_USE_REGISTER_DEFINES |
duke@435 | 375 | |
duke@435 | 376 | // Maximum number of incoming arguments that can be passed in i registers. |
duke@435 | 377 | const int SPARC_ARGS_IN_REGS_NUM = 6; |
duke@435 | 378 | |
duke@435 | 379 | class ConcreteRegisterImpl : public AbstractRegisterImpl { |
duke@435 | 380 | public: |
duke@435 | 381 | enum { |
duke@435 | 382 | // This number must be large enough to cover REG_COUNT (defined by c2) registers. |
duke@435 | 383 | // There is no requirement that any ordering here matches any ordering c2 gives |
duke@435 | 384 | // it's optoregs. |
duke@435 | 385 | number_of_registers = 2*RegisterImpl::number_of_registers + |
duke@435 | 386 | FloatRegisterImpl::number_of_registers + |
duke@435 | 387 | 1 + // ccr |
duke@435 | 388 | 4 // fcc |
duke@435 | 389 | }; |
duke@435 | 390 | static const int max_gpr; |
duke@435 | 391 | static const int max_fpr; |
duke@435 | 392 | |
duke@435 | 393 | }; |
duke@435 | 394 | |
duke@435 | 395 | // Single, Double and Quad fp reg classes. These exist to map the ADLC |
duke@435 | 396 | // encoding for a floating point register, to the FloatRegister number |
duke@435 | 397 | // desired by the macroassembler. A FloatRegister is a number between |
duke@435 | 398 | // 0 and 63 passed around as a pointer. For ADLC, an fp register encoding |
duke@435 | 399 | // is the actual bit encoding used by the sparc hardware. When ADLC used |
duke@435 | 400 | // the macroassembler to generate an instruction that references, e.g., a |
duke@435 | 401 | // double fp reg, it passed the bit encoding to the macroassembler via |
duke@435 | 402 | // as_FloatRegister, which, for double regs > 30, returns an illegal |
duke@435 | 403 | // register number. |
duke@435 | 404 | // |
duke@435 | 405 | // Therefore we provide the following classes for use by ADLC. Their |
duke@435 | 406 | // sole purpose is to convert from sparc register encodings to FloatRegisters. |
duke@435 | 407 | // At some future time, we might replace FloatRegister with these classes, |
duke@435 | 408 | // hence the definitions of as_xxxFloatRegister as class methods rather |
duke@435 | 409 | // than as external inline routines. |
duke@435 | 410 | |
duke@435 | 411 | class SingleFloatRegisterImpl; |
duke@435 | 412 | typedef SingleFloatRegisterImpl *SingleFloatRegister; |
duke@435 | 413 | |
duke@435 | 414 | inline FloatRegister as_SingleFloatRegister(int encoding); |
duke@435 | 415 | class SingleFloatRegisterImpl { |
duke@435 | 416 | public: |
duke@435 | 417 | friend inline FloatRegister as_SingleFloatRegister(int encoding) { |
duke@435 | 418 | assert(encoding < 32, "bad single float register encoding"); |
duke@435 | 419 | return as_FloatRegister(encoding); |
duke@435 | 420 | } |
duke@435 | 421 | }; |
duke@435 | 422 | |
duke@435 | 423 | |
duke@435 | 424 | class DoubleFloatRegisterImpl; |
duke@435 | 425 | typedef DoubleFloatRegisterImpl *DoubleFloatRegister; |
duke@435 | 426 | |
duke@435 | 427 | inline FloatRegister as_DoubleFloatRegister(int encoding); |
duke@435 | 428 | class DoubleFloatRegisterImpl { |
duke@435 | 429 | public: |
duke@435 | 430 | friend inline FloatRegister as_DoubleFloatRegister(int encoding) { |
duke@435 | 431 | assert(encoding < 32, "bad double float register encoding"); |
duke@435 | 432 | return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) ); |
duke@435 | 433 | } |
duke@435 | 434 | }; |
duke@435 | 435 | |
duke@435 | 436 | |
duke@435 | 437 | class QuadFloatRegisterImpl; |
duke@435 | 438 | typedef QuadFloatRegisterImpl *QuadFloatRegister; |
duke@435 | 439 | |
duke@435 | 440 | class QuadFloatRegisterImpl { |
duke@435 | 441 | public: |
duke@435 | 442 | friend FloatRegister as_QuadFloatRegister(int encoding) { |
duke@435 | 443 | assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding"); |
duke@435 | 444 | return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) ); |
duke@435 | 445 | } |
duke@435 | 446 | }; |
stefank@2314 | 447 | |
stefank@2314 | 448 | #endif // CPU_SPARC_VM_REGISTER_SPARC_HPP |