Mon, 04 Nov 2013 21:59:54 +0100
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
Summary: String.equals() intrinsic shouldn't use integer length input in pointer arithmetic without an i2l.
Reviewed-by: kvn, twisti
duke@435 | 1 | /* |
mikael@4153 | 2 | * Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #include "precompiled.hpp" |
stefank@2314 | 26 | #include "c1/c1_FrameMap.hpp" |
stefank@2314 | 27 | #include "c1/c1_LIR.hpp" |
stefank@2314 | 28 | #include "runtime/sharedRuntime.hpp" |
stefank@2314 | 29 | #include "vmreg_sparc.inline.hpp" |
duke@435 | 30 | |
duke@435 | 31 | |
duke@435 | 32 | const int FrameMap::pd_c_runtime_reserved_arg_size = 7; |
duke@435 | 33 | |
duke@435 | 34 | |
duke@435 | 35 | LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { |
duke@435 | 36 | LIR_Opr opr = LIR_OprFact::illegalOpr; |
duke@435 | 37 | VMReg r_1 = reg->first(); |
duke@435 | 38 | VMReg r_2 = reg->second(); |
duke@435 | 39 | if (r_1->is_stack()) { |
duke@435 | 40 | // Convert stack slot to an SP offset |
duke@435 | 41 | // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
duke@435 | 42 | // so we must add it in here. |
duke@435 | 43 | int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
duke@435 | 44 | opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); |
duke@435 | 45 | } else if (r_1->is_Register()) { |
duke@435 | 46 | Register reg = r_1->as_Register(); |
duke@435 | 47 | if (outgoing) { |
duke@435 | 48 | assert(!reg->is_in(), "should be using I regs"); |
duke@435 | 49 | } else { |
duke@435 | 50 | assert(!reg->is_out(), "should be using O regs"); |
duke@435 | 51 | } |
duke@435 | 52 | if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
duke@435 | 53 | opr = as_long_opr(reg); |
duke@435 | 54 | } else if (type == T_OBJECT || type == T_ARRAY) { |
duke@435 | 55 | opr = as_oop_opr(reg); |
iveresov@5994 | 56 | } else if (type == T_METADATA) { |
iveresov@5994 | 57 | opr = as_metadata_opr(reg); |
duke@435 | 58 | } else { |
duke@435 | 59 | opr = as_opr(reg); |
duke@435 | 60 | } |
duke@435 | 61 | } else if (r_1->is_FloatRegister()) { |
duke@435 | 62 | assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
duke@435 | 63 | FloatRegister f = r_1->as_FloatRegister(); |
duke@435 | 64 | if (type == T_DOUBLE) { |
duke@435 | 65 | opr = as_double_opr(f); |
duke@435 | 66 | } else { |
duke@435 | 67 | opr = as_float_opr(f); |
duke@435 | 68 | } |
duke@435 | 69 | } |
duke@435 | 70 | return opr; |
duke@435 | 71 | } |
duke@435 | 72 | |
duke@435 | 73 | // FrameMap |
duke@435 | 74 | //-------------------------------------------------------- |
duke@435 | 75 | |
duke@435 | 76 | FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; |
duke@435 | 77 | |
duke@435 | 78 | // some useful constant RInfo's: |
duke@435 | 79 | LIR_Opr FrameMap::in_long_opr; |
duke@435 | 80 | LIR_Opr FrameMap::out_long_opr; |
iveresov@2138 | 81 | LIR_Opr FrameMap::g1_long_single_opr; |
duke@435 | 82 | |
duke@435 | 83 | LIR_Opr FrameMap::F0_opr; |
duke@435 | 84 | LIR_Opr FrameMap::F0_double_opr; |
duke@435 | 85 | |
duke@435 | 86 | LIR_Opr FrameMap::G0_opr; |
duke@435 | 87 | LIR_Opr FrameMap::G1_opr; |
duke@435 | 88 | LIR_Opr FrameMap::G2_opr; |
duke@435 | 89 | LIR_Opr FrameMap::G3_opr; |
duke@435 | 90 | LIR_Opr FrameMap::G4_opr; |
duke@435 | 91 | LIR_Opr FrameMap::G5_opr; |
duke@435 | 92 | LIR_Opr FrameMap::G6_opr; |
duke@435 | 93 | LIR_Opr FrameMap::G7_opr; |
duke@435 | 94 | LIR_Opr FrameMap::O0_opr; |
duke@435 | 95 | LIR_Opr FrameMap::O1_opr; |
duke@435 | 96 | LIR_Opr FrameMap::O2_opr; |
duke@435 | 97 | LIR_Opr FrameMap::O3_opr; |
duke@435 | 98 | LIR_Opr FrameMap::O4_opr; |
duke@435 | 99 | LIR_Opr FrameMap::O5_opr; |
duke@435 | 100 | LIR_Opr FrameMap::O6_opr; |
duke@435 | 101 | LIR_Opr FrameMap::O7_opr; |
duke@435 | 102 | LIR_Opr FrameMap::L0_opr; |
duke@435 | 103 | LIR_Opr FrameMap::L1_opr; |
duke@435 | 104 | LIR_Opr FrameMap::L2_opr; |
duke@435 | 105 | LIR_Opr FrameMap::L3_opr; |
duke@435 | 106 | LIR_Opr FrameMap::L4_opr; |
duke@435 | 107 | LIR_Opr FrameMap::L5_opr; |
duke@435 | 108 | LIR_Opr FrameMap::L6_opr; |
duke@435 | 109 | LIR_Opr FrameMap::L7_opr; |
duke@435 | 110 | LIR_Opr FrameMap::I0_opr; |
duke@435 | 111 | LIR_Opr FrameMap::I1_opr; |
duke@435 | 112 | LIR_Opr FrameMap::I2_opr; |
duke@435 | 113 | LIR_Opr FrameMap::I3_opr; |
duke@435 | 114 | LIR_Opr FrameMap::I4_opr; |
duke@435 | 115 | LIR_Opr FrameMap::I5_opr; |
duke@435 | 116 | LIR_Opr FrameMap::I6_opr; |
duke@435 | 117 | LIR_Opr FrameMap::I7_opr; |
duke@435 | 118 | |
duke@435 | 119 | LIR_Opr FrameMap::G0_oop_opr; |
duke@435 | 120 | LIR_Opr FrameMap::G1_oop_opr; |
duke@435 | 121 | LIR_Opr FrameMap::G2_oop_opr; |
duke@435 | 122 | LIR_Opr FrameMap::G3_oop_opr; |
duke@435 | 123 | LIR_Opr FrameMap::G4_oop_opr; |
duke@435 | 124 | LIR_Opr FrameMap::G5_oop_opr; |
duke@435 | 125 | LIR_Opr FrameMap::G6_oop_opr; |
duke@435 | 126 | LIR_Opr FrameMap::G7_oop_opr; |
duke@435 | 127 | LIR_Opr FrameMap::O0_oop_opr; |
duke@435 | 128 | LIR_Opr FrameMap::O1_oop_opr; |
duke@435 | 129 | LIR_Opr FrameMap::O2_oop_opr; |
duke@435 | 130 | LIR_Opr FrameMap::O3_oop_opr; |
duke@435 | 131 | LIR_Opr FrameMap::O4_oop_opr; |
duke@435 | 132 | LIR_Opr FrameMap::O5_oop_opr; |
duke@435 | 133 | LIR_Opr FrameMap::O6_oop_opr; |
duke@435 | 134 | LIR_Opr FrameMap::O7_oop_opr; |
duke@435 | 135 | LIR_Opr FrameMap::L0_oop_opr; |
duke@435 | 136 | LIR_Opr FrameMap::L1_oop_opr; |
duke@435 | 137 | LIR_Opr FrameMap::L2_oop_opr; |
duke@435 | 138 | LIR_Opr FrameMap::L3_oop_opr; |
duke@435 | 139 | LIR_Opr FrameMap::L4_oop_opr; |
duke@435 | 140 | LIR_Opr FrameMap::L5_oop_opr; |
duke@435 | 141 | LIR_Opr FrameMap::L6_oop_opr; |
duke@435 | 142 | LIR_Opr FrameMap::L7_oop_opr; |
duke@435 | 143 | LIR_Opr FrameMap::I0_oop_opr; |
duke@435 | 144 | LIR_Opr FrameMap::I1_oop_opr; |
duke@435 | 145 | LIR_Opr FrameMap::I2_oop_opr; |
duke@435 | 146 | LIR_Opr FrameMap::I3_oop_opr; |
duke@435 | 147 | LIR_Opr FrameMap::I4_oop_opr; |
duke@435 | 148 | LIR_Opr FrameMap::I5_oop_opr; |
duke@435 | 149 | LIR_Opr FrameMap::I6_oop_opr; |
duke@435 | 150 | LIR_Opr FrameMap::I7_oop_opr; |
duke@435 | 151 | |
roland@4051 | 152 | LIR_Opr FrameMap::G0_metadata_opr; |
roland@4051 | 153 | LIR_Opr FrameMap::G1_metadata_opr; |
roland@4051 | 154 | LIR_Opr FrameMap::G2_metadata_opr; |
roland@4051 | 155 | LIR_Opr FrameMap::G3_metadata_opr; |
roland@4051 | 156 | LIR_Opr FrameMap::G4_metadata_opr; |
roland@4051 | 157 | LIR_Opr FrameMap::G5_metadata_opr; |
roland@4051 | 158 | LIR_Opr FrameMap::G6_metadata_opr; |
roland@4051 | 159 | LIR_Opr FrameMap::G7_metadata_opr; |
roland@4051 | 160 | LIR_Opr FrameMap::O0_metadata_opr; |
roland@4051 | 161 | LIR_Opr FrameMap::O1_metadata_opr; |
roland@4051 | 162 | LIR_Opr FrameMap::O2_metadata_opr; |
roland@4051 | 163 | LIR_Opr FrameMap::O3_metadata_opr; |
roland@4051 | 164 | LIR_Opr FrameMap::O4_metadata_opr; |
roland@4051 | 165 | LIR_Opr FrameMap::O5_metadata_opr; |
roland@4051 | 166 | LIR_Opr FrameMap::O6_metadata_opr; |
roland@4051 | 167 | LIR_Opr FrameMap::O7_metadata_opr; |
roland@4051 | 168 | LIR_Opr FrameMap::L0_metadata_opr; |
roland@4051 | 169 | LIR_Opr FrameMap::L1_metadata_opr; |
roland@4051 | 170 | LIR_Opr FrameMap::L2_metadata_opr; |
roland@4051 | 171 | LIR_Opr FrameMap::L3_metadata_opr; |
roland@4051 | 172 | LIR_Opr FrameMap::L4_metadata_opr; |
roland@4051 | 173 | LIR_Opr FrameMap::L5_metadata_opr; |
roland@4051 | 174 | LIR_Opr FrameMap::L6_metadata_opr; |
roland@4051 | 175 | LIR_Opr FrameMap::L7_metadata_opr; |
roland@4051 | 176 | LIR_Opr FrameMap::I0_metadata_opr; |
roland@4051 | 177 | LIR_Opr FrameMap::I1_metadata_opr; |
roland@4051 | 178 | LIR_Opr FrameMap::I2_metadata_opr; |
roland@4051 | 179 | LIR_Opr FrameMap::I3_metadata_opr; |
roland@4051 | 180 | LIR_Opr FrameMap::I4_metadata_opr; |
roland@4051 | 181 | LIR_Opr FrameMap::I5_metadata_opr; |
roland@4051 | 182 | LIR_Opr FrameMap::I6_metadata_opr; |
roland@4051 | 183 | LIR_Opr FrameMap::I7_metadata_opr; |
roland@4051 | 184 | |
duke@435 | 185 | LIR_Opr FrameMap::SP_opr; |
duke@435 | 186 | LIR_Opr FrameMap::FP_opr; |
duke@435 | 187 | |
duke@435 | 188 | LIR_Opr FrameMap::Oexception_opr; |
duke@435 | 189 | LIR_Opr FrameMap::Oissuing_pc_opr; |
duke@435 | 190 | |
duke@435 | 191 | LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
duke@435 | 192 | LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
duke@435 | 193 | |
duke@435 | 194 | |
duke@435 | 195 | FloatRegister FrameMap::nr2floatreg (int rnr) { |
duke@435 | 196 | assert(_init_done, "tables not initialized"); |
duke@435 | 197 | debug_only(fpu_range_check(rnr);) |
duke@435 | 198 | return _fpu_regs[rnr]; |
duke@435 | 199 | } |
duke@435 | 200 | |
duke@435 | 201 | |
duke@435 | 202 | // returns true if reg could be smashed by a callee. |
duke@435 | 203 | bool FrameMap::is_caller_save_register (LIR_Opr reg) { |
duke@435 | 204 | if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } |
duke@435 | 205 | if (reg->is_double_cpu()) { |
duke@435 | 206 | return is_caller_save_register(reg->as_register_lo()) || |
duke@435 | 207 | is_caller_save_register(reg->as_register_hi()); |
duke@435 | 208 | } |
duke@435 | 209 | return is_caller_save_register(reg->as_register()); |
duke@435 | 210 | } |
duke@435 | 211 | |
duke@435 | 212 | |
duke@435 | 213 | NEEDS_CLEANUP // once the new calling convention is enabled, we no |
duke@435 | 214 | // longer need to treat I5, I4 and L0 specially |
duke@435 | 215 | // Because the interpreter destroys caller's I5, I4 and L0, |
duke@435 | 216 | // we must spill them before doing a Java call as we may land in |
duke@435 | 217 | // interpreter. |
duke@435 | 218 | bool FrameMap::is_caller_save_register (Register r) { |
duke@435 | 219 | return (r->is_global() && (r != G0)) || r->is_out(); |
duke@435 | 220 | } |
duke@435 | 221 | |
duke@435 | 222 | |
iveresov@1939 | 223 | void FrameMap::initialize() { |
iveresov@1939 | 224 | assert(!_init_done, "once"); |
duke@435 | 225 | |
duke@435 | 226 | int i=0; |
duke@435 | 227 | // Register usage: |
duke@435 | 228 | // O6: sp |
duke@435 | 229 | // I6: fp |
duke@435 | 230 | // I7: return address |
duke@435 | 231 | // G0: zero |
duke@435 | 232 | // G2: thread |
duke@435 | 233 | // G7: not available |
duke@435 | 234 | // G6: not available |
duke@435 | 235 | /* 0 */ map_register(i++, L0); |
duke@435 | 236 | /* 1 */ map_register(i++, L1); |
duke@435 | 237 | /* 2 */ map_register(i++, L2); |
duke@435 | 238 | /* 3 */ map_register(i++, L3); |
duke@435 | 239 | /* 4 */ map_register(i++, L4); |
duke@435 | 240 | /* 5 */ map_register(i++, L5); |
duke@435 | 241 | /* 6 */ map_register(i++, L6); |
duke@435 | 242 | /* 7 */ map_register(i++, L7); |
duke@435 | 243 | |
duke@435 | 244 | /* 8 */ map_register(i++, I0); |
duke@435 | 245 | /* 9 */ map_register(i++, I1); |
duke@435 | 246 | /* 10 */ map_register(i++, I2); |
duke@435 | 247 | /* 11 */ map_register(i++, I3); |
duke@435 | 248 | /* 12 */ map_register(i++, I4); |
duke@435 | 249 | /* 13 */ map_register(i++, I5); |
duke@435 | 250 | /* 14 */ map_register(i++, O0); |
duke@435 | 251 | /* 15 */ map_register(i++, O1); |
duke@435 | 252 | /* 16 */ map_register(i++, O2); |
duke@435 | 253 | /* 17 */ map_register(i++, O3); |
duke@435 | 254 | /* 18 */ map_register(i++, O4); |
duke@435 | 255 | /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) |
duke@435 | 256 | /* 20 */ map_register(i++, G1); |
duke@435 | 257 | /* 21 */ map_register(i++, G3); |
duke@435 | 258 | /* 22 */ map_register(i++, G4); |
duke@435 | 259 | /* 23 */ map_register(i++, G5); |
duke@435 | 260 | /* 24 */ map_register(i++, G0); |
duke@435 | 261 | |
duke@435 | 262 | // the following registers are not normally available |
duke@435 | 263 | /* 25 */ map_register(i++, O7); |
duke@435 | 264 | /* 26 */ map_register(i++, G2); |
duke@435 | 265 | /* 27 */ map_register(i++, O6); |
duke@435 | 266 | /* 28 */ map_register(i++, I6); |
duke@435 | 267 | /* 29 */ map_register(i++, I7); |
duke@435 | 268 | /* 30 */ map_register(i++, G6); |
duke@435 | 269 | /* 31 */ map_register(i++, G7); |
duke@435 | 270 | assert(i == nof_cpu_regs, "number of CPU registers"); |
duke@435 | 271 | |
duke@435 | 272 | for (i = 0; i < nof_fpu_regs; i++) { |
duke@435 | 273 | _fpu_regs[i] = as_FloatRegister(i); |
duke@435 | 274 | } |
duke@435 | 275 | |
duke@435 | 276 | _init_done = true; |
duke@435 | 277 | |
duke@435 | 278 | in_long_opr = as_long_opr(I0); |
duke@435 | 279 | out_long_opr = as_long_opr(O0); |
iveresov@2138 | 280 | g1_long_single_opr = as_long_single_opr(G1); |
duke@435 | 281 | |
duke@435 | 282 | G0_opr = as_opr(G0); |
duke@435 | 283 | G1_opr = as_opr(G1); |
duke@435 | 284 | G2_opr = as_opr(G2); |
duke@435 | 285 | G3_opr = as_opr(G3); |
duke@435 | 286 | G4_opr = as_opr(G4); |
duke@435 | 287 | G5_opr = as_opr(G5); |
duke@435 | 288 | G6_opr = as_opr(G6); |
duke@435 | 289 | G7_opr = as_opr(G7); |
duke@435 | 290 | O0_opr = as_opr(O0); |
duke@435 | 291 | O1_opr = as_opr(O1); |
duke@435 | 292 | O2_opr = as_opr(O2); |
duke@435 | 293 | O3_opr = as_opr(O3); |
duke@435 | 294 | O4_opr = as_opr(O4); |
duke@435 | 295 | O5_opr = as_opr(O5); |
duke@435 | 296 | O6_opr = as_opr(O6); |
duke@435 | 297 | O7_opr = as_opr(O7); |
duke@435 | 298 | L0_opr = as_opr(L0); |
duke@435 | 299 | L1_opr = as_opr(L1); |
duke@435 | 300 | L2_opr = as_opr(L2); |
duke@435 | 301 | L3_opr = as_opr(L3); |
duke@435 | 302 | L4_opr = as_opr(L4); |
duke@435 | 303 | L5_opr = as_opr(L5); |
duke@435 | 304 | L6_opr = as_opr(L6); |
duke@435 | 305 | L7_opr = as_opr(L7); |
duke@435 | 306 | I0_opr = as_opr(I0); |
duke@435 | 307 | I1_opr = as_opr(I1); |
duke@435 | 308 | I2_opr = as_opr(I2); |
duke@435 | 309 | I3_opr = as_opr(I3); |
duke@435 | 310 | I4_opr = as_opr(I4); |
duke@435 | 311 | I5_opr = as_opr(I5); |
duke@435 | 312 | I6_opr = as_opr(I6); |
duke@435 | 313 | I7_opr = as_opr(I7); |
duke@435 | 314 | |
duke@435 | 315 | G0_oop_opr = as_oop_opr(G0); |
duke@435 | 316 | G1_oop_opr = as_oop_opr(G1); |
duke@435 | 317 | G2_oop_opr = as_oop_opr(G2); |
duke@435 | 318 | G3_oop_opr = as_oop_opr(G3); |
duke@435 | 319 | G4_oop_opr = as_oop_opr(G4); |
duke@435 | 320 | G5_oop_opr = as_oop_opr(G5); |
duke@435 | 321 | G6_oop_opr = as_oop_opr(G6); |
duke@435 | 322 | G7_oop_opr = as_oop_opr(G7); |
duke@435 | 323 | O0_oop_opr = as_oop_opr(O0); |
duke@435 | 324 | O1_oop_opr = as_oop_opr(O1); |
duke@435 | 325 | O2_oop_opr = as_oop_opr(O2); |
duke@435 | 326 | O3_oop_opr = as_oop_opr(O3); |
duke@435 | 327 | O4_oop_opr = as_oop_opr(O4); |
duke@435 | 328 | O5_oop_opr = as_oop_opr(O5); |
duke@435 | 329 | O6_oop_opr = as_oop_opr(O6); |
duke@435 | 330 | O7_oop_opr = as_oop_opr(O7); |
duke@435 | 331 | L0_oop_opr = as_oop_opr(L0); |
duke@435 | 332 | L1_oop_opr = as_oop_opr(L1); |
duke@435 | 333 | L2_oop_opr = as_oop_opr(L2); |
duke@435 | 334 | L3_oop_opr = as_oop_opr(L3); |
duke@435 | 335 | L4_oop_opr = as_oop_opr(L4); |
duke@435 | 336 | L5_oop_opr = as_oop_opr(L5); |
duke@435 | 337 | L6_oop_opr = as_oop_opr(L6); |
duke@435 | 338 | L7_oop_opr = as_oop_opr(L7); |
duke@435 | 339 | I0_oop_opr = as_oop_opr(I0); |
duke@435 | 340 | I1_oop_opr = as_oop_opr(I1); |
duke@435 | 341 | I2_oop_opr = as_oop_opr(I2); |
duke@435 | 342 | I3_oop_opr = as_oop_opr(I3); |
duke@435 | 343 | I4_oop_opr = as_oop_opr(I4); |
duke@435 | 344 | I5_oop_opr = as_oop_opr(I5); |
duke@435 | 345 | I6_oop_opr = as_oop_opr(I6); |
duke@435 | 346 | I7_oop_opr = as_oop_opr(I7); |
duke@435 | 347 | |
roland@4051 | 348 | G0_metadata_opr = as_metadata_opr(G0); |
roland@4051 | 349 | G1_metadata_opr = as_metadata_opr(G1); |
roland@4051 | 350 | G2_metadata_opr = as_metadata_opr(G2); |
roland@4051 | 351 | G3_metadata_opr = as_metadata_opr(G3); |
roland@4051 | 352 | G4_metadata_opr = as_metadata_opr(G4); |
roland@4051 | 353 | G5_metadata_opr = as_metadata_opr(G5); |
roland@4051 | 354 | G6_metadata_opr = as_metadata_opr(G6); |
roland@4051 | 355 | G7_metadata_opr = as_metadata_opr(G7); |
roland@4051 | 356 | O0_metadata_opr = as_metadata_opr(O0); |
roland@4051 | 357 | O1_metadata_opr = as_metadata_opr(O1); |
roland@4051 | 358 | O2_metadata_opr = as_metadata_opr(O2); |
roland@4051 | 359 | O3_metadata_opr = as_metadata_opr(O3); |
roland@4051 | 360 | O4_metadata_opr = as_metadata_opr(O4); |
roland@4051 | 361 | O5_metadata_opr = as_metadata_opr(O5); |
roland@4051 | 362 | O6_metadata_opr = as_metadata_opr(O6); |
roland@4051 | 363 | O7_metadata_opr = as_metadata_opr(O7); |
roland@4051 | 364 | L0_metadata_opr = as_metadata_opr(L0); |
roland@4051 | 365 | L1_metadata_opr = as_metadata_opr(L1); |
roland@4051 | 366 | L2_metadata_opr = as_metadata_opr(L2); |
roland@4051 | 367 | L3_metadata_opr = as_metadata_opr(L3); |
roland@4051 | 368 | L4_metadata_opr = as_metadata_opr(L4); |
roland@4051 | 369 | L5_metadata_opr = as_metadata_opr(L5); |
roland@4051 | 370 | L6_metadata_opr = as_metadata_opr(L6); |
roland@4051 | 371 | L7_metadata_opr = as_metadata_opr(L7); |
roland@4051 | 372 | I0_metadata_opr = as_metadata_opr(I0); |
roland@4051 | 373 | I1_metadata_opr = as_metadata_opr(I1); |
roland@4051 | 374 | I2_metadata_opr = as_metadata_opr(I2); |
roland@4051 | 375 | I3_metadata_opr = as_metadata_opr(I3); |
roland@4051 | 376 | I4_metadata_opr = as_metadata_opr(I4); |
roland@4051 | 377 | I5_metadata_opr = as_metadata_opr(I5); |
roland@4051 | 378 | I6_metadata_opr = as_metadata_opr(I6); |
roland@4051 | 379 | I7_metadata_opr = as_metadata_opr(I7); |
roland@4051 | 380 | |
duke@435 | 381 | FP_opr = as_pointer_opr(FP); |
duke@435 | 382 | SP_opr = as_pointer_opr(SP); |
duke@435 | 383 | |
duke@435 | 384 | F0_opr = as_float_opr(F0); |
duke@435 | 385 | F0_double_opr = as_double_opr(F0); |
duke@435 | 386 | |
duke@435 | 387 | Oexception_opr = as_oop_opr(Oexception); |
duke@435 | 388 | Oissuing_pc_opr = as_opr(Oissuing_pc); |
duke@435 | 389 | |
duke@435 | 390 | _caller_save_cpu_regs[0] = FrameMap::O0_opr; |
duke@435 | 391 | _caller_save_cpu_regs[1] = FrameMap::O1_opr; |
duke@435 | 392 | _caller_save_cpu_regs[2] = FrameMap::O2_opr; |
duke@435 | 393 | _caller_save_cpu_regs[3] = FrameMap::O3_opr; |
duke@435 | 394 | _caller_save_cpu_regs[4] = FrameMap::O4_opr; |
duke@435 | 395 | _caller_save_cpu_regs[5] = FrameMap::O5_opr; |
never@1363 | 396 | _caller_save_cpu_regs[6] = FrameMap::G1_opr; |
never@1363 | 397 | _caller_save_cpu_regs[7] = FrameMap::G3_opr; |
never@1363 | 398 | _caller_save_cpu_regs[8] = FrameMap::G4_opr; |
never@1363 | 399 | _caller_save_cpu_regs[9] = FrameMap::G5_opr; |
duke@435 | 400 | for (int i = 0; i < nof_caller_save_fpu_regs; i++) { |
duke@435 | 401 | _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); |
duke@435 | 402 | } |
duke@435 | 403 | } |
duke@435 | 404 | |
duke@435 | 405 | |
duke@435 | 406 | Address FrameMap::make_new_address(ByteSize sp_offset) const { |
twisti@1162 | 407 | return Address(SP, STACK_BIAS + in_bytes(sp_offset)); |
duke@435 | 408 | } |
duke@435 | 409 | |
duke@435 | 410 | |
duke@435 | 411 | VMReg FrameMap::fpu_regname (int n) { |
duke@435 | 412 | return as_FloatRegister(n)->as_VMReg(); |
duke@435 | 413 | } |
duke@435 | 414 | |
duke@435 | 415 | |
duke@435 | 416 | LIR_Opr FrameMap::stack_pointer() { |
duke@435 | 417 | return SP_opr; |
duke@435 | 418 | } |
duke@435 | 419 | |
duke@435 | 420 | |
twisti@1919 | 421 | // JSR 292 |
twisti@1919 | 422 | LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
twisti@1919 | 423 | assert(L7 == L7_mh_SP_save, "must be same register"); |
twisti@1919 | 424 | return L7_opr; |
twisti@1919 | 425 | } |
twisti@1919 | 426 | |
twisti@1919 | 427 | |
duke@435 | 428 | bool FrameMap::validate_frame() { |
duke@435 | 429 | int max_offset = in_bytes(framesize_in_bytes()); |
duke@435 | 430 | int java_index = 0; |
duke@435 | 431 | for (int i = 0; i < _incoming_arguments->length(); i++) { |
duke@435 | 432 | LIR_Opr opr = _incoming_arguments->at(i); |
duke@435 | 433 | if (opr->is_stack()) { |
duke@435 | 434 | max_offset = MAX2(_argument_locations->at(java_index), max_offset); |
duke@435 | 435 | } |
duke@435 | 436 | java_index += type2size[opr->type()]; |
duke@435 | 437 | } |
duke@435 | 438 | return Assembler::is_simm13(max_offset + STACK_BIAS); |
duke@435 | 439 | } |