Thu, 21 Aug 2008 23:36:31 -0400
Merge
duke@435 | 1 | /* |
xdono@631 | 2 | * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | #include "incls/_precompiled.incl" |
duke@435 | 26 | #include "incls/_assembler_x86_32.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | // Implementation of AddressLiteral |
duke@435 | 29 | |
duke@435 | 30 | AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { |
duke@435 | 31 | _is_lval = false; |
duke@435 | 32 | _target = target; |
duke@435 | 33 | switch (rtype) { |
duke@435 | 34 | case relocInfo::oop_type: |
duke@435 | 35 | // Oops are a special case. Normally they would be their own section |
duke@435 | 36 | // but in cases like icBuffer they are literals in the code stream that |
duke@435 | 37 | // we don't have a section for. We use none so that we get a literal address |
duke@435 | 38 | // which is always patchable. |
duke@435 | 39 | break; |
duke@435 | 40 | case relocInfo::external_word_type: |
duke@435 | 41 | _rspec = external_word_Relocation::spec(target); |
duke@435 | 42 | break; |
duke@435 | 43 | case relocInfo::internal_word_type: |
duke@435 | 44 | _rspec = internal_word_Relocation::spec(target); |
duke@435 | 45 | break; |
duke@435 | 46 | case relocInfo::opt_virtual_call_type: |
duke@435 | 47 | _rspec = opt_virtual_call_Relocation::spec(); |
duke@435 | 48 | break; |
duke@435 | 49 | case relocInfo::static_call_type: |
duke@435 | 50 | _rspec = static_call_Relocation::spec(); |
duke@435 | 51 | break; |
duke@435 | 52 | case relocInfo::runtime_call_type: |
duke@435 | 53 | _rspec = runtime_call_Relocation::spec(); |
duke@435 | 54 | break; |
duke@435 | 55 | case relocInfo::poll_type: |
duke@435 | 56 | case relocInfo::poll_return_type: |
duke@435 | 57 | _rspec = Relocation::spec_simple(rtype); |
duke@435 | 58 | break; |
duke@435 | 59 | case relocInfo::none: |
duke@435 | 60 | break; |
duke@435 | 61 | default: |
duke@435 | 62 | ShouldNotReachHere(); |
duke@435 | 63 | break; |
duke@435 | 64 | } |
duke@435 | 65 | } |
duke@435 | 66 | |
duke@435 | 67 | // Implementation of Address |
duke@435 | 68 | |
duke@435 | 69 | Address Address::make_array(ArrayAddress adr) { |
duke@435 | 70 | #ifdef _LP64 |
duke@435 | 71 | // Not implementable on 64bit machines |
duke@435 | 72 | // Should have been handled higher up the call chain. |
duke@435 | 73 | ShouldNotReachHere(); |
duke@435 | 74 | #else |
duke@435 | 75 | AddressLiteral base = adr.base(); |
duke@435 | 76 | Address index = adr.index(); |
duke@435 | 77 | assert(index._disp == 0, "must not have disp"); // maybe it can? |
duke@435 | 78 | Address array(index._base, index._index, index._scale, (intptr_t) base.target()); |
duke@435 | 79 | array._rspec = base._rspec; |
duke@435 | 80 | return array; |
duke@435 | 81 | #endif // _LP64 |
duke@435 | 82 | } |
duke@435 | 83 | |
duke@435 | 84 | #ifndef _LP64 |
duke@435 | 85 | |
duke@435 | 86 | // exceedingly dangerous constructor |
duke@435 | 87 | Address::Address(address loc, RelocationHolder spec) { |
duke@435 | 88 | _base = noreg; |
duke@435 | 89 | _index = noreg; |
duke@435 | 90 | _scale = no_scale; |
duke@435 | 91 | _disp = (intptr_t) loc; |
duke@435 | 92 | _rspec = spec; |
duke@435 | 93 | } |
duke@435 | 94 | #endif // _LP64 |
duke@435 | 95 | |
duke@435 | 96 | // Convert the raw encoding form into the form expected by the constructor for |
duke@435 | 97 | // Address. An index of 4 (rsp) corresponds to having no index, so convert |
duke@435 | 98 | // that to noreg for the Address constructor. |
duke@435 | 99 | Address Address::make_raw(int base, int index, int scale, int disp) { |
duke@435 | 100 | bool valid_index = index != rsp->encoding(); |
duke@435 | 101 | if (valid_index) { |
duke@435 | 102 | Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); |
duke@435 | 103 | return madr; |
duke@435 | 104 | } else { |
duke@435 | 105 | Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); |
duke@435 | 106 | return madr; |
duke@435 | 107 | } |
duke@435 | 108 | } |
duke@435 | 109 | |
duke@435 | 110 | // Implementation of Assembler |
duke@435 | 111 | |
duke@435 | 112 | int AbstractAssembler::code_fill_byte() { |
duke@435 | 113 | return (u_char)'\xF4'; // hlt |
duke@435 | 114 | } |
duke@435 | 115 | |
duke@435 | 116 | // make this go away someday |
duke@435 | 117 | void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { |
duke@435 | 118 | if (rtype == relocInfo::none) |
duke@435 | 119 | emit_long(data); |
duke@435 | 120 | else emit_data(data, Relocation::spec_simple(rtype), format); |
duke@435 | 121 | } |
duke@435 | 122 | |
duke@435 | 123 | |
duke@435 | 124 | void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { |
duke@435 | 125 | assert(imm32_operand == 0, "default format must be imm32 in this file"); |
duke@435 | 126 | assert(inst_mark() != NULL, "must be inside InstructionMark"); |
duke@435 | 127 | if (rspec.type() != relocInfo::none) { |
duke@435 | 128 | #ifdef ASSERT |
duke@435 | 129 | check_relocation(rspec, format); |
duke@435 | 130 | #endif |
duke@435 | 131 | // Do not use AbstractAssembler::relocate, which is not intended for |
duke@435 | 132 | // embedded words. Instead, relocate to the enclosing instruction. |
duke@435 | 133 | |
duke@435 | 134 | // hack. call32 is too wide for mask so use disp32 |
duke@435 | 135 | if (format == call32_operand) |
duke@435 | 136 | code_section()->relocate(inst_mark(), rspec, disp32_operand); |
duke@435 | 137 | else |
duke@435 | 138 | code_section()->relocate(inst_mark(), rspec, format); |
duke@435 | 139 | } |
duke@435 | 140 | emit_long(data); |
duke@435 | 141 | } |
duke@435 | 142 | |
duke@435 | 143 | |
duke@435 | 144 | void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { |
duke@435 | 145 | assert(dst->has_byte_register(), "must have byte register"); |
duke@435 | 146 | assert(isByte(op1) && isByte(op2), "wrong opcode"); |
duke@435 | 147 | assert(isByte(imm8), "not a byte"); |
duke@435 | 148 | assert((op1 & 0x01) == 0, "should be 8bit operation"); |
duke@435 | 149 | emit_byte(op1); |
duke@435 | 150 | emit_byte(op2 | dst->encoding()); |
duke@435 | 151 | emit_byte(imm8); |
duke@435 | 152 | } |
duke@435 | 153 | |
duke@435 | 154 | |
duke@435 | 155 | void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) { |
duke@435 | 156 | assert(isByte(op1) && isByte(op2), "wrong opcode"); |
duke@435 | 157 | assert((op1 & 0x01) == 1, "should be 32bit operation"); |
duke@435 | 158 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
duke@435 | 159 | if (is8bit(imm32)) { |
duke@435 | 160 | emit_byte(op1 | 0x02); // set sign bit |
duke@435 | 161 | emit_byte(op2 | dst->encoding()); |
duke@435 | 162 | emit_byte(imm32 & 0xFF); |
duke@435 | 163 | } else { |
duke@435 | 164 | emit_byte(op1); |
duke@435 | 165 | emit_byte(op2 | dst->encoding()); |
duke@435 | 166 | emit_long(imm32); |
duke@435 | 167 | } |
duke@435 | 168 | } |
duke@435 | 169 | |
duke@435 | 170 | // immediate-to-memory forms |
duke@435 | 171 | void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) { |
duke@435 | 172 | assert((op1 & 0x01) == 1, "should be 32bit operation"); |
duke@435 | 173 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
duke@435 | 174 | if (is8bit(imm32)) { |
duke@435 | 175 | emit_byte(op1 | 0x02); // set sign bit |
duke@435 | 176 | emit_operand(rm,adr); |
duke@435 | 177 | emit_byte(imm32 & 0xFF); |
duke@435 | 178 | } else { |
duke@435 | 179 | emit_byte(op1); |
duke@435 | 180 | emit_operand(rm,adr); |
duke@435 | 181 | emit_long(imm32); |
duke@435 | 182 | } |
duke@435 | 183 | } |
duke@435 | 184 | |
duke@435 | 185 | void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { |
duke@435 | 186 | assert(isByte(op1) && isByte(op2), "wrong opcode"); |
duke@435 | 187 | assert((op1 & 0x01) == 1, "should be 32bit operation"); |
duke@435 | 188 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
duke@435 | 189 | InstructionMark im(this); |
duke@435 | 190 | emit_byte(op1); |
duke@435 | 191 | emit_byte(op2 | dst->encoding()); |
duke@435 | 192 | emit_data((int)obj, relocInfo::oop_type, 0); |
duke@435 | 193 | } |
duke@435 | 194 | |
duke@435 | 195 | |
duke@435 | 196 | void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { |
duke@435 | 197 | assert(isByte(op1) && isByte(op2), "wrong opcode"); |
duke@435 | 198 | emit_byte(op1); |
duke@435 | 199 | emit_byte(op2 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 200 | } |
duke@435 | 201 | |
duke@435 | 202 | |
duke@435 | 203 | void Assembler::emit_operand(Register reg, |
duke@435 | 204 | Register base, |
duke@435 | 205 | Register index, |
duke@435 | 206 | Address::ScaleFactor scale, |
duke@435 | 207 | int disp, |
duke@435 | 208 | RelocationHolder const& rspec) { |
duke@435 | 209 | |
duke@435 | 210 | relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
duke@435 | 211 | if (base->is_valid()) { |
duke@435 | 212 | if (index->is_valid()) { |
duke@435 | 213 | assert(scale != Address::no_scale, "inconsistent address"); |
duke@435 | 214 | // [base + index*scale + disp] |
duke@435 | 215 | if (disp == 0 && rtype == relocInfo::none && base != rbp) { |
duke@435 | 216 | // [base + index*scale] |
duke@435 | 217 | // [00 reg 100][ss index base] |
duke@435 | 218 | assert(index != rsp, "illegal addressing mode"); |
duke@435 | 219 | emit_byte(0x04 | reg->encoding() << 3); |
duke@435 | 220 | emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); |
duke@435 | 221 | } else if (is8bit(disp) && rtype == relocInfo::none) { |
duke@435 | 222 | // [base + index*scale + imm8] |
duke@435 | 223 | // [01 reg 100][ss index base] imm8 |
duke@435 | 224 | assert(index != rsp, "illegal addressing mode"); |
duke@435 | 225 | emit_byte(0x44 | reg->encoding() << 3); |
duke@435 | 226 | emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); |
duke@435 | 227 | emit_byte(disp & 0xFF); |
duke@435 | 228 | } else { |
duke@435 | 229 | // [base + index*scale + imm32] |
duke@435 | 230 | // [10 reg 100][ss index base] imm32 |
duke@435 | 231 | assert(index != rsp, "illegal addressing mode"); |
duke@435 | 232 | emit_byte(0x84 | reg->encoding() << 3); |
duke@435 | 233 | emit_byte(scale << 6 | index->encoding() << 3 | base->encoding()); |
duke@435 | 234 | emit_data(disp, rspec, disp32_operand); |
duke@435 | 235 | } |
duke@435 | 236 | } else if (base == rsp) { |
duke@435 | 237 | // [esp + disp] |
duke@435 | 238 | if (disp == 0 && rtype == relocInfo::none) { |
duke@435 | 239 | // [esp] |
duke@435 | 240 | // [00 reg 100][00 100 100] |
duke@435 | 241 | emit_byte(0x04 | reg->encoding() << 3); |
duke@435 | 242 | emit_byte(0x24); |
duke@435 | 243 | } else if (is8bit(disp) && rtype == relocInfo::none) { |
duke@435 | 244 | // [esp + imm8] |
duke@435 | 245 | // [01 reg 100][00 100 100] imm8 |
duke@435 | 246 | emit_byte(0x44 | reg->encoding() << 3); |
duke@435 | 247 | emit_byte(0x24); |
duke@435 | 248 | emit_byte(disp & 0xFF); |
duke@435 | 249 | } else { |
duke@435 | 250 | // [esp + imm32] |
duke@435 | 251 | // [10 reg 100][00 100 100] imm32 |
duke@435 | 252 | emit_byte(0x84 | reg->encoding() << 3); |
duke@435 | 253 | emit_byte(0x24); |
duke@435 | 254 | emit_data(disp, rspec, disp32_operand); |
duke@435 | 255 | } |
duke@435 | 256 | } else { |
duke@435 | 257 | // [base + disp] |
duke@435 | 258 | assert(base != rsp, "illegal addressing mode"); |
duke@435 | 259 | if (disp == 0 && rtype == relocInfo::none && base != rbp) { |
duke@435 | 260 | // [base] |
duke@435 | 261 | // [00 reg base] |
duke@435 | 262 | assert(base != rbp, "illegal addressing mode"); |
duke@435 | 263 | emit_byte(0x00 | reg->encoding() << 3 | base->encoding()); |
duke@435 | 264 | } else if (is8bit(disp) && rtype == relocInfo::none) { |
duke@435 | 265 | // [base + imm8] |
duke@435 | 266 | // [01 reg base] imm8 |
duke@435 | 267 | emit_byte(0x40 | reg->encoding() << 3 | base->encoding()); |
duke@435 | 268 | emit_byte(disp & 0xFF); |
duke@435 | 269 | } else { |
duke@435 | 270 | // [base + imm32] |
duke@435 | 271 | // [10 reg base] imm32 |
duke@435 | 272 | emit_byte(0x80 | reg->encoding() << 3 | base->encoding()); |
duke@435 | 273 | emit_data(disp, rspec, disp32_operand); |
duke@435 | 274 | } |
duke@435 | 275 | } |
duke@435 | 276 | } else { |
duke@435 | 277 | if (index->is_valid()) { |
duke@435 | 278 | assert(scale != Address::no_scale, "inconsistent address"); |
duke@435 | 279 | // [index*scale + disp] |
duke@435 | 280 | // [00 reg 100][ss index 101] imm32 |
duke@435 | 281 | assert(index != rsp, "illegal addressing mode"); |
duke@435 | 282 | emit_byte(0x04 | reg->encoding() << 3); |
duke@435 | 283 | emit_byte(scale << 6 | index->encoding() << 3 | 0x05); |
duke@435 | 284 | emit_data(disp, rspec, disp32_operand); |
duke@435 | 285 | } else { |
duke@435 | 286 | // [disp] |
duke@435 | 287 | // [00 reg 101] imm32 |
duke@435 | 288 | emit_byte(0x05 | reg->encoding() << 3); |
duke@435 | 289 | emit_data(disp, rspec, disp32_operand); |
duke@435 | 290 | } |
duke@435 | 291 | } |
duke@435 | 292 | } |
duke@435 | 293 | |
duke@435 | 294 | // Secret local extension to Assembler::WhichOperand: |
duke@435 | 295 | #define end_pc_operand (_WhichOperand_limit) |
duke@435 | 296 | |
duke@435 | 297 | address Assembler::locate_operand(address inst, WhichOperand which) { |
duke@435 | 298 | // Decode the given instruction, and return the address of |
duke@435 | 299 | // an embedded 32-bit operand word. |
duke@435 | 300 | |
duke@435 | 301 | // If "which" is disp32_operand, selects the displacement portion |
duke@435 | 302 | // of an effective address specifier. |
duke@435 | 303 | // If "which" is imm32_operand, selects the trailing immediate constant. |
duke@435 | 304 | // If "which" is call32_operand, selects the displacement of a call or jump. |
duke@435 | 305 | // Caller is responsible for ensuring that there is such an operand, |
duke@435 | 306 | // and that it is 32 bits wide. |
duke@435 | 307 | |
duke@435 | 308 | // If "which" is end_pc_operand, find the end of the instruction. |
duke@435 | 309 | |
duke@435 | 310 | address ip = inst; |
duke@435 | 311 | |
duke@435 | 312 | debug_only(bool has_imm32 = false); |
duke@435 | 313 | int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn |
duke@435 | 314 | |
duke@435 | 315 | again_after_prefix: |
duke@435 | 316 | switch (0xFF & *ip++) { |
duke@435 | 317 | |
duke@435 | 318 | // These convenience macros generate groups of "case" labels for the switch. |
duke@435 | 319 | #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
duke@435 | 320 | #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ |
duke@435 | 321 | case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
duke@435 | 322 | #define REP16(x) REP8((x)+0): \ |
duke@435 | 323 | case REP8((x)+8) |
duke@435 | 324 | |
duke@435 | 325 | case CS_segment: |
duke@435 | 326 | case SS_segment: |
duke@435 | 327 | case DS_segment: |
duke@435 | 328 | case ES_segment: |
duke@435 | 329 | case FS_segment: |
duke@435 | 330 | case GS_segment: |
duke@435 | 331 | assert(ip == inst+1, "only one prefix allowed"); |
duke@435 | 332 | goto again_after_prefix; |
duke@435 | 333 | |
duke@435 | 334 | case 0xFF: // pushl a; decl a; incl a; call a; jmp a |
duke@435 | 335 | case 0x88: // movb a, r |
duke@435 | 336 | case 0x89: // movl a, r |
duke@435 | 337 | case 0x8A: // movb r, a |
duke@435 | 338 | case 0x8B: // movl r, a |
duke@435 | 339 | case 0x8F: // popl a |
duke@435 | 340 | break; |
duke@435 | 341 | |
duke@435 | 342 | case 0x68: // pushl #32(oop?) |
duke@435 | 343 | if (which == end_pc_operand) return ip + 4; |
duke@435 | 344 | assert(which == imm32_operand, "pushl has no disp32"); |
duke@435 | 345 | return ip; // not produced by emit_operand |
duke@435 | 346 | |
duke@435 | 347 | case 0x66: // movw ... (size prefix) |
duke@435 | 348 | switch (0xFF & *ip++) { |
duke@435 | 349 | case 0x8B: // movw r, a |
duke@435 | 350 | case 0x89: // movw a, r |
duke@435 | 351 | break; |
duke@435 | 352 | case 0xC7: // movw a, #16 |
duke@435 | 353 | tail_size = 2; // the imm16 |
duke@435 | 354 | break; |
duke@435 | 355 | case 0x0F: // several SSE/SSE2 variants |
duke@435 | 356 | ip--; // reparse the 0x0F |
duke@435 | 357 | goto again_after_prefix; |
duke@435 | 358 | default: |
duke@435 | 359 | ShouldNotReachHere(); |
duke@435 | 360 | } |
duke@435 | 361 | break; |
duke@435 | 362 | |
duke@435 | 363 | case REP8(0xB8): // movl r, #32(oop?) |
duke@435 | 364 | if (which == end_pc_operand) return ip + 4; |
duke@435 | 365 | assert(which == imm32_operand || which == disp32_operand, ""); |
duke@435 | 366 | return ip; |
duke@435 | 367 | |
duke@435 | 368 | case 0x69: // imul r, a, #32 |
duke@435 | 369 | case 0xC7: // movl a, #32(oop?) |
duke@435 | 370 | tail_size = 4; |
duke@435 | 371 | debug_only(has_imm32 = true); // has both kinds of operands! |
duke@435 | 372 | break; |
duke@435 | 373 | |
duke@435 | 374 | case 0x0F: // movx..., etc. |
duke@435 | 375 | switch (0xFF & *ip++) { |
duke@435 | 376 | case 0x12: // movlps |
duke@435 | 377 | case 0x28: // movaps |
duke@435 | 378 | case 0x2E: // ucomiss |
duke@435 | 379 | case 0x2F: // comiss |
duke@435 | 380 | case 0x54: // andps |
duke@435 | 381 | case 0x55: // andnps |
duke@435 | 382 | case 0x56: // orps |
duke@435 | 383 | case 0x57: // xorps |
duke@435 | 384 | case 0x6E: // movd |
duke@435 | 385 | case 0x7E: // movd |
duke@435 | 386 | case 0xAE: // ldmxcsr a |
duke@435 | 387 | // amd side says it these have both operands but that doesn't |
duke@435 | 388 | // appear to be true. |
duke@435 | 389 | // debug_only(has_imm32 = true); // has both kinds of operands! |
duke@435 | 390 | break; |
duke@435 | 391 | |
duke@435 | 392 | case 0xAD: // shrd r, a, %cl |
duke@435 | 393 | case 0xAF: // imul r, a |
duke@435 | 394 | case 0xBE: // movsxb r, a |
duke@435 | 395 | case 0xBF: // movsxw r, a |
duke@435 | 396 | case 0xB6: // movzxb r, a |
duke@435 | 397 | case 0xB7: // movzxw r, a |
duke@435 | 398 | case REP16(0x40): // cmovl cc, r, a |
duke@435 | 399 | case 0xB0: // cmpxchgb |
duke@435 | 400 | case 0xB1: // cmpxchg |
duke@435 | 401 | case 0xC1: // xaddl |
duke@435 | 402 | case 0xC7: // cmpxchg8 |
duke@435 | 403 | case REP16(0x90): // setcc a |
duke@435 | 404 | // fall out of the switch to decode the address |
duke@435 | 405 | break; |
duke@435 | 406 | case 0xAC: // shrd r, a, #8 |
duke@435 | 407 | tail_size = 1; // the imm8 |
duke@435 | 408 | break; |
duke@435 | 409 | case REP16(0x80): // jcc rdisp32 |
duke@435 | 410 | if (which == end_pc_operand) return ip + 4; |
duke@435 | 411 | assert(which == call32_operand, "jcc has no disp32 or imm32"); |
duke@435 | 412 | return ip; |
duke@435 | 413 | default: |
duke@435 | 414 | ShouldNotReachHere(); |
duke@435 | 415 | } |
duke@435 | 416 | break; |
duke@435 | 417 | |
duke@435 | 418 | case 0x81: // addl a, #32; addl r, #32 |
duke@435 | 419 | // also: orl, adcl, sbbl, andl, subl, xorl, cmpl |
duke@435 | 420 | // in the case of cmpl, the imm32 might be an oop |
duke@435 | 421 | tail_size = 4; |
duke@435 | 422 | debug_only(has_imm32 = true); // has both kinds of operands! |
duke@435 | 423 | break; |
duke@435 | 424 | |
duke@435 | 425 | case 0x85: // test r/m, r |
duke@435 | 426 | break; |
duke@435 | 427 | |
duke@435 | 428 | case 0x83: // addl a, #8; addl r, #8 |
duke@435 | 429 | // also: orl, adcl, sbbl, andl, subl, xorl, cmpl |
duke@435 | 430 | tail_size = 1; |
duke@435 | 431 | break; |
duke@435 | 432 | |
duke@435 | 433 | case 0x9B: |
duke@435 | 434 | switch (0xFF & *ip++) { |
duke@435 | 435 | case 0xD9: // fnstcw a |
duke@435 | 436 | break; |
duke@435 | 437 | default: |
duke@435 | 438 | ShouldNotReachHere(); |
duke@435 | 439 | } |
duke@435 | 440 | break; |
duke@435 | 441 | |
duke@435 | 442 | case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a |
duke@435 | 443 | case REP4(0x10): // adc... |
duke@435 | 444 | case REP4(0x20): // and... |
duke@435 | 445 | case REP4(0x30): // xor... |
duke@435 | 446 | case REP4(0x08): // or... |
duke@435 | 447 | case REP4(0x18): // sbb... |
duke@435 | 448 | case REP4(0x28): // sub... |
duke@435 | 449 | case REP4(0x38): // cmp... |
duke@435 | 450 | case 0xF7: // mull a |
duke@435 | 451 | case 0x8D: // leal r, a |
duke@435 | 452 | case 0x87: // xchg r, a |
duke@435 | 453 | break; |
duke@435 | 454 | |
duke@435 | 455 | case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 |
duke@435 | 456 | case 0xC6: // movb a, #8 |
duke@435 | 457 | case 0x80: // cmpb a, #8 |
duke@435 | 458 | case 0x6B: // imul r, a, #8 |
duke@435 | 459 | tail_size = 1; // the imm8 |
duke@435 | 460 | break; |
duke@435 | 461 | |
duke@435 | 462 | case 0xE8: // call rdisp32 |
duke@435 | 463 | case 0xE9: // jmp rdisp32 |
duke@435 | 464 | if (which == end_pc_operand) return ip + 4; |
duke@435 | 465 | assert(which == call32_operand, "call has no disp32 or imm32"); |
duke@435 | 466 | return ip; |
duke@435 | 467 | |
duke@435 | 468 | case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 |
duke@435 | 469 | case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl |
duke@435 | 470 | case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a |
duke@435 | 471 | case 0xDD: // fld_d a; fst_d a; fstp_d a |
duke@435 | 472 | case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a |
duke@435 | 473 | case 0xDF: // fild_d a; fistp_d a |
duke@435 | 474 | case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a |
duke@435 | 475 | case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a |
duke@435 | 476 | case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a |
duke@435 | 477 | break; |
duke@435 | 478 | |
duke@435 | 479 | case 0xF3: // For SSE |
duke@435 | 480 | case 0xF2: // For SSE2 |
duke@435 | 481 | ip++; ip++; |
duke@435 | 482 | break; |
duke@435 | 483 | |
duke@435 | 484 | default: |
duke@435 | 485 | ShouldNotReachHere(); |
duke@435 | 486 | |
duke@435 | 487 | #undef REP8 |
duke@435 | 488 | #undef REP16 |
duke@435 | 489 | } |
duke@435 | 490 | |
duke@435 | 491 | assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); |
duke@435 | 492 | assert(which != imm32_operand || has_imm32, "instruction has no imm32 field"); |
duke@435 | 493 | |
duke@435 | 494 | // parse the output of emit_operand |
duke@435 | 495 | int op2 = 0xFF & *ip++; |
duke@435 | 496 | int base = op2 & 0x07; |
duke@435 | 497 | int op3 = -1; |
duke@435 | 498 | const int b100 = 4; |
duke@435 | 499 | const int b101 = 5; |
duke@435 | 500 | if (base == b100 && (op2 >> 6) != 3) { |
duke@435 | 501 | op3 = 0xFF & *ip++; |
duke@435 | 502 | base = op3 & 0x07; // refetch the base |
duke@435 | 503 | } |
duke@435 | 504 | // now ip points at the disp (if any) |
duke@435 | 505 | |
duke@435 | 506 | switch (op2 >> 6) { |
duke@435 | 507 | case 0: |
duke@435 | 508 | // [00 reg 100][ss index base] |
duke@435 | 509 | // [00 reg 100][00 100 rsp] |
duke@435 | 510 | // [00 reg base] |
duke@435 | 511 | // [00 reg 100][ss index 101][disp32] |
duke@435 | 512 | // [00 reg 101] [disp32] |
duke@435 | 513 | |
duke@435 | 514 | if (base == b101) { |
duke@435 | 515 | if (which == disp32_operand) |
duke@435 | 516 | return ip; // caller wants the disp32 |
duke@435 | 517 | ip += 4; // skip the disp32 |
duke@435 | 518 | } |
duke@435 | 519 | break; |
duke@435 | 520 | |
duke@435 | 521 | case 1: |
duke@435 | 522 | // [01 reg 100][ss index base][disp8] |
duke@435 | 523 | // [01 reg 100][00 100 rsp][disp8] |
duke@435 | 524 | // [01 reg base] [disp8] |
duke@435 | 525 | ip += 1; // skip the disp8 |
duke@435 | 526 | break; |
duke@435 | 527 | |
duke@435 | 528 | case 2: |
duke@435 | 529 | // [10 reg 100][ss index base][disp32] |
duke@435 | 530 | // [10 reg 100][00 100 rsp][disp32] |
duke@435 | 531 | // [10 reg base] [disp32] |
duke@435 | 532 | if (which == disp32_operand) |
duke@435 | 533 | return ip; // caller wants the disp32 |
duke@435 | 534 | ip += 4; // skip the disp32 |
duke@435 | 535 | break; |
duke@435 | 536 | |
duke@435 | 537 | case 3: |
duke@435 | 538 | // [11 reg base] (not a memory addressing mode) |
duke@435 | 539 | break; |
duke@435 | 540 | } |
duke@435 | 541 | |
duke@435 | 542 | if (which == end_pc_operand) { |
duke@435 | 543 | return ip + tail_size; |
duke@435 | 544 | } |
duke@435 | 545 | |
duke@435 | 546 | assert(which == imm32_operand, "instruction has only an imm32 field"); |
duke@435 | 547 | return ip; |
duke@435 | 548 | } |
duke@435 | 549 | |
duke@435 | 550 | address Assembler::locate_next_instruction(address inst) { |
duke@435 | 551 | // Secretly share code with locate_operand: |
duke@435 | 552 | return locate_operand(inst, end_pc_operand); |
duke@435 | 553 | } |
duke@435 | 554 | |
duke@435 | 555 | |
duke@435 | 556 | #ifdef ASSERT |
duke@435 | 557 | void Assembler::check_relocation(RelocationHolder const& rspec, int format) { |
duke@435 | 558 | address inst = inst_mark(); |
duke@435 | 559 | assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); |
duke@435 | 560 | address opnd; |
duke@435 | 561 | |
duke@435 | 562 | Relocation* r = rspec.reloc(); |
duke@435 | 563 | if (r->type() == relocInfo::none) { |
duke@435 | 564 | return; |
duke@435 | 565 | } else if (r->is_call() || format == call32_operand) { |
duke@435 | 566 | // assert(format == imm32_operand, "cannot specify a nonzero format"); |
duke@435 | 567 | opnd = locate_operand(inst, call32_operand); |
duke@435 | 568 | } else if (r->is_data()) { |
duke@435 | 569 | assert(format == imm32_operand || format == disp32_operand, "format ok"); |
duke@435 | 570 | opnd = locate_operand(inst, (WhichOperand)format); |
duke@435 | 571 | } else { |
duke@435 | 572 | assert(format == imm32_operand, "cannot specify a format"); |
duke@435 | 573 | return; |
duke@435 | 574 | } |
duke@435 | 575 | assert(opnd == pc(), "must put operand where relocs can find it"); |
duke@435 | 576 | } |
duke@435 | 577 | #endif |
duke@435 | 578 | |
duke@435 | 579 | |
duke@435 | 580 | |
duke@435 | 581 | void Assembler::emit_operand(Register reg, Address adr) { |
duke@435 | 582 | emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); |
duke@435 | 583 | } |
duke@435 | 584 | |
duke@435 | 585 | |
duke@435 | 586 | void Assembler::emit_farith(int b1, int b2, int i) { |
duke@435 | 587 | assert(isByte(b1) && isByte(b2), "wrong opcode"); |
duke@435 | 588 | assert(0 <= i && i < 8, "illegal stack offset"); |
duke@435 | 589 | emit_byte(b1); |
duke@435 | 590 | emit_byte(b2 + i); |
duke@435 | 591 | } |
duke@435 | 592 | |
duke@435 | 593 | |
duke@435 | 594 | void Assembler::pushad() { |
duke@435 | 595 | emit_byte(0x60); |
duke@435 | 596 | } |
duke@435 | 597 | |
duke@435 | 598 | void Assembler::popad() { |
duke@435 | 599 | emit_byte(0x61); |
duke@435 | 600 | } |
duke@435 | 601 | |
duke@435 | 602 | void Assembler::pushfd() { |
duke@435 | 603 | emit_byte(0x9C); |
duke@435 | 604 | } |
duke@435 | 605 | |
duke@435 | 606 | void Assembler::popfd() { |
duke@435 | 607 | emit_byte(0x9D); |
duke@435 | 608 | } |
duke@435 | 609 | |
duke@435 | 610 | void Assembler::pushl(int imm32) { |
duke@435 | 611 | emit_byte(0x68); |
duke@435 | 612 | emit_long(imm32); |
duke@435 | 613 | } |
duke@435 | 614 | |
duke@435 | 615 | #ifndef _LP64 |
duke@435 | 616 | void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { |
duke@435 | 617 | InstructionMark im(this); |
duke@435 | 618 | emit_byte(0x68); |
duke@435 | 619 | emit_data(imm32, rspec, 0); |
duke@435 | 620 | } |
duke@435 | 621 | #endif // _LP64 |
duke@435 | 622 | |
duke@435 | 623 | void Assembler::pushl(Register src) { |
duke@435 | 624 | emit_byte(0x50 | src->encoding()); |
duke@435 | 625 | } |
duke@435 | 626 | |
duke@435 | 627 | |
duke@435 | 628 | void Assembler::pushl(Address src) { |
duke@435 | 629 | InstructionMark im(this); |
duke@435 | 630 | emit_byte(0xFF); |
duke@435 | 631 | emit_operand(rsi, src); |
duke@435 | 632 | } |
duke@435 | 633 | |
duke@435 | 634 | void Assembler::popl(Register dst) { |
duke@435 | 635 | emit_byte(0x58 | dst->encoding()); |
duke@435 | 636 | } |
duke@435 | 637 | |
duke@435 | 638 | |
duke@435 | 639 | void Assembler::popl(Address dst) { |
duke@435 | 640 | InstructionMark im(this); |
duke@435 | 641 | emit_byte(0x8F); |
duke@435 | 642 | emit_operand(rax, dst); |
duke@435 | 643 | } |
duke@435 | 644 | |
duke@435 | 645 | |
duke@435 | 646 | void Assembler::prefix(Prefix p) { |
duke@435 | 647 | a_byte(p); |
duke@435 | 648 | } |
duke@435 | 649 | |
duke@435 | 650 | |
duke@435 | 651 | void Assembler::movb(Register dst, Address src) { |
duke@435 | 652 | assert(dst->has_byte_register(), "must have byte register"); |
duke@435 | 653 | InstructionMark im(this); |
duke@435 | 654 | emit_byte(0x8A); |
duke@435 | 655 | emit_operand(dst, src); |
duke@435 | 656 | } |
duke@435 | 657 | |
duke@435 | 658 | |
duke@435 | 659 | void Assembler::movb(Address dst, int imm8) { |
duke@435 | 660 | InstructionMark im(this); |
duke@435 | 661 | emit_byte(0xC6); |
duke@435 | 662 | emit_operand(rax, dst); |
duke@435 | 663 | emit_byte(imm8); |
duke@435 | 664 | } |
duke@435 | 665 | |
duke@435 | 666 | |
duke@435 | 667 | void Assembler::movb(Address dst, Register src) { |
duke@435 | 668 | assert(src->has_byte_register(), "must have byte register"); |
duke@435 | 669 | InstructionMark im(this); |
duke@435 | 670 | emit_byte(0x88); |
duke@435 | 671 | emit_operand(src, dst); |
duke@435 | 672 | } |
duke@435 | 673 | |
duke@435 | 674 | |
duke@435 | 675 | void Assembler::movw(Address dst, int imm16) { |
duke@435 | 676 | InstructionMark im(this); |
duke@435 | 677 | |
duke@435 | 678 | emit_byte(0x66); // switch to 16-bit mode |
duke@435 | 679 | emit_byte(0xC7); |
duke@435 | 680 | emit_operand(rax, dst); |
duke@435 | 681 | emit_word(imm16); |
duke@435 | 682 | } |
duke@435 | 683 | |
duke@435 | 684 | |
duke@435 | 685 | void Assembler::movw(Register dst, Address src) { |
duke@435 | 686 | InstructionMark im(this); |
duke@435 | 687 | emit_byte(0x66); |
duke@435 | 688 | emit_byte(0x8B); |
duke@435 | 689 | emit_operand(dst, src); |
duke@435 | 690 | } |
duke@435 | 691 | |
duke@435 | 692 | |
duke@435 | 693 | void Assembler::movw(Address dst, Register src) { |
duke@435 | 694 | InstructionMark im(this); |
duke@435 | 695 | emit_byte(0x66); |
duke@435 | 696 | emit_byte(0x89); |
duke@435 | 697 | emit_operand(src, dst); |
duke@435 | 698 | } |
duke@435 | 699 | |
duke@435 | 700 | |
duke@435 | 701 | void Assembler::movl(Register dst, int imm32) { |
duke@435 | 702 | emit_byte(0xB8 | dst->encoding()); |
duke@435 | 703 | emit_long(imm32); |
duke@435 | 704 | } |
duke@435 | 705 | |
duke@435 | 706 | #ifndef _LP64 |
duke@435 | 707 | void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
duke@435 | 708 | |
duke@435 | 709 | InstructionMark im(this); |
duke@435 | 710 | emit_byte(0xB8 | dst->encoding()); |
duke@435 | 711 | emit_data((int)imm32, rspec, 0); |
duke@435 | 712 | } |
duke@435 | 713 | #endif // _LP64 |
duke@435 | 714 | |
duke@435 | 715 | void Assembler::movl(Register dst, Register src) { |
duke@435 | 716 | emit_byte(0x8B); |
duke@435 | 717 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 718 | } |
duke@435 | 719 | |
duke@435 | 720 | |
duke@435 | 721 | void Assembler::movl(Register dst, Address src) { |
duke@435 | 722 | InstructionMark im(this); |
duke@435 | 723 | emit_byte(0x8B); |
duke@435 | 724 | emit_operand(dst, src); |
duke@435 | 725 | } |
duke@435 | 726 | |
duke@435 | 727 | |
duke@435 | 728 | void Assembler::movl(Address dst, int imm32) { |
duke@435 | 729 | InstructionMark im(this); |
duke@435 | 730 | emit_byte(0xC7); |
duke@435 | 731 | emit_operand(rax, dst); |
duke@435 | 732 | emit_long(imm32); |
duke@435 | 733 | } |
duke@435 | 734 | |
duke@435 | 735 | #ifndef _LP64 |
duke@435 | 736 | void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
duke@435 | 737 | InstructionMark im(this); |
duke@435 | 738 | emit_byte(0xC7); |
duke@435 | 739 | emit_operand(rax, dst); |
duke@435 | 740 | emit_data((int)imm32, rspec, 0); |
duke@435 | 741 | } |
duke@435 | 742 | #endif // _LP64 |
duke@435 | 743 | |
duke@435 | 744 | void Assembler::movl(Address dst, Register src) { |
duke@435 | 745 | InstructionMark im(this); |
duke@435 | 746 | emit_byte(0x89); |
duke@435 | 747 | emit_operand(src, dst); |
duke@435 | 748 | } |
duke@435 | 749 | |
duke@435 | 750 | void Assembler::movsxb(Register dst, Address src) { |
duke@435 | 751 | InstructionMark im(this); |
duke@435 | 752 | emit_byte(0x0F); |
duke@435 | 753 | emit_byte(0xBE); |
duke@435 | 754 | emit_operand(dst, src); |
duke@435 | 755 | } |
duke@435 | 756 | |
duke@435 | 757 | void Assembler::movsxb(Register dst, Register src) { |
duke@435 | 758 | assert(src->has_byte_register(), "must have byte register"); |
duke@435 | 759 | emit_byte(0x0F); |
duke@435 | 760 | emit_byte(0xBE); |
duke@435 | 761 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 762 | } |
duke@435 | 763 | |
duke@435 | 764 | |
duke@435 | 765 | void Assembler::movsxw(Register dst, Address src) { |
duke@435 | 766 | InstructionMark im(this); |
duke@435 | 767 | emit_byte(0x0F); |
duke@435 | 768 | emit_byte(0xBF); |
duke@435 | 769 | emit_operand(dst, src); |
duke@435 | 770 | } |
duke@435 | 771 | |
duke@435 | 772 | |
duke@435 | 773 | void Assembler::movsxw(Register dst, Register src) { |
duke@435 | 774 | emit_byte(0x0F); |
duke@435 | 775 | emit_byte(0xBF); |
duke@435 | 776 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 777 | } |
duke@435 | 778 | |
duke@435 | 779 | |
duke@435 | 780 | void Assembler::movzxb(Register dst, Address src) { |
duke@435 | 781 | InstructionMark im(this); |
duke@435 | 782 | emit_byte(0x0F); |
duke@435 | 783 | emit_byte(0xB6); |
duke@435 | 784 | emit_operand(dst, src); |
duke@435 | 785 | } |
duke@435 | 786 | |
duke@435 | 787 | |
duke@435 | 788 | void Assembler::movzxb(Register dst, Register src) { |
duke@435 | 789 | assert(src->has_byte_register(), "must have byte register"); |
duke@435 | 790 | emit_byte(0x0F); |
duke@435 | 791 | emit_byte(0xB6); |
duke@435 | 792 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 793 | } |
duke@435 | 794 | |
duke@435 | 795 | |
duke@435 | 796 | void Assembler::movzxw(Register dst, Address src) { |
duke@435 | 797 | InstructionMark im(this); |
duke@435 | 798 | emit_byte(0x0F); |
duke@435 | 799 | emit_byte(0xB7); |
duke@435 | 800 | emit_operand(dst, src); |
duke@435 | 801 | } |
duke@435 | 802 | |
duke@435 | 803 | |
duke@435 | 804 | void Assembler::movzxw(Register dst, Register src) { |
duke@435 | 805 | emit_byte(0x0F); |
duke@435 | 806 | emit_byte(0xB7); |
duke@435 | 807 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 808 | } |
duke@435 | 809 | |
duke@435 | 810 | |
duke@435 | 811 | void Assembler::cmovl(Condition cc, Register dst, Register src) { |
duke@435 | 812 | guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
duke@435 | 813 | emit_byte(0x0F); |
duke@435 | 814 | emit_byte(0x40 | cc); |
duke@435 | 815 | emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding()); |
duke@435 | 816 | } |
duke@435 | 817 | |
duke@435 | 818 | |
duke@435 | 819 | void Assembler::cmovl(Condition cc, Register dst, Address src) { |
duke@435 | 820 | guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
duke@435 | 821 | // The code below seems to be wrong - however the manual is inconclusive |
duke@435 | 822 | // do not use for now (remember to enable all callers when fixing this) |
duke@435 | 823 | Unimplemented(); |
duke@435 | 824 | // wrong bytes? |
duke@435 | 825 | InstructionMark im(this); |
duke@435 | 826 | emit_byte(0x0F); |
duke@435 | 827 | emit_byte(0x40 | cc); |
duke@435 | 828 | emit_operand(dst, src); |
duke@435 | 829 | } |
duke@435 | 830 | |
duke@435 | 831 | |
duke@435 | 832 | void Assembler::prefetcht0(Address src) { |
duke@435 | 833 | assert(VM_Version::supports_sse(), "must support"); |
duke@435 | 834 | InstructionMark im(this); |
duke@435 | 835 | emit_byte(0x0F); |
duke@435 | 836 | emit_byte(0x18); |
duke@435 | 837 | emit_operand(rcx, src); // 1, src |
duke@435 | 838 | } |
duke@435 | 839 | |
duke@435 | 840 | |
duke@435 | 841 | void Assembler::prefetcht1(Address src) { |
duke@435 | 842 | assert(VM_Version::supports_sse(), "must support"); |
duke@435 | 843 | InstructionMark im(this); |
duke@435 | 844 | emit_byte(0x0F); |
duke@435 | 845 | emit_byte(0x18); |
duke@435 | 846 | emit_operand(rdx, src); // 2, src |
duke@435 | 847 | } |
duke@435 | 848 | |
duke@435 | 849 | |
duke@435 | 850 | void Assembler::prefetcht2(Address src) { |
duke@435 | 851 | assert(VM_Version::supports_sse(), "must support"); |
duke@435 | 852 | InstructionMark im(this); |
duke@435 | 853 | emit_byte(0x0F); |
duke@435 | 854 | emit_byte(0x18); |
duke@435 | 855 | emit_operand(rbx, src); // 3, src |
duke@435 | 856 | } |
duke@435 | 857 | |
duke@435 | 858 | |
duke@435 | 859 | void Assembler::prefetchnta(Address src) { |
duke@435 | 860 | assert(VM_Version::supports_sse2(), "must support"); |
duke@435 | 861 | InstructionMark im(this); |
duke@435 | 862 | emit_byte(0x0F); |
duke@435 | 863 | emit_byte(0x18); |
duke@435 | 864 | emit_operand(rax, src); // 0, src |
duke@435 | 865 | } |
duke@435 | 866 | |
duke@435 | 867 | |
duke@435 | 868 | void Assembler::prefetchw(Address src) { |
duke@435 | 869 | assert(VM_Version::supports_3dnow(), "must support"); |
duke@435 | 870 | InstructionMark im(this); |
duke@435 | 871 | emit_byte(0x0F); |
duke@435 | 872 | emit_byte(0x0D); |
duke@435 | 873 | emit_operand(rcx, src); // 1, src |
duke@435 | 874 | } |
duke@435 | 875 | |
duke@435 | 876 | |
duke@435 | 877 | void Assembler::prefetchr(Address src) { |
duke@435 | 878 | assert(VM_Version::supports_3dnow(), "must support"); |
duke@435 | 879 | InstructionMark im(this); |
duke@435 | 880 | emit_byte(0x0F); |
duke@435 | 881 | emit_byte(0x0D); |
duke@435 | 882 | emit_operand(rax, src); // 0, src |
duke@435 | 883 | } |
duke@435 | 884 | |
duke@435 | 885 | |
duke@435 | 886 | void Assembler::adcl(Register dst, int imm32) { |
duke@435 | 887 | emit_arith(0x81, 0xD0, dst, imm32); |
duke@435 | 888 | } |
duke@435 | 889 | |
duke@435 | 890 | |
duke@435 | 891 | void Assembler::adcl(Register dst, Address src) { |
duke@435 | 892 | InstructionMark im(this); |
duke@435 | 893 | emit_byte(0x13); |
duke@435 | 894 | emit_operand(dst, src); |
duke@435 | 895 | } |
duke@435 | 896 | |
duke@435 | 897 | |
duke@435 | 898 | void Assembler::adcl(Register dst, Register src) { |
duke@435 | 899 | emit_arith(0x13, 0xC0, dst, src); |
duke@435 | 900 | } |
duke@435 | 901 | |
duke@435 | 902 | |
duke@435 | 903 | void Assembler::addl(Address dst, int imm32) { |
duke@435 | 904 | InstructionMark im(this); |
duke@435 | 905 | emit_arith_operand(0x81,rax,dst,imm32); |
duke@435 | 906 | } |
duke@435 | 907 | |
duke@435 | 908 | |
duke@435 | 909 | void Assembler::addl(Address dst, Register src) { |
duke@435 | 910 | InstructionMark im(this); |
duke@435 | 911 | emit_byte(0x01); |
duke@435 | 912 | emit_operand(src, dst); |
duke@435 | 913 | } |
duke@435 | 914 | |
duke@435 | 915 | |
duke@435 | 916 | void Assembler::addl(Register dst, int imm32) { |
duke@435 | 917 | emit_arith(0x81, 0xC0, dst, imm32); |
duke@435 | 918 | } |
duke@435 | 919 | |
duke@435 | 920 | |
duke@435 | 921 | void Assembler::addl(Register dst, Address src) { |
duke@435 | 922 | InstructionMark im(this); |
duke@435 | 923 | emit_byte(0x03); |
duke@435 | 924 | emit_operand(dst, src); |
duke@435 | 925 | } |
duke@435 | 926 | |
duke@435 | 927 | |
duke@435 | 928 | void Assembler::addl(Register dst, Register src) { |
duke@435 | 929 | emit_arith(0x03, 0xC0, dst, src); |
duke@435 | 930 | } |
duke@435 | 931 | |
duke@435 | 932 | |
duke@435 | 933 | void Assembler::andl(Register dst, int imm32) { |
duke@435 | 934 | emit_arith(0x81, 0xE0, dst, imm32); |
duke@435 | 935 | } |
duke@435 | 936 | |
duke@435 | 937 | |
duke@435 | 938 | void Assembler::andl(Register dst, Address src) { |
duke@435 | 939 | InstructionMark im(this); |
duke@435 | 940 | emit_byte(0x23); |
duke@435 | 941 | emit_operand(dst, src); |
duke@435 | 942 | } |
duke@435 | 943 | |
duke@435 | 944 | |
duke@435 | 945 | void Assembler::andl(Register dst, Register src) { |
duke@435 | 946 | emit_arith(0x23, 0xC0, dst, src); |
duke@435 | 947 | } |
duke@435 | 948 | |
duke@435 | 949 | |
duke@435 | 950 | void Assembler::cmpb(Address dst, int imm8) { |
duke@435 | 951 | InstructionMark im(this); |
duke@435 | 952 | emit_byte(0x80); |
duke@435 | 953 | emit_operand(rdi, dst); |
duke@435 | 954 | emit_byte(imm8); |
duke@435 | 955 | } |
duke@435 | 956 | |
duke@435 | 957 | void Assembler::cmpw(Address dst, int imm16) { |
duke@435 | 958 | InstructionMark im(this); |
duke@435 | 959 | emit_byte(0x66); |
duke@435 | 960 | emit_byte(0x81); |
duke@435 | 961 | emit_operand(rdi, dst); |
duke@435 | 962 | emit_word(imm16); |
duke@435 | 963 | } |
duke@435 | 964 | |
duke@435 | 965 | void Assembler::cmpl(Address dst, int imm32) { |
duke@435 | 966 | InstructionMark im(this); |
duke@435 | 967 | emit_byte(0x81); |
duke@435 | 968 | emit_operand(rdi, dst); |
duke@435 | 969 | emit_long(imm32); |
duke@435 | 970 | } |
duke@435 | 971 | |
duke@435 | 972 | #ifndef _LP64 |
duke@435 | 973 | void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
duke@435 | 974 | InstructionMark im(this); |
duke@435 | 975 | emit_byte(0x81); |
duke@435 | 976 | emit_byte(0xF8 | src1->encoding()); |
duke@435 | 977 | emit_data(imm32, rspec, 0); |
duke@435 | 978 | } |
duke@435 | 979 | |
duke@435 | 980 | void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
duke@435 | 981 | InstructionMark im(this); |
duke@435 | 982 | emit_byte(0x81); |
duke@435 | 983 | emit_operand(rdi, src1); |
duke@435 | 984 | emit_data(imm32, rspec, 0); |
duke@435 | 985 | } |
duke@435 | 986 | #endif // _LP64 |
duke@435 | 987 | |
duke@435 | 988 | |
duke@435 | 989 | void Assembler::cmpl(Register dst, int imm32) { |
duke@435 | 990 | emit_arith(0x81, 0xF8, dst, imm32); |
duke@435 | 991 | } |
duke@435 | 992 | |
duke@435 | 993 | |
duke@435 | 994 | void Assembler::cmpl(Register dst, Register src) { |
duke@435 | 995 | emit_arith(0x3B, 0xC0, dst, src); |
duke@435 | 996 | } |
duke@435 | 997 | |
duke@435 | 998 | |
duke@435 | 999 | void Assembler::cmpl(Register dst, Address src) { |
duke@435 | 1000 | InstructionMark im(this); |
duke@435 | 1001 | emit_byte(0x3B); |
duke@435 | 1002 | emit_operand(dst, src); |
duke@435 | 1003 | } |
duke@435 | 1004 | |
duke@435 | 1005 | |
duke@435 | 1006 | void Assembler::decl(Register dst) { |
duke@435 | 1007 | // Don't use it directly. Use MacroAssembler::decrement() instead. |
duke@435 | 1008 | emit_byte(0x48 | dst->encoding()); |
duke@435 | 1009 | } |
duke@435 | 1010 | |
duke@435 | 1011 | |
duke@435 | 1012 | void Assembler::decl(Address dst) { |
duke@435 | 1013 | // Don't use it directly. Use MacroAssembler::decrement() instead. |
duke@435 | 1014 | InstructionMark im(this); |
duke@435 | 1015 | emit_byte(0xFF); |
duke@435 | 1016 | emit_operand(rcx, dst); |
duke@435 | 1017 | } |
duke@435 | 1018 | |
duke@435 | 1019 | |
duke@435 | 1020 | void Assembler::idivl(Register src) { |
duke@435 | 1021 | emit_byte(0xF7); |
duke@435 | 1022 | emit_byte(0xF8 | src->encoding()); |
duke@435 | 1023 | } |
duke@435 | 1024 | |
duke@435 | 1025 | |
duke@435 | 1026 | void Assembler::cdql() { |
duke@435 | 1027 | emit_byte(0x99); |
duke@435 | 1028 | } |
duke@435 | 1029 | |
duke@435 | 1030 | |
duke@435 | 1031 | void Assembler::imull(Register dst, Register src) { |
duke@435 | 1032 | emit_byte(0x0F); |
duke@435 | 1033 | emit_byte(0xAF); |
duke@435 | 1034 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 1035 | } |
duke@435 | 1036 | |
duke@435 | 1037 | |
duke@435 | 1038 | void Assembler::imull(Register dst, Register src, int value) { |
duke@435 | 1039 | if (is8bit(value)) { |
duke@435 | 1040 | emit_byte(0x6B); |
duke@435 | 1041 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 1042 | emit_byte(value); |
duke@435 | 1043 | } else { |
duke@435 | 1044 | emit_byte(0x69); |
duke@435 | 1045 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 1046 | emit_long(value); |
duke@435 | 1047 | } |
duke@435 | 1048 | } |
duke@435 | 1049 | |
duke@435 | 1050 | |
duke@435 | 1051 | void Assembler::incl(Register dst) { |
duke@435 | 1052 | // Don't use it directly. Use MacroAssembler::increment() instead. |
duke@435 | 1053 | emit_byte(0x40 | dst->encoding()); |
duke@435 | 1054 | } |
duke@435 | 1055 | |
duke@435 | 1056 | |
duke@435 | 1057 | void Assembler::incl(Address dst) { |
duke@435 | 1058 | // Don't use it directly. Use MacroAssembler::increment() instead. |
duke@435 | 1059 | InstructionMark im(this); |
duke@435 | 1060 | emit_byte(0xFF); |
duke@435 | 1061 | emit_operand(rax, dst); |
duke@435 | 1062 | } |
duke@435 | 1063 | |
duke@435 | 1064 | |
duke@435 | 1065 | void Assembler::leal(Register dst, Address src) { |
duke@435 | 1066 | InstructionMark im(this); |
duke@435 | 1067 | emit_byte(0x8D); |
duke@435 | 1068 | emit_operand(dst, src); |
duke@435 | 1069 | } |
duke@435 | 1070 | |
duke@435 | 1071 | void Assembler::mull(Address src) { |
duke@435 | 1072 | InstructionMark im(this); |
duke@435 | 1073 | emit_byte(0xF7); |
duke@435 | 1074 | emit_operand(rsp, src); |
duke@435 | 1075 | } |
duke@435 | 1076 | |
duke@435 | 1077 | |
duke@435 | 1078 | void Assembler::mull(Register src) { |
duke@435 | 1079 | emit_byte(0xF7); |
duke@435 | 1080 | emit_byte(0xE0 | src->encoding()); |
duke@435 | 1081 | } |
duke@435 | 1082 | |
duke@435 | 1083 | |
duke@435 | 1084 | void Assembler::negl(Register dst) { |
duke@435 | 1085 | emit_byte(0xF7); |
duke@435 | 1086 | emit_byte(0xD8 | dst->encoding()); |
duke@435 | 1087 | } |
duke@435 | 1088 | |
duke@435 | 1089 | |
duke@435 | 1090 | void Assembler::notl(Register dst) { |
duke@435 | 1091 | emit_byte(0xF7); |
duke@435 | 1092 | emit_byte(0xD0 | dst->encoding()); |
duke@435 | 1093 | } |
duke@435 | 1094 | |
duke@435 | 1095 | |
duke@435 | 1096 | void Assembler::orl(Address dst, int imm32) { |
duke@435 | 1097 | InstructionMark im(this); |
duke@435 | 1098 | emit_byte(0x81); |
duke@435 | 1099 | emit_operand(rcx, dst); |
duke@435 | 1100 | emit_long(imm32); |
duke@435 | 1101 | } |
duke@435 | 1102 | |
duke@435 | 1103 | void Assembler::orl(Register dst, int imm32) { |
duke@435 | 1104 | emit_arith(0x81, 0xC8, dst, imm32); |
duke@435 | 1105 | } |
duke@435 | 1106 | |
duke@435 | 1107 | |
duke@435 | 1108 | void Assembler::orl(Register dst, Address src) { |
duke@435 | 1109 | InstructionMark im(this); |
duke@435 | 1110 | emit_byte(0x0B); |
duke@435 | 1111 | emit_operand(dst, src); |
duke@435 | 1112 | } |
duke@435 | 1113 | |
duke@435 | 1114 | |
duke@435 | 1115 | void Assembler::orl(Register dst, Register src) { |
duke@435 | 1116 | emit_arith(0x0B, 0xC0, dst, src); |
duke@435 | 1117 | } |
duke@435 | 1118 | |
duke@435 | 1119 | |
duke@435 | 1120 | void Assembler::rcll(Register dst, int imm8) { |
duke@435 | 1121 | assert(isShiftCount(imm8), "illegal shift count"); |
duke@435 | 1122 | if (imm8 == 1) { |
duke@435 | 1123 | emit_byte(0xD1); |
duke@435 | 1124 | emit_byte(0xD0 | dst->encoding()); |
duke@435 | 1125 | } else { |
duke@435 | 1126 | emit_byte(0xC1); |
duke@435 | 1127 | emit_byte(0xD0 | dst->encoding()); |
duke@435 | 1128 | emit_byte(imm8); |
duke@435 | 1129 | } |
duke@435 | 1130 | } |
duke@435 | 1131 | |
duke@435 | 1132 | |
duke@435 | 1133 | void Assembler::sarl(Register dst, int imm8) { |
duke@435 | 1134 | assert(isShiftCount(imm8), "illegal shift count"); |
duke@435 | 1135 | if (imm8 == 1) { |
duke@435 | 1136 | emit_byte(0xD1); |
duke@435 | 1137 | emit_byte(0xF8 | dst->encoding()); |
duke@435 | 1138 | } else { |
duke@435 | 1139 | emit_byte(0xC1); |
duke@435 | 1140 | emit_byte(0xF8 | dst->encoding()); |
duke@435 | 1141 | emit_byte(imm8); |
duke@435 | 1142 | } |
duke@435 | 1143 | } |
duke@435 | 1144 | |
duke@435 | 1145 | |
duke@435 | 1146 | void Assembler::sarl(Register dst) { |
duke@435 | 1147 | emit_byte(0xD3); |
duke@435 | 1148 | emit_byte(0xF8 | dst->encoding()); |
duke@435 | 1149 | } |
duke@435 | 1150 | |
duke@435 | 1151 | |
duke@435 | 1152 | void Assembler::sbbl(Address dst, int imm32) { |
duke@435 | 1153 | InstructionMark im(this); |
duke@435 | 1154 | emit_arith_operand(0x81,rbx,dst,imm32); |
duke@435 | 1155 | } |
duke@435 | 1156 | |
duke@435 | 1157 | |
duke@435 | 1158 | void Assembler::sbbl(Register dst, int imm32) { |
duke@435 | 1159 | emit_arith(0x81, 0xD8, dst, imm32); |
duke@435 | 1160 | } |
duke@435 | 1161 | |
duke@435 | 1162 | |
duke@435 | 1163 | void Assembler::sbbl(Register dst, Address src) { |
duke@435 | 1164 | InstructionMark im(this); |
duke@435 | 1165 | emit_byte(0x1B); |
duke@435 | 1166 | emit_operand(dst, src); |
duke@435 | 1167 | } |
duke@435 | 1168 | |
duke@435 | 1169 | |
duke@435 | 1170 | void Assembler::sbbl(Register dst, Register src) { |
duke@435 | 1171 | emit_arith(0x1B, 0xC0, dst, src); |
duke@435 | 1172 | } |
duke@435 | 1173 | |
duke@435 | 1174 | |
duke@435 | 1175 | void Assembler::shldl(Register dst, Register src) { |
duke@435 | 1176 | emit_byte(0x0F); |
duke@435 | 1177 | emit_byte(0xA5); |
duke@435 | 1178 | emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); |
duke@435 | 1179 | } |
duke@435 | 1180 | |
duke@435 | 1181 | |
duke@435 | 1182 | void Assembler::shll(Register dst, int imm8) { |
duke@435 | 1183 | assert(isShiftCount(imm8), "illegal shift count"); |
duke@435 | 1184 | if (imm8 == 1 ) { |
duke@435 | 1185 | emit_byte(0xD1); |
duke@435 | 1186 | emit_byte(0xE0 | dst->encoding()); |
duke@435 | 1187 | } else { |
duke@435 | 1188 | emit_byte(0xC1); |
duke@435 | 1189 | emit_byte(0xE0 | dst->encoding()); |
duke@435 | 1190 | emit_byte(imm8); |
duke@435 | 1191 | } |
duke@435 | 1192 | } |
duke@435 | 1193 | |
duke@435 | 1194 | |
duke@435 | 1195 | void Assembler::shll(Register dst) { |
duke@435 | 1196 | emit_byte(0xD3); |
duke@435 | 1197 | emit_byte(0xE0 | dst->encoding()); |
duke@435 | 1198 | } |
duke@435 | 1199 | |
duke@435 | 1200 | |
duke@435 | 1201 | void Assembler::shrdl(Register dst, Register src) { |
duke@435 | 1202 | emit_byte(0x0F); |
duke@435 | 1203 | emit_byte(0xAD); |
duke@435 | 1204 | emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); |
duke@435 | 1205 | } |
duke@435 | 1206 | |
duke@435 | 1207 | |
duke@435 | 1208 | void Assembler::shrl(Register dst, int imm8) { |
duke@435 | 1209 | assert(isShiftCount(imm8), "illegal shift count"); |
duke@435 | 1210 | emit_byte(0xC1); |
duke@435 | 1211 | emit_byte(0xE8 | dst->encoding()); |
duke@435 | 1212 | emit_byte(imm8); |
duke@435 | 1213 | } |
duke@435 | 1214 | |
duke@435 | 1215 | |
duke@435 | 1216 | void Assembler::shrl(Register dst) { |
duke@435 | 1217 | emit_byte(0xD3); |
duke@435 | 1218 | emit_byte(0xE8 | dst->encoding()); |
duke@435 | 1219 | } |
duke@435 | 1220 | |
duke@435 | 1221 | |
duke@435 | 1222 | void Assembler::subl(Address dst, int imm32) { |
duke@435 | 1223 | if (is8bit(imm32)) { |
duke@435 | 1224 | InstructionMark im(this); |
duke@435 | 1225 | emit_byte(0x83); |
duke@435 | 1226 | emit_operand(rbp, dst); |
duke@435 | 1227 | emit_byte(imm32 & 0xFF); |
duke@435 | 1228 | } else { |
duke@435 | 1229 | InstructionMark im(this); |
duke@435 | 1230 | emit_byte(0x81); |
duke@435 | 1231 | emit_operand(rbp, dst); |
duke@435 | 1232 | emit_long(imm32); |
duke@435 | 1233 | } |
duke@435 | 1234 | } |
duke@435 | 1235 | |
duke@435 | 1236 | |
duke@435 | 1237 | void Assembler::subl(Register dst, int imm32) { |
duke@435 | 1238 | emit_arith(0x81, 0xE8, dst, imm32); |
duke@435 | 1239 | } |
duke@435 | 1240 | |
duke@435 | 1241 | |
duke@435 | 1242 | void Assembler::subl(Address dst, Register src) { |
duke@435 | 1243 | InstructionMark im(this); |
duke@435 | 1244 | emit_byte(0x29); |
duke@435 | 1245 | emit_operand(src, dst); |
duke@435 | 1246 | } |
duke@435 | 1247 | |
duke@435 | 1248 | |
duke@435 | 1249 | void Assembler::subl(Register dst, Address src) { |
duke@435 | 1250 | InstructionMark im(this); |
duke@435 | 1251 | emit_byte(0x2B); |
duke@435 | 1252 | emit_operand(dst, src); |
duke@435 | 1253 | } |
duke@435 | 1254 | |
duke@435 | 1255 | |
duke@435 | 1256 | void Assembler::subl(Register dst, Register src) { |
duke@435 | 1257 | emit_arith(0x2B, 0xC0, dst, src); |
duke@435 | 1258 | } |
duke@435 | 1259 | |
duke@435 | 1260 | |
duke@435 | 1261 | void Assembler::testb(Register dst, int imm8) { |
duke@435 | 1262 | assert(dst->has_byte_register(), "must have byte register"); |
duke@435 | 1263 | emit_arith_b(0xF6, 0xC0, dst, imm8); |
duke@435 | 1264 | } |
duke@435 | 1265 | |
duke@435 | 1266 | |
duke@435 | 1267 | void Assembler::testl(Register dst, int imm32) { |
duke@435 | 1268 | // not using emit_arith because test |
duke@435 | 1269 | // doesn't support sign-extension of |
duke@435 | 1270 | // 8bit operands |
duke@435 | 1271 | if (dst->encoding() == 0) { |
duke@435 | 1272 | emit_byte(0xA9); |
duke@435 | 1273 | } else { |
duke@435 | 1274 | emit_byte(0xF7); |
duke@435 | 1275 | emit_byte(0xC0 | dst->encoding()); |
duke@435 | 1276 | } |
duke@435 | 1277 | emit_long(imm32); |
duke@435 | 1278 | } |
duke@435 | 1279 | |
duke@435 | 1280 | |
duke@435 | 1281 | void Assembler::testl(Register dst, Register src) { |
duke@435 | 1282 | emit_arith(0x85, 0xC0, dst, src); |
duke@435 | 1283 | } |
duke@435 | 1284 | |
duke@435 | 1285 | void Assembler::testl(Register dst, Address src) { |
duke@435 | 1286 | InstructionMark im(this); |
duke@435 | 1287 | emit_byte(0x85); |
duke@435 | 1288 | emit_operand(dst, src); |
duke@435 | 1289 | } |
duke@435 | 1290 | |
duke@435 | 1291 | void Assembler::xaddl(Address dst, Register src) { |
duke@435 | 1292 | InstructionMark im(this); |
duke@435 | 1293 | emit_byte(0x0F); |
duke@435 | 1294 | emit_byte(0xC1); |
duke@435 | 1295 | emit_operand(src, dst); |
duke@435 | 1296 | } |
duke@435 | 1297 | |
duke@435 | 1298 | void Assembler::xorl(Register dst, int imm32) { |
duke@435 | 1299 | emit_arith(0x81, 0xF0, dst, imm32); |
duke@435 | 1300 | } |
duke@435 | 1301 | |
duke@435 | 1302 | |
duke@435 | 1303 | void Assembler::xorl(Register dst, Address src) { |
duke@435 | 1304 | InstructionMark im(this); |
duke@435 | 1305 | emit_byte(0x33); |
duke@435 | 1306 | emit_operand(dst, src); |
duke@435 | 1307 | } |
duke@435 | 1308 | |
duke@435 | 1309 | |
duke@435 | 1310 | void Assembler::xorl(Register dst, Register src) { |
duke@435 | 1311 | emit_arith(0x33, 0xC0, dst, src); |
duke@435 | 1312 | } |
duke@435 | 1313 | |
duke@435 | 1314 | |
duke@435 | 1315 | void Assembler::bswap(Register reg) { |
duke@435 | 1316 | emit_byte(0x0F); |
duke@435 | 1317 | emit_byte(0xC8 | reg->encoding()); |
duke@435 | 1318 | } |
duke@435 | 1319 | |
duke@435 | 1320 | |
duke@435 | 1321 | void Assembler::lock() { |
duke@435 | 1322 | if (Atomics & 1) { |
duke@435 | 1323 | // Emit either nothing, a NOP, or a NOP: prefix |
duke@435 | 1324 | emit_byte(0x90) ; |
duke@435 | 1325 | } else { |
duke@435 | 1326 | emit_byte(0xF0); |
duke@435 | 1327 | } |
duke@435 | 1328 | } |
duke@435 | 1329 | |
duke@435 | 1330 | |
duke@435 | 1331 | void Assembler::xchg(Register reg, Address adr) { |
duke@435 | 1332 | InstructionMark im(this); |
duke@435 | 1333 | emit_byte(0x87); |
duke@435 | 1334 | emit_operand(reg, adr); |
duke@435 | 1335 | } |
duke@435 | 1336 | |
duke@435 | 1337 | |
duke@435 | 1338 | void Assembler::xchgl(Register dst, Register src) { |
duke@435 | 1339 | emit_byte(0x87); |
duke@435 | 1340 | emit_byte(0xc0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 1341 | } |
duke@435 | 1342 | |
duke@435 | 1343 | |
duke@435 | 1344 | // The 32-bit cmpxchg compares the value at adr with the contents of rax, |
duke@435 | 1345 | // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. |
duke@435 | 1346 | // The ZF is set if the compared values were equal, and cleared otherwise. |
duke@435 | 1347 | void Assembler::cmpxchg(Register reg, Address adr) { |
duke@435 | 1348 | if (Atomics & 2) { |
duke@435 | 1349 | // caveat: no instructionmark, so this isn't relocatable. |
duke@435 | 1350 | // Emit a synthetic, non-atomic, CAS equivalent. |
duke@435 | 1351 | // Beware. The synthetic form sets all ICCs, not just ZF. |
duke@435 | 1352 | // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) |
duke@435 | 1353 | cmpl (rax, adr) ; |
duke@435 | 1354 | movl (rax, adr) ; |
duke@435 | 1355 | if (reg != rax) { |
duke@435 | 1356 | Label L ; |
duke@435 | 1357 | jcc (Assembler::notEqual, L) ; |
duke@435 | 1358 | movl (adr, reg) ; |
duke@435 | 1359 | bind (L) ; |
duke@435 | 1360 | } |
duke@435 | 1361 | } else { |
duke@435 | 1362 | InstructionMark im(this); |
duke@435 | 1363 | emit_byte(0x0F); |
duke@435 | 1364 | emit_byte(0xB1); |
duke@435 | 1365 | emit_operand(reg, adr); |
duke@435 | 1366 | } |
duke@435 | 1367 | } |
duke@435 | 1368 | |
duke@435 | 1369 | // The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax, |
duke@435 | 1370 | // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded |
duke@435 | 1371 | // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. |
duke@435 | 1372 | void Assembler::cmpxchg8(Address adr) { |
duke@435 | 1373 | InstructionMark im(this); |
duke@435 | 1374 | emit_byte(0x0F); |
duke@435 | 1375 | emit_byte(0xc7); |
duke@435 | 1376 | emit_operand(rcx, adr); |
duke@435 | 1377 | } |
duke@435 | 1378 | |
duke@435 | 1379 | void Assembler::hlt() { |
duke@435 | 1380 | emit_byte(0xF4); |
duke@435 | 1381 | } |
duke@435 | 1382 | |
duke@435 | 1383 | |
duke@435 | 1384 | void Assembler::addr_nop_4() { |
duke@435 | 1385 | // 4 bytes: NOP DWORD PTR [EAX+0] |
duke@435 | 1386 | emit_byte(0x0F); |
duke@435 | 1387 | emit_byte(0x1F); |
duke@435 | 1388 | emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
duke@435 | 1389 | emit_byte(0); // 8-bits offset (1 byte) |
duke@435 | 1390 | } |
duke@435 | 1391 | |
duke@435 | 1392 | void Assembler::addr_nop_5() { |
duke@435 | 1393 | // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
duke@435 | 1394 | emit_byte(0x0F); |
duke@435 | 1395 | emit_byte(0x1F); |
duke@435 | 1396 | emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
duke@435 | 1397 | emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
duke@435 | 1398 | emit_byte(0); // 8-bits offset (1 byte) |
duke@435 | 1399 | } |
duke@435 | 1400 | |
duke@435 | 1401 | void Assembler::addr_nop_7() { |
duke@435 | 1402 | // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
duke@435 | 1403 | emit_byte(0x0F); |
duke@435 | 1404 | emit_byte(0x1F); |
duke@435 | 1405 | emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
duke@435 | 1406 | emit_long(0); // 32-bits offset (4 bytes) |
duke@435 | 1407 | } |
duke@435 | 1408 | |
duke@435 | 1409 | void Assembler::addr_nop_8() { |
duke@435 | 1410 | // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
duke@435 | 1411 | emit_byte(0x0F); |
duke@435 | 1412 | emit_byte(0x1F); |
duke@435 | 1413 | emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
duke@435 | 1414 | emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
duke@435 | 1415 | emit_long(0); // 32-bits offset (4 bytes) |
duke@435 | 1416 | } |
duke@435 | 1417 | |
duke@435 | 1418 | void Assembler::nop(int i) { |
duke@435 | 1419 | assert(i > 0, " "); |
duke@435 | 1420 | if (UseAddressNop && VM_Version::is_intel()) { |
duke@435 | 1421 | // |
duke@435 | 1422 | // Using multi-bytes nops "0x0F 0x1F [address]" for Intel |
duke@435 | 1423 | // 1: 0x90 |
duke@435 | 1424 | // 2: 0x66 0x90 |
duke@435 | 1425 | // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) |
duke@435 | 1426 | // 4: 0x0F 0x1F 0x40 0x00 |
duke@435 | 1427 | // 5: 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1428 | // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1429 | // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 |
duke@435 | 1430 | // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1431 | // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1432 | // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1433 | // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1434 | |
duke@435 | 1435 | // The rest coding is Intel specific - don't use consecutive address nops |
duke@435 | 1436 | |
duke@435 | 1437 | // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 |
duke@435 | 1438 | // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 |
duke@435 | 1439 | // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 |
duke@435 | 1440 | // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 |
duke@435 | 1441 | |
duke@435 | 1442 | while(i >= 15) { |
duke@435 | 1443 | // For Intel don't generate consecutive addess nops (mix with regular nops) |
duke@435 | 1444 | i -= 15; |
duke@435 | 1445 | emit_byte(0x66); // size prefix |
duke@435 | 1446 | emit_byte(0x66); // size prefix |
duke@435 | 1447 | emit_byte(0x66); // size prefix |
duke@435 | 1448 | addr_nop_8(); |
duke@435 | 1449 | emit_byte(0x66); // size prefix |
duke@435 | 1450 | emit_byte(0x66); // size prefix |
duke@435 | 1451 | emit_byte(0x66); // size prefix |
duke@435 | 1452 | emit_byte(0x90); // nop |
duke@435 | 1453 | } |
duke@435 | 1454 | switch (i) { |
duke@435 | 1455 | case 14: |
duke@435 | 1456 | emit_byte(0x66); // size prefix |
duke@435 | 1457 | case 13: |
duke@435 | 1458 | emit_byte(0x66); // size prefix |
duke@435 | 1459 | case 12: |
duke@435 | 1460 | addr_nop_8(); |
duke@435 | 1461 | emit_byte(0x66); // size prefix |
duke@435 | 1462 | emit_byte(0x66); // size prefix |
duke@435 | 1463 | emit_byte(0x66); // size prefix |
duke@435 | 1464 | emit_byte(0x90); // nop |
duke@435 | 1465 | break; |
duke@435 | 1466 | case 11: |
duke@435 | 1467 | emit_byte(0x66); // size prefix |
duke@435 | 1468 | case 10: |
duke@435 | 1469 | emit_byte(0x66); // size prefix |
duke@435 | 1470 | case 9: |
duke@435 | 1471 | emit_byte(0x66); // size prefix |
duke@435 | 1472 | case 8: |
duke@435 | 1473 | addr_nop_8(); |
duke@435 | 1474 | break; |
duke@435 | 1475 | case 7: |
duke@435 | 1476 | addr_nop_7(); |
duke@435 | 1477 | break; |
duke@435 | 1478 | case 6: |
duke@435 | 1479 | emit_byte(0x66); // size prefix |
duke@435 | 1480 | case 5: |
duke@435 | 1481 | addr_nop_5(); |
duke@435 | 1482 | break; |
duke@435 | 1483 | case 4: |
duke@435 | 1484 | addr_nop_4(); |
duke@435 | 1485 | break; |
duke@435 | 1486 | case 3: |
duke@435 | 1487 | // Don't use "0x0F 0x1F 0x00" - need patching safe padding |
duke@435 | 1488 | emit_byte(0x66); // size prefix |
duke@435 | 1489 | case 2: |
duke@435 | 1490 | emit_byte(0x66); // size prefix |
duke@435 | 1491 | case 1: |
duke@435 | 1492 | emit_byte(0x90); // nop |
duke@435 | 1493 | break; |
duke@435 | 1494 | default: |
duke@435 | 1495 | assert(i == 0, " "); |
duke@435 | 1496 | } |
duke@435 | 1497 | return; |
duke@435 | 1498 | } |
duke@435 | 1499 | if (UseAddressNop && VM_Version::is_amd()) { |
duke@435 | 1500 | // |
duke@435 | 1501 | // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. |
duke@435 | 1502 | // 1: 0x90 |
duke@435 | 1503 | // 2: 0x66 0x90 |
duke@435 | 1504 | // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) |
duke@435 | 1505 | // 4: 0x0F 0x1F 0x40 0x00 |
duke@435 | 1506 | // 5: 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1507 | // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1508 | // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 |
duke@435 | 1509 | // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1510 | // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1511 | // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1512 | // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1513 | |
duke@435 | 1514 | // The rest coding is AMD specific - use consecutive address nops |
duke@435 | 1515 | |
duke@435 | 1516 | // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1517 | // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 |
duke@435 | 1518 | // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 |
duke@435 | 1519 | // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 |
duke@435 | 1520 | // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 |
duke@435 | 1521 | // Size prefixes (0x66) are added for larger sizes |
duke@435 | 1522 | |
duke@435 | 1523 | while(i >= 22) { |
duke@435 | 1524 | i -= 11; |
duke@435 | 1525 | emit_byte(0x66); // size prefix |
duke@435 | 1526 | emit_byte(0x66); // size prefix |
duke@435 | 1527 | emit_byte(0x66); // size prefix |
duke@435 | 1528 | addr_nop_8(); |
duke@435 | 1529 | } |
duke@435 | 1530 | // Generate first nop for size between 21-12 |
duke@435 | 1531 | switch (i) { |
duke@435 | 1532 | case 21: |
duke@435 | 1533 | i -= 1; |
duke@435 | 1534 | emit_byte(0x66); // size prefix |
duke@435 | 1535 | case 20: |
duke@435 | 1536 | case 19: |
duke@435 | 1537 | i -= 1; |
duke@435 | 1538 | emit_byte(0x66); // size prefix |
duke@435 | 1539 | case 18: |
duke@435 | 1540 | case 17: |
duke@435 | 1541 | i -= 1; |
duke@435 | 1542 | emit_byte(0x66); // size prefix |
duke@435 | 1543 | case 16: |
duke@435 | 1544 | case 15: |
duke@435 | 1545 | i -= 8; |
duke@435 | 1546 | addr_nop_8(); |
duke@435 | 1547 | break; |
duke@435 | 1548 | case 14: |
duke@435 | 1549 | case 13: |
duke@435 | 1550 | i -= 7; |
duke@435 | 1551 | addr_nop_7(); |
duke@435 | 1552 | break; |
duke@435 | 1553 | case 12: |
duke@435 | 1554 | i -= 6; |
duke@435 | 1555 | emit_byte(0x66); // size prefix |
duke@435 | 1556 | addr_nop_5(); |
duke@435 | 1557 | break; |
duke@435 | 1558 | default: |
duke@435 | 1559 | assert(i < 12, " "); |
duke@435 | 1560 | } |
duke@435 | 1561 | |
duke@435 | 1562 | // Generate second nop for size between 11-1 |
duke@435 | 1563 | switch (i) { |
duke@435 | 1564 | case 11: |
duke@435 | 1565 | emit_byte(0x66); // size prefix |
duke@435 | 1566 | case 10: |
duke@435 | 1567 | emit_byte(0x66); // size prefix |
duke@435 | 1568 | case 9: |
duke@435 | 1569 | emit_byte(0x66); // size prefix |
duke@435 | 1570 | case 8: |
duke@435 | 1571 | addr_nop_8(); |
duke@435 | 1572 | break; |
duke@435 | 1573 | case 7: |
duke@435 | 1574 | addr_nop_7(); |
duke@435 | 1575 | break; |
duke@435 | 1576 | case 6: |
duke@435 | 1577 | emit_byte(0x66); // size prefix |
duke@435 | 1578 | case 5: |
duke@435 | 1579 | addr_nop_5(); |
duke@435 | 1580 | break; |
duke@435 | 1581 | case 4: |
duke@435 | 1582 | addr_nop_4(); |
duke@435 | 1583 | break; |
duke@435 | 1584 | case 3: |
duke@435 | 1585 | // Don't use "0x0F 0x1F 0x00" - need patching safe padding |
duke@435 | 1586 | emit_byte(0x66); // size prefix |
duke@435 | 1587 | case 2: |
duke@435 | 1588 | emit_byte(0x66); // size prefix |
duke@435 | 1589 | case 1: |
duke@435 | 1590 | emit_byte(0x90); // nop |
duke@435 | 1591 | break; |
duke@435 | 1592 | default: |
duke@435 | 1593 | assert(i == 0, " "); |
duke@435 | 1594 | } |
duke@435 | 1595 | return; |
duke@435 | 1596 | } |
duke@435 | 1597 | |
duke@435 | 1598 | // Using nops with size prefixes "0x66 0x90". |
duke@435 | 1599 | // From AMD Optimization Guide: |
duke@435 | 1600 | // 1: 0x90 |
duke@435 | 1601 | // 2: 0x66 0x90 |
duke@435 | 1602 | // 3: 0x66 0x66 0x90 |
duke@435 | 1603 | // 4: 0x66 0x66 0x66 0x90 |
duke@435 | 1604 | // 5: 0x66 0x66 0x90 0x66 0x90 |
duke@435 | 1605 | // 6: 0x66 0x66 0x90 0x66 0x66 0x90 |
duke@435 | 1606 | // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 |
duke@435 | 1607 | // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 |
duke@435 | 1608 | // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 |
duke@435 | 1609 | // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 |
duke@435 | 1610 | // |
duke@435 | 1611 | while(i > 12) { |
duke@435 | 1612 | i -= 4; |
duke@435 | 1613 | emit_byte(0x66); // size prefix |
duke@435 | 1614 | emit_byte(0x66); |
duke@435 | 1615 | emit_byte(0x66); |
duke@435 | 1616 | emit_byte(0x90); // nop |
duke@435 | 1617 | } |
duke@435 | 1618 | // 1 - 12 nops |
duke@435 | 1619 | if(i > 8) { |
duke@435 | 1620 | if(i > 9) { |
duke@435 | 1621 | i -= 1; |
duke@435 | 1622 | emit_byte(0x66); |
duke@435 | 1623 | } |
duke@435 | 1624 | i -= 3; |
duke@435 | 1625 | emit_byte(0x66); |
duke@435 | 1626 | emit_byte(0x66); |
duke@435 | 1627 | emit_byte(0x90); |
duke@435 | 1628 | } |
duke@435 | 1629 | // 1 - 8 nops |
duke@435 | 1630 | if(i > 4) { |
duke@435 | 1631 | if(i > 6) { |
duke@435 | 1632 | i -= 1; |
duke@435 | 1633 | emit_byte(0x66); |
duke@435 | 1634 | } |
duke@435 | 1635 | i -= 3; |
duke@435 | 1636 | emit_byte(0x66); |
duke@435 | 1637 | emit_byte(0x66); |
duke@435 | 1638 | emit_byte(0x90); |
duke@435 | 1639 | } |
duke@435 | 1640 | switch (i) { |
duke@435 | 1641 | case 4: |
duke@435 | 1642 | emit_byte(0x66); |
duke@435 | 1643 | case 3: |
duke@435 | 1644 | emit_byte(0x66); |
duke@435 | 1645 | case 2: |
duke@435 | 1646 | emit_byte(0x66); |
duke@435 | 1647 | case 1: |
duke@435 | 1648 | emit_byte(0x90); |
duke@435 | 1649 | break; |
duke@435 | 1650 | default: |
duke@435 | 1651 | assert(i == 0, " "); |
duke@435 | 1652 | } |
duke@435 | 1653 | } |
duke@435 | 1654 | |
duke@435 | 1655 | void Assembler::ret(int imm16) { |
duke@435 | 1656 | if (imm16 == 0) { |
duke@435 | 1657 | emit_byte(0xC3); |
duke@435 | 1658 | } else { |
duke@435 | 1659 | emit_byte(0xC2); |
duke@435 | 1660 | emit_word(imm16); |
duke@435 | 1661 | } |
duke@435 | 1662 | } |
duke@435 | 1663 | |
duke@435 | 1664 | |
duke@435 | 1665 | void Assembler::set_byte_if_not_zero(Register dst) { |
duke@435 | 1666 | emit_byte(0x0F); |
duke@435 | 1667 | emit_byte(0x95); |
duke@435 | 1668 | emit_byte(0xE0 | dst->encoding()); |
duke@435 | 1669 | } |
duke@435 | 1670 | |
duke@435 | 1671 | |
duke@435 | 1672 | // copies a single word from [esi] to [edi] |
duke@435 | 1673 | void Assembler::smovl() { |
duke@435 | 1674 | emit_byte(0xA5); |
duke@435 | 1675 | } |
duke@435 | 1676 | |
duke@435 | 1677 | // copies data from [esi] to [edi] using rcx double words (m32) |
duke@435 | 1678 | void Assembler::rep_movl() { |
duke@435 | 1679 | emit_byte(0xF3); |
duke@435 | 1680 | emit_byte(0xA5); |
duke@435 | 1681 | } |
duke@435 | 1682 | |
duke@435 | 1683 | |
duke@435 | 1684 | // sets rcx double words (m32) with rax, value at [edi] |
duke@435 | 1685 | void Assembler::rep_set() { |
duke@435 | 1686 | emit_byte(0xF3); |
duke@435 | 1687 | emit_byte(0xAB); |
duke@435 | 1688 | } |
duke@435 | 1689 | |
duke@435 | 1690 | // scans rcx double words (m32) at [edi] for occurance of rax, |
duke@435 | 1691 | void Assembler::repne_scan() { |
duke@435 | 1692 | emit_byte(0xF2); |
duke@435 | 1693 | emit_byte(0xAF); |
duke@435 | 1694 | } |
duke@435 | 1695 | |
duke@435 | 1696 | |
duke@435 | 1697 | void Assembler::setb(Condition cc, Register dst) { |
duke@435 | 1698 | assert(0 <= cc && cc < 16, "illegal cc"); |
duke@435 | 1699 | emit_byte(0x0F); |
duke@435 | 1700 | emit_byte(0x90 | cc); |
duke@435 | 1701 | emit_byte(0xC0 | dst->encoding()); |
duke@435 | 1702 | } |
duke@435 | 1703 | |
duke@435 | 1704 | void Assembler::cld() { |
duke@435 | 1705 | emit_byte(0xfc); |
duke@435 | 1706 | } |
duke@435 | 1707 | |
duke@435 | 1708 | void Assembler::std() { |
duke@435 | 1709 | emit_byte(0xfd); |
duke@435 | 1710 | } |
duke@435 | 1711 | |
duke@435 | 1712 | void Assembler::emit_raw (unsigned char b) { |
duke@435 | 1713 | emit_byte (b) ; |
duke@435 | 1714 | } |
duke@435 | 1715 | |
duke@435 | 1716 | // Serializes memory. |
duke@435 | 1717 | void Assembler::membar() { |
duke@435 | 1718 | // Memory barriers are only needed on multiprocessors |
duke@435 | 1719 | if (os::is_MP()) { |
duke@435 | 1720 | if( VM_Version::supports_sse2() ) { |
duke@435 | 1721 | emit_byte( 0x0F ); // MFENCE; faster blows no regs |
duke@435 | 1722 | emit_byte( 0xAE ); |
duke@435 | 1723 | emit_byte( 0xF0 ); |
duke@435 | 1724 | } else { |
duke@435 | 1725 | // All usable chips support "locked" instructions which suffice |
duke@435 | 1726 | // as barriers, and are much faster than the alternative of |
duke@435 | 1727 | // using cpuid instruction. We use here a locked add [esp],0. |
duke@435 | 1728 | // This is conveniently otherwise a no-op except for blowing |
duke@435 | 1729 | // flags (which we save and restore.) |
duke@435 | 1730 | pushfd(); // Save eflags register |
duke@435 | 1731 | lock(); |
duke@435 | 1732 | addl(Address(rsp, 0), 0);// Assert the lock# signal here |
duke@435 | 1733 | popfd(); // Restore eflags register |
duke@435 | 1734 | } |
duke@435 | 1735 | } |
duke@435 | 1736 | } |
duke@435 | 1737 | |
duke@435 | 1738 | // Identify processor type and features |
duke@435 | 1739 | void Assembler::cpuid() { |
duke@435 | 1740 | // Note: we can't assert VM_Version::supports_cpuid() here |
duke@435 | 1741 | // because this instruction is used in the processor |
duke@435 | 1742 | // identification code. |
duke@435 | 1743 | emit_byte( 0x0F ); |
duke@435 | 1744 | emit_byte( 0xA2 ); |
duke@435 | 1745 | } |
duke@435 | 1746 | |
duke@435 | 1747 | void Assembler::call(Label& L, relocInfo::relocType rtype) { |
duke@435 | 1748 | if (L.is_bound()) { |
duke@435 | 1749 | const int long_size = 5; |
duke@435 | 1750 | int offs = target(L) - pc(); |
duke@435 | 1751 | assert(offs <= 0, "assembler error"); |
duke@435 | 1752 | InstructionMark im(this); |
duke@435 | 1753 | // 1110 1000 #32-bit disp |
duke@435 | 1754 | emit_byte(0xE8); |
duke@435 | 1755 | emit_data(offs - long_size, rtype, 0); |
duke@435 | 1756 | } else { |
duke@435 | 1757 | InstructionMark im(this); |
duke@435 | 1758 | // 1110 1000 #32-bit disp |
duke@435 | 1759 | L.add_patch_at(code(), locator()); |
duke@435 | 1760 | emit_byte(0xE8); |
duke@435 | 1761 | emit_data(int(0), rtype, 0); |
duke@435 | 1762 | } |
duke@435 | 1763 | } |
duke@435 | 1764 | |
duke@435 | 1765 | void Assembler::call(Register dst) { |
duke@435 | 1766 | emit_byte(0xFF); |
duke@435 | 1767 | emit_byte(0xD0 | dst->encoding()); |
duke@435 | 1768 | } |
duke@435 | 1769 | |
duke@435 | 1770 | |
duke@435 | 1771 | void Assembler::call(Address adr) { |
duke@435 | 1772 | InstructionMark im(this); |
duke@435 | 1773 | relocInfo::relocType rtype = adr.reloc(); |
duke@435 | 1774 | if (rtype != relocInfo::runtime_call_type) { |
duke@435 | 1775 | emit_byte(0xFF); |
duke@435 | 1776 | emit_operand(rdx, adr); |
duke@435 | 1777 | } else { |
duke@435 | 1778 | assert(false, "ack"); |
duke@435 | 1779 | } |
duke@435 | 1780 | |
duke@435 | 1781 | } |
duke@435 | 1782 | |
duke@435 | 1783 | void Assembler::call_literal(address dest, RelocationHolder const& rspec) { |
duke@435 | 1784 | InstructionMark im(this); |
duke@435 | 1785 | emit_byte(0xE8); |
duke@435 | 1786 | intptr_t disp = dest - (_code_pos + sizeof(int32_t)); |
duke@435 | 1787 | assert(dest != NULL, "must have a target"); |
duke@435 | 1788 | emit_data(disp, rspec, call32_operand); |
duke@435 | 1789 | |
duke@435 | 1790 | } |
duke@435 | 1791 | |
duke@435 | 1792 | void Assembler::jmp(Register entry) { |
duke@435 | 1793 | emit_byte(0xFF); |
duke@435 | 1794 | emit_byte(0xE0 | entry->encoding()); |
duke@435 | 1795 | } |
duke@435 | 1796 | |
duke@435 | 1797 | |
duke@435 | 1798 | void Assembler::jmp(Address adr) { |
duke@435 | 1799 | InstructionMark im(this); |
duke@435 | 1800 | emit_byte(0xFF); |
duke@435 | 1801 | emit_operand(rsp, adr); |
duke@435 | 1802 | } |
duke@435 | 1803 | |
duke@435 | 1804 | void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { |
duke@435 | 1805 | InstructionMark im(this); |
duke@435 | 1806 | emit_byte(0xE9); |
duke@435 | 1807 | assert(dest != NULL, "must have a target"); |
duke@435 | 1808 | intptr_t disp = dest - (_code_pos + sizeof(int32_t)); |
duke@435 | 1809 | emit_data(disp, rspec.reloc(), call32_operand); |
duke@435 | 1810 | } |
duke@435 | 1811 | |
duke@435 | 1812 | void Assembler::jmp(Label& L, relocInfo::relocType rtype) { |
duke@435 | 1813 | if (L.is_bound()) { |
duke@435 | 1814 | address entry = target(L); |
duke@435 | 1815 | assert(entry != NULL, "jmp most probably wrong"); |
duke@435 | 1816 | InstructionMark im(this); |
duke@435 | 1817 | const int short_size = 2; |
duke@435 | 1818 | const int long_size = 5; |
duke@435 | 1819 | intptr_t offs = entry - _code_pos; |
duke@435 | 1820 | if (rtype == relocInfo::none && is8bit(offs - short_size)) { |
duke@435 | 1821 | emit_byte(0xEB); |
duke@435 | 1822 | emit_byte((offs - short_size) & 0xFF); |
duke@435 | 1823 | } else { |
duke@435 | 1824 | emit_byte(0xE9); |
duke@435 | 1825 | emit_long(offs - long_size); |
duke@435 | 1826 | } |
duke@435 | 1827 | } else { |
duke@435 | 1828 | // By default, forward jumps are always 32-bit displacements, since |
duke@435 | 1829 | // we can't yet know where the label will be bound. If you're sure that |
duke@435 | 1830 | // the forward jump will not run beyond 256 bytes, use jmpb to |
duke@435 | 1831 | // force an 8-bit displacement. |
duke@435 | 1832 | InstructionMark im(this); |
duke@435 | 1833 | relocate(rtype); |
duke@435 | 1834 | L.add_patch_at(code(), locator()); |
duke@435 | 1835 | emit_byte(0xE9); |
duke@435 | 1836 | emit_long(0); |
duke@435 | 1837 | } |
duke@435 | 1838 | } |
duke@435 | 1839 | |
duke@435 | 1840 | void Assembler::jmpb(Label& L) { |
duke@435 | 1841 | if (L.is_bound()) { |
duke@435 | 1842 | const int short_size = 2; |
duke@435 | 1843 | address entry = target(L); |
duke@435 | 1844 | assert(is8bit((entry - _code_pos) + short_size), |
duke@435 | 1845 | "Dispacement too large for a short jmp"); |
duke@435 | 1846 | assert(entry != NULL, "jmp most probably wrong"); |
duke@435 | 1847 | intptr_t offs = entry - _code_pos; |
duke@435 | 1848 | emit_byte(0xEB); |
duke@435 | 1849 | emit_byte((offs - short_size) & 0xFF); |
duke@435 | 1850 | } else { |
duke@435 | 1851 | InstructionMark im(this); |
duke@435 | 1852 | L.add_patch_at(code(), locator()); |
duke@435 | 1853 | emit_byte(0xEB); |
duke@435 | 1854 | emit_byte(0); |
duke@435 | 1855 | } |
duke@435 | 1856 | } |
duke@435 | 1857 | |
duke@435 | 1858 | void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { |
duke@435 | 1859 | InstructionMark im(this); |
duke@435 | 1860 | relocate(rtype); |
duke@435 | 1861 | assert((0 <= cc) && (cc < 16), "illegal cc"); |
duke@435 | 1862 | if (L.is_bound()) { |
duke@435 | 1863 | address dst = target(L); |
duke@435 | 1864 | assert(dst != NULL, "jcc most probably wrong"); |
duke@435 | 1865 | |
duke@435 | 1866 | const int short_size = 2; |
duke@435 | 1867 | const int long_size = 6; |
duke@435 | 1868 | int offs = (int)dst - ((int)_code_pos); |
duke@435 | 1869 | if (rtype == relocInfo::none && is8bit(offs - short_size)) { |
duke@435 | 1870 | // 0111 tttn #8-bit disp |
duke@435 | 1871 | emit_byte(0x70 | cc); |
duke@435 | 1872 | emit_byte((offs - short_size) & 0xFF); |
duke@435 | 1873 | } else { |
duke@435 | 1874 | // 0000 1111 1000 tttn #32-bit disp |
duke@435 | 1875 | emit_byte(0x0F); |
duke@435 | 1876 | emit_byte(0x80 | cc); |
duke@435 | 1877 | emit_long(offs - long_size); |
duke@435 | 1878 | } |
duke@435 | 1879 | } else { |
duke@435 | 1880 | // Note: could eliminate cond. jumps to this jump if condition |
duke@435 | 1881 | // is the same however, seems to be rather unlikely case. |
duke@435 | 1882 | // Note: use jccb() if label to be bound is very close to get |
duke@435 | 1883 | // an 8-bit displacement |
duke@435 | 1884 | L.add_patch_at(code(), locator()); |
duke@435 | 1885 | emit_byte(0x0F); |
duke@435 | 1886 | emit_byte(0x80 | cc); |
duke@435 | 1887 | emit_long(0); |
duke@435 | 1888 | } |
duke@435 | 1889 | } |
duke@435 | 1890 | |
duke@435 | 1891 | void Assembler::jccb(Condition cc, Label& L) { |
duke@435 | 1892 | if (L.is_bound()) { |
duke@435 | 1893 | const int short_size = 2; |
duke@435 | 1894 | address entry = target(L); |
duke@435 | 1895 | assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), |
duke@435 | 1896 | "Dispacement too large for a short jmp"); |
duke@435 | 1897 | intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; |
duke@435 | 1898 | // 0111 tttn #8-bit disp |
duke@435 | 1899 | emit_byte(0x70 | cc); |
duke@435 | 1900 | emit_byte((offs - short_size) & 0xFF); |
duke@435 | 1901 | jcc(cc, L); |
duke@435 | 1902 | } else { |
duke@435 | 1903 | InstructionMark im(this); |
duke@435 | 1904 | L.add_patch_at(code(), locator()); |
duke@435 | 1905 | emit_byte(0x70 | cc); |
duke@435 | 1906 | emit_byte(0); |
duke@435 | 1907 | } |
duke@435 | 1908 | } |
duke@435 | 1909 | |
duke@435 | 1910 | // FPU instructions |
duke@435 | 1911 | |
duke@435 | 1912 | void Assembler::fld1() { |
duke@435 | 1913 | emit_byte(0xD9); |
duke@435 | 1914 | emit_byte(0xE8); |
duke@435 | 1915 | } |
duke@435 | 1916 | |
duke@435 | 1917 | |
duke@435 | 1918 | void Assembler::fldz() { |
duke@435 | 1919 | emit_byte(0xD9); |
duke@435 | 1920 | emit_byte(0xEE); |
duke@435 | 1921 | } |
duke@435 | 1922 | |
duke@435 | 1923 | |
duke@435 | 1924 | void Assembler::fld_s(Address adr) { |
duke@435 | 1925 | InstructionMark im(this); |
duke@435 | 1926 | emit_byte(0xD9); |
duke@435 | 1927 | emit_operand(rax, adr); |
duke@435 | 1928 | } |
duke@435 | 1929 | |
duke@435 | 1930 | |
duke@435 | 1931 | void Assembler::fld_s (int index) { |
duke@435 | 1932 | emit_farith(0xD9, 0xC0, index); |
duke@435 | 1933 | } |
duke@435 | 1934 | |
duke@435 | 1935 | |
duke@435 | 1936 | void Assembler::fld_d(Address adr) { |
duke@435 | 1937 | InstructionMark im(this); |
duke@435 | 1938 | emit_byte(0xDD); |
duke@435 | 1939 | emit_operand(rax, adr); |
duke@435 | 1940 | } |
duke@435 | 1941 | |
duke@435 | 1942 | |
duke@435 | 1943 | void Assembler::fld_x(Address adr) { |
duke@435 | 1944 | InstructionMark im(this); |
duke@435 | 1945 | emit_byte(0xDB); |
duke@435 | 1946 | emit_operand(rbp, adr); |
duke@435 | 1947 | } |
duke@435 | 1948 | |
duke@435 | 1949 | |
duke@435 | 1950 | void Assembler::fst_s(Address adr) { |
duke@435 | 1951 | InstructionMark im(this); |
duke@435 | 1952 | emit_byte(0xD9); |
duke@435 | 1953 | emit_operand(rdx, adr); |
duke@435 | 1954 | } |
duke@435 | 1955 | |
duke@435 | 1956 | |
duke@435 | 1957 | void Assembler::fst_d(Address adr) { |
duke@435 | 1958 | InstructionMark im(this); |
duke@435 | 1959 | emit_byte(0xDD); |
duke@435 | 1960 | emit_operand(rdx, adr); |
duke@435 | 1961 | } |
duke@435 | 1962 | |
duke@435 | 1963 | |
duke@435 | 1964 | void Assembler::fstp_s(Address adr) { |
duke@435 | 1965 | InstructionMark im(this); |
duke@435 | 1966 | emit_byte(0xD9); |
duke@435 | 1967 | emit_operand(rbx, adr); |
duke@435 | 1968 | } |
duke@435 | 1969 | |
duke@435 | 1970 | |
duke@435 | 1971 | void Assembler::fstp_d(Address adr) { |
duke@435 | 1972 | InstructionMark im(this); |
duke@435 | 1973 | emit_byte(0xDD); |
duke@435 | 1974 | emit_operand(rbx, adr); |
duke@435 | 1975 | } |
duke@435 | 1976 | |
duke@435 | 1977 | |
duke@435 | 1978 | void Assembler::fstp_x(Address adr) { |
duke@435 | 1979 | InstructionMark im(this); |
duke@435 | 1980 | emit_byte(0xDB); |
duke@435 | 1981 | emit_operand(rdi, adr); |
duke@435 | 1982 | } |
duke@435 | 1983 | |
duke@435 | 1984 | |
duke@435 | 1985 | void Assembler::fstp_d(int index) { |
duke@435 | 1986 | emit_farith(0xDD, 0xD8, index); |
duke@435 | 1987 | } |
duke@435 | 1988 | |
duke@435 | 1989 | |
duke@435 | 1990 | void Assembler::fild_s(Address adr) { |
duke@435 | 1991 | InstructionMark im(this); |
duke@435 | 1992 | emit_byte(0xDB); |
duke@435 | 1993 | emit_operand(rax, adr); |
duke@435 | 1994 | } |
duke@435 | 1995 | |
duke@435 | 1996 | |
duke@435 | 1997 | void Assembler::fild_d(Address adr) { |
duke@435 | 1998 | InstructionMark im(this); |
duke@435 | 1999 | emit_byte(0xDF); |
duke@435 | 2000 | emit_operand(rbp, adr); |
duke@435 | 2001 | } |
duke@435 | 2002 | |
duke@435 | 2003 | |
duke@435 | 2004 | void Assembler::fistp_s(Address adr) { |
duke@435 | 2005 | InstructionMark im(this); |
duke@435 | 2006 | emit_byte(0xDB); |
duke@435 | 2007 | emit_operand(rbx, adr); |
duke@435 | 2008 | } |
duke@435 | 2009 | |
duke@435 | 2010 | |
duke@435 | 2011 | void Assembler::fistp_d(Address adr) { |
duke@435 | 2012 | InstructionMark im(this); |
duke@435 | 2013 | emit_byte(0xDF); |
duke@435 | 2014 | emit_operand(rdi, adr); |
duke@435 | 2015 | } |
duke@435 | 2016 | |
duke@435 | 2017 | |
duke@435 | 2018 | void Assembler::fist_s(Address adr) { |
duke@435 | 2019 | InstructionMark im(this); |
duke@435 | 2020 | emit_byte(0xDB); |
duke@435 | 2021 | emit_operand(rdx, adr); |
duke@435 | 2022 | } |
duke@435 | 2023 | |
duke@435 | 2024 | |
duke@435 | 2025 | void Assembler::fabs() { |
duke@435 | 2026 | emit_byte(0xD9); |
duke@435 | 2027 | emit_byte(0xE1); |
duke@435 | 2028 | } |
duke@435 | 2029 | |
duke@435 | 2030 | |
duke@435 | 2031 | void Assembler::fldln2() { |
duke@435 | 2032 | emit_byte(0xD9); |
duke@435 | 2033 | emit_byte(0xED); |
duke@435 | 2034 | } |
duke@435 | 2035 | |
duke@435 | 2036 | void Assembler::fyl2x() { |
duke@435 | 2037 | emit_byte(0xD9); |
duke@435 | 2038 | emit_byte(0xF1); |
duke@435 | 2039 | } |
duke@435 | 2040 | |
duke@435 | 2041 | |
duke@435 | 2042 | void Assembler::fldlg2() { |
duke@435 | 2043 | emit_byte(0xD9); |
duke@435 | 2044 | emit_byte(0xEC); |
duke@435 | 2045 | } |
duke@435 | 2046 | |
duke@435 | 2047 | |
duke@435 | 2048 | void Assembler::flog() { |
duke@435 | 2049 | fldln2(); |
duke@435 | 2050 | fxch(); |
duke@435 | 2051 | fyl2x(); |
duke@435 | 2052 | } |
duke@435 | 2053 | |
duke@435 | 2054 | |
duke@435 | 2055 | void Assembler::flog10() { |
duke@435 | 2056 | fldlg2(); |
duke@435 | 2057 | fxch(); |
duke@435 | 2058 | fyl2x(); |
duke@435 | 2059 | } |
duke@435 | 2060 | |
duke@435 | 2061 | |
duke@435 | 2062 | void Assembler::fsin() { |
duke@435 | 2063 | emit_byte(0xD9); |
duke@435 | 2064 | emit_byte(0xFE); |
duke@435 | 2065 | } |
duke@435 | 2066 | |
duke@435 | 2067 | |
duke@435 | 2068 | void Assembler::fcos() { |
duke@435 | 2069 | emit_byte(0xD9); |
duke@435 | 2070 | emit_byte(0xFF); |
duke@435 | 2071 | } |
duke@435 | 2072 | |
duke@435 | 2073 | void Assembler::ftan() { |
duke@435 | 2074 | emit_byte(0xD9); |
duke@435 | 2075 | emit_byte(0xF2); |
duke@435 | 2076 | emit_byte(0xDD); |
duke@435 | 2077 | emit_byte(0xD8); |
duke@435 | 2078 | } |
duke@435 | 2079 | |
duke@435 | 2080 | void Assembler::fsqrt() { |
duke@435 | 2081 | emit_byte(0xD9); |
duke@435 | 2082 | emit_byte(0xFA); |
duke@435 | 2083 | } |
duke@435 | 2084 | |
duke@435 | 2085 | |
duke@435 | 2086 | void Assembler::fchs() { |
duke@435 | 2087 | emit_byte(0xD9); |
duke@435 | 2088 | emit_byte(0xE0); |
duke@435 | 2089 | } |
duke@435 | 2090 | |
duke@435 | 2091 | |
duke@435 | 2092 | void Assembler::fadd_s(Address src) { |
duke@435 | 2093 | InstructionMark im(this); |
duke@435 | 2094 | emit_byte(0xD8); |
duke@435 | 2095 | emit_operand(rax, src); |
duke@435 | 2096 | } |
duke@435 | 2097 | |
duke@435 | 2098 | |
duke@435 | 2099 | void Assembler::fadd_d(Address src) { |
duke@435 | 2100 | InstructionMark im(this); |
duke@435 | 2101 | emit_byte(0xDC); |
duke@435 | 2102 | emit_operand(rax, src); |
duke@435 | 2103 | } |
duke@435 | 2104 | |
duke@435 | 2105 | |
duke@435 | 2106 | void Assembler::fadd(int i) { |
duke@435 | 2107 | emit_farith(0xD8, 0xC0, i); |
duke@435 | 2108 | } |
duke@435 | 2109 | |
duke@435 | 2110 | |
duke@435 | 2111 | void Assembler::fadda(int i) { |
duke@435 | 2112 | emit_farith(0xDC, 0xC0, i); |
duke@435 | 2113 | } |
duke@435 | 2114 | |
duke@435 | 2115 | |
duke@435 | 2116 | void Assembler::fsub_d(Address src) { |
duke@435 | 2117 | InstructionMark im(this); |
duke@435 | 2118 | emit_byte(0xDC); |
duke@435 | 2119 | emit_operand(rsp, src); |
duke@435 | 2120 | } |
duke@435 | 2121 | |
duke@435 | 2122 | |
duke@435 | 2123 | void Assembler::fsub_s(Address src) { |
duke@435 | 2124 | InstructionMark im(this); |
duke@435 | 2125 | emit_byte(0xD8); |
duke@435 | 2126 | emit_operand(rsp, src); |
duke@435 | 2127 | } |
duke@435 | 2128 | |
duke@435 | 2129 | |
duke@435 | 2130 | void Assembler::fsubr_s(Address src) { |
duke@435 | 2131 | InstructionMark im(this); |
duke@435 | 2132 | emit_byte(0xD8); |
duke@435 | 2133 | emit_operand(rbp, src); |
duke@435 | 2134 | } |
duke@435 | 2135 | |
duke@435 | 2136 | |
duke@435 | 2137 | void Assembler::fsubr_d(Address src) { |
duke@435 | 2138 | InstructionMark im(this); |
duke@435 | 2139 | emit_byte(0xDC); |
duke@435 | 2140 | emit_operand(rbp, src); |
duke@435 | 2141 | } |
duke@435 | 2142 | |
duke@435 | 2143 | |
duke@435 | 2144 | void Assembler::fmul_s(Address src) { |
duke@435 | 2145 | InstructionMark im(this); |
duke@435 | 2146 | emit_byte(0xD8); |
duke@435 | 2147 | emit_operand(rcx, src); |
duke@435 | 2148 | } |
duke@435 | 2149 | |
duke@435 | 2150 | |
duke@435 | 2151 | void Assembler::fmul_d(Address src) { |
duke@435 | 2152 | InstructionMark im(this); |
duke@435 | 2153 | emit_byte(0xDC); |
duke@435 | 2154 | emit_operand(rcx, src); |
duke@435 | 2155 | } |
duke@435 | 2156 | |
duke@435 | 2157 | |
duke@435 | 2158 | void Assembler::fmul(int i) { |
duke@435 | 2159 | emit_farith(0xD8, 0xC8, i); |
duke@435 | 2160 | } |
duke@435 | 2161 | |
duke@435 | 2162 | |
duke@435 | 2163 | void Assembler::fmula(int i) { |
duke@435 | 2164 | emit_farith(0xDC, 0xC8, i); |
duke@435 | 2165 | } |
duke@435 | 2166 | |
duke@435 | 2167 | |
duke@435 | 2168 | void Assembler::fdiv_s(Address src) { |
duke@435 | 2169 | InstructionMark im(this); |
duke@435 | 2170 | emit_byte(0xD8); |
duke@435 | 2171 | emit_operand(rsi, src); |
duke@435 | 2172 | } |
duke@435 | 2173 | |
duke@435 | 2174 | |
duke@435 | 2175 | void Assembler::fdiv_d(Address src) { |
duke@435 | 2176 | InstructionMark im(this); |
duke@435 | 2177 | emit_byte(0xDC); |
duke@435 | 2178 | emit_operand(rsi, src); |
duke@435 | 2179 | } |
duke@435 | 2180 | |
duke@435 | 2181 | |
duke@435 | 2182 | void Assembler::fdivr_s(Address src) { |
duke@435 | 2183 | InstructionMark im(this); |
duke@435 | 2184 | emit_byte(0xD8); |
duke@435 | 2185 | emit_operand(rdi, src); |
duke@435 | 2186 | } |
duke@435 | 2187 | |
duke@435 | 2188 | |
duke@435 | 2189 | void Assembler::fdivr_d(Address src) { |
duke@435 | 2190 | InstructionMark im(this); |
duke@435 | 2191 | emit_byte(0xDC); |
duke@435 | 2192 | emit_operand(rdi, src); |
duke@435 | 2193 | } |
duke@435 | 2194 | |
duke@435 | 2195 | |
duke@435 | 2196 | void Assembler::fsub(int i) { |
duke@435 | 2197 | emit_farith(0xD8, 0xE0, i); |
duke@435 | 2198 | } |
duke@435 | 2199 | |
duke@435 | 2200 | |
duke@435 | 2201 | void Assembler::fsuba(int i) { |
duke@435 | 2202 | emit_farith(0xDC, 0xE8, i); |
duke@435 | 2203 | } |
duke@435 | 2204 | |
duke@435 | 2205 | |
duke@435 | 2206 | void Assembler::fsubr(int i) { |
duke@435 | 2207 | emit_farith(0xD8, 0xE8, i); |
duke@435 | 2208 | } |
duke@435 | 2209 | |
duke@435 | 2210 | |
duke@435 | 2211 | void Assembler::fsubra(int i) { |
duke@435 | 2212 | emit_farith(0xDC, 0xE0, i); |
duke@435 | 2213 | } |
duke@435 | 2214 | |
duke@435 | 2215 | |
duke@435 | 2216 | void Assembler::fdiv(int i) { |
duke@435 | 2217 | emit_farith(0xD8, 0xF0, i); |
duke@435 | 2218 | } |
duke@435 | 2219 | |
duke@435 | 2220 | |
duke@435 | 2221 | void Assembler::fdiva(int i) { |
duke@435 | 2222 | emit_farith(0xDC, 0xF8, i); |
duke@435 | 2223 | } |
duke@435 | 2224 | |
duke@435 | 2225 | |
duke@435 | 2226 | void Assembler::fdivr(int i) { |
duke@435 | 2227 | emit_farith(0xD8, 0xF8, i); |
duke@435 | 2228 | } |
duke@435 | 2229 | |
duke@435 | 2230 | |
duke@435 | 2231 | void Assembler::fdivra(int i) { |
duke@435 | 2232 | emit_farith(0xDC, 0xF0, i); |
duke@435 | 2233 | } |
duke@435 | 2234 | |
duke@435 | 2235 | |
duke@435 | 2236 | // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) |
duke@435 | 2237 | // is erroneous for some of the floating-point instructions below. |
duke@435 | 2238 | |
duke@435 | 2239 | void Assembler::fdivp(int i) { |
duke@435 | 2240 | emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) |
duke@435 | 2241 | } |
duke@435 | 2242 | |
duke@435 | 2243 | |
duke@435 | 2244 | void Assembler::fdivrp(int i) { |
duke@435 | 2245 | emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) |
duke@435 | 2246 | } |
duke@435 | 2247 | |
duke@435 | 2248 | |
duke@435 | 2249 | void Assembler::fsubp(int i) { |
duke@435 | 2250 | emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) |
duke@435 | 2251 | } |
duke@435 | 2252 | |
duke@435 | 2253 | |
duke@435 | 2254 | void Assembler::fsubrp(int i) { |
duke@435 | 2255 | emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) |
duke@435 | 2256 | } |
duke@435 | 2257 | |
duke@435 | 2258 | |
duke@435 | 2259 | void Assembler::faddp(int i) { |
duke@435 | 2260 | emit_farith(0xDE, 0xC0, i); |
duke@435 | 2261 | } |
duke@435 | 2262 | |
duke@435 | 2263 | |
duke@435 | 2264 | void Assembler::fmulp(int i) { |
duke@435 | 2265 | emit_farith(0xDE, 0xC8, i); |
duke@435 | 2266 | } |
duke@435 | 2267 | |
duke@435 | 2268 | |
duke@435 | 2269 | void Assembler::fprem() { |
duke@435 | 2270 | emit_byte(0xD9); |
duke@435 | 2271 | emit_byte(0xF8); |
duke@435 | 2272 | } |
duke@435 | 2273 | |
duke@435 | 2274 | |
duke@435 | 2275 | void Assembler::fprem1() { |
duke@435 | 2276 | emit_byte(0xD9); |
duke@435 | 2277 | emit_byte(0xF5); |
duke@435 | 2278 | } |
duke@435 | 2279 | |
duke@435 | 2280 | |
duke@435 | 2281 | void Assembler::fxch(int i) { |
duke@435 | 2282 | emit_farith(0xD9, 0xC8, i); |
duke@435 | 2283 | } |
duke@435 | 2284 | |
duke@435 | 2285 | |
duke@435 | 2286 | void Assembler::fincstp() { |
duke@435 | 2287 | emit_byte(0xD9); |
duke@435 | 2288 | emit_byte(0xF7); |
duke@435 | 2289 | } |
duke@435 | 2290 | |
duke@435 | 2291 | |
duke@435 | 2292 | void Assembler::fdecstp() { |
duke@435 | 2293 | emit_byte(0xD9); |
duke@435 | 2294 | emit_byte(0xF6); |
duke@435 | 2295 | } |
duke@435 | 2296 | |
duke@435 | 2297 | |
duke@435 | 2298 | void Assembler::ffree(int i) { |
duke@435 | 2299 | emit_farith(0xDD, 0xC0, i); |
duke@435 | 2300 | } |
duke@435 | 2301 | |
duke@435 | 2302 | |
duke@435 | 2303 | void Assembler::fcomp_s(Address src) { |
duke@435 | 2304 | InstructionMark im(this); |
duke@435 | 2305 | emit_byte(0xD8); |
duke@435 | 2306 | emit_operand(rbx, src); |
duke@435 | 2307 | } |
duke@435 | 2308 | |
duke@435 | 2309 | |
duke@435 | 2310 | void Assembler::fcomp_d(Address src) { |
duke@435 | 2311 | InstructionMark im(this); |
duke@435 | 2312 | emit_byte(0xDC); |
duke@435 | 2313 | emit_operand(rbx, src); |
duke@435 | 2314 | } |
duke@435 | 2315 | |
duke@435 | 2316 | |
duke@435 | 2317 | void Assembler::fcom(int i) { |
duke@435 | 2318 | emit_farith(0xD8, 0xD0, i); |
duke@435 | 2319 | } |
duke@435 | 2320 | |
duke@435 | 2321 | |
duke@435 | 2322 | void Assembler::fcomp(int i) { |
duke@435 | 2323 | emit_farith(0xD8, 0xD8, i); |
duke@435 | 2324 | } |
duke@435 | 2325 | |
duke@435 | 2326 | |
duke@435 | 2327 | void Assembler::fcompp() { |
duke@435 | 2328 | emit_byte(0xDE); |
duke@435 | 2329 | emit_byte(0xD9); |
duke@435 | 2330 | } |
duke@435 | 2331 | |
duke@435 | 2332 | |
duke@435 | 2333 | void Assembler::fucomi(int i) { |
duke@435 | 2334 | // make sure the instruction is supported (introduced for P6, together with cmov) |
duke@435 | 2335 | guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
duke@435 | 2336 | emit_farith(0xDB, 0xE8, i); |
duke@435 | 2337 | } |
duke@435 | 2338 | |
duke@435 | 2339 | |
duke@435 | 2340 | void Assembler::fucomip(int i) { |
duke@435 | 2341 | // make sure the instruction is supported (introduced for P6, together with cmov) |
duke@435 | 2342 | guarantee(VM_Version::supports_cmov(), "illegal instruction"); |
duke@435 | 2343 | emit_farith(0xDF, 0xE8, i); |
duke@435 | 2344 | } |
duke@435 | 2345 | |
duke@435 | 2346 | |
duke@435 | 2347 | void Assembler::ftst() { |
duke@435 | 2348 | emit_byte(0xD9); |
duke@435 | 2349 | emit_byte(0xE4); |
duke@435 | 2350 | } |
duke@435 | 2351 | |
duke@435 | 2352 | |
duke@435 | 2353 | void Assembler::fnstsw_ax() { |
duke@435 | 2354 | emit_byte(0xdF); |
duke@435 | 2355 | emit_byte(0xE0); |
duke@435 | 2356 | } |
duke@435 | 2357 | |
duke@435 | 2358 | |
duke@435 | 2359 | void Assembler::fwait() { |
duke@435 | 2360 | emit_byte(0x9B); |
duke@435 | 2361 | } |
duke@435 | 2362 | |
duke@435 | 2363 | |
duke@435 | 2364 | void Assembler::finit() { |
duke@435 | 2365 | emit_byte(0x9B); |
duke@435 | 2366 | emit_byte(0xDB); |
duke@435 | 2367 | emit_byte(0xE3); |
duke@435 | 2368 | } |
duke@435 | 2369 | |
duke@435 | 2370 | |
duke@435 | 2371 | void Assembler::fldcw(Address src) { |
duke@435 | 2372 | InstructionMark im(this); |
duke@435 | 2373 | emit_byte(0xd9); |
duke@435 | 2374 | emit_operand(rbp, src); |
duke@435 | 2375 | } |
duke@435 | 2376 | |
duke@435 | 2377 | |
duke@435 | 2378 | void Assembler::fnstcw(Address src) { |
duke@435 | 2379 | InstructionMark im(this); |
duke@435 | 2380 | emit_byte(0x9B); |
duke@435 | 2381 | emit_byte(0xD9); |
duke@435 | 2382 | emit_operand(rdi, src); |
duke@435 | 2383 | } |
duke@435 | 2384 | |
duke@435 | 2385 | void Assembler::fnsave(Address dst) { |
duke@435 | 2386 | InstructionMark im(this); |
duke@435 | 2387 | emit_byte(0xDD); |
duke@435 | 2388 | emit_operand(rsi, dst); |
duke@435 | 2389 | } |
duke@435 | 2390 | |
duke@435 | 2391 | |
duke@435 | 2392 | void Assembler::frstor(Address src) { |
duke@435 | 2393 | InstructionMark im(this); |
duke@435 | 2394 | emit_byte(0xDD); |
duke@435 | 2395 | emit_operand(rsp, src); |
duke@435 | 2396 | } |
duke@435 | 2397 | |
duke@435 | 2398 | |
duke@435 | 2399 | void Assembler::fldenv(Address src) { |
duke@435 | 2400 | InstructionMark im(this); |
duke@435 | 2401 | emit_byte(0xD9); |
duke@435 | 2402 | emit_operand(rsp, src); |
duke@435 | 2403 | } |
duke@435 | 2404 | |
duke@435 | 2405 | |
duke@435 | 2406 | void Assembler::sahf() { |
duke@435 | 2407 | emit_byte(0x9E); |
duke@435 | 2408 | } |
duke@435 | 2409 | |
duke@435 | 2410 | // MMX operations |
duke@435 | 2411 | void Assembler::emit_operand(MMXRegister reg, Address adr) { |
duke@435 | 2412 | emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); |
duke@435 | 2413 | } |
duke@435 | 2414 | |
duke@435 | 2415 | void Assembler::movq( MMXRegister dst, Address src ) { |
duke@435 | 2416 | assert( VM_Version::supports_mmx(), "" ); |
duke@435 | 2417 | emit_byte(0x0F); |
duke@435 | 2418 | emit_byte(0x6F); |
duke@435 | 2419 | emit_operand(dst,src); |
duke@435 | 2420 | } |
duke@435 | 2421 | |
duke@435 | 2422 | void Assembler::movq( Address dst, MMXRegister src ) { |
duke@435 | 2423 | assert( VM_Version::supports_mmx(), "" ); |
duke@435 | 2424 | emit_byte(0x0F); |
duke@435 | 2425 | emit_byte(0x7F); |
duke@435 | 2426 | emit_operand(src,dst); |
duke@435 | 2427 | } |
duke@435 | 2428 | |
duke@435 | 2429 | void Assembler::emms() { |
duke@435 | 2430 | emit_byte(0x0F); |
duke@435 | 2431 | emit_byte(0x77); |
duke@435 | 2432 | } |
duke@435 | 2433 | |
duke@435 | 2434 | |
duke@435 | 2435 | |
duke@435 | 2436 | |
duke@435 | 2437 | // SSE and SSE2 instructions |
duke@435 | 2438 | inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) { |
duke@435 | 2439 | assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid"); |
duke@435 | 2440 | emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); |
duke@435 | 2441 | } |
duke@435 | 2442 | inline void Assembler::emit_sse_operand(Register reg, Address adr) { |
duke@435 | 2443 | emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); |
duke@435 | 2444 | } |
duke@435 | 2445 | |
duke@435 | 2446 | inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { |
duke@435 | 2447 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 2448 | } |
duke@435 | 2449 | inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) { |
duke@435 | 2450 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 2451 | } |
duke@435 | 2452 | inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) { |
duke@435 | 2453 | emit_byte(0xC0 | dst->encoding() << 3 | src->encoding()); |
duke@435 | 2454 | } |
duke@435 | 2455 | |
duke@435 | 2456 | |
duke@435 | 2457 | // Macro for creation of SSE2 instructions |
duke@435 | 2458 | // The SSE2 instricution set is highly regular, so this macro saves |
duke@435 | 2459 | // a lot of cut&paste |
duke@435 | 2460 | // Each macro expansion creates two methods (same name with different |
duke@435 | 2461 | // parameter list) |
duke@435 | 2462 | // |
duke@435 | 2463 | // Macro parameters: |
duke@435 | 2464 | // * name: name of the created methods |
duke@435 | 2465 | // * sse_version: either sse or sse2 for the assertion if instruction supported by processor |
duke@435 | 2466 | // * prefix: first opcode byte of the instruction (or 0 if no prefix byte) |
duke@435 | 2467 | // * opcode: last opcode byte of the instruction |
duke@435 | 2468 | // * conversion instruction have parameters of type Register instead of XMMRegister, |
duke@435 | 2469 | // so this can also configured with macro parameters |
duke@435 | 2470 | #define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type) \ |
duke@435 | 2471 | \ |
duke@435 | 2472 | void Assembler:: name (dst_register_type dst, Address src) { \ |
duke@435 | 2473 | assert(VM_Version::supports_##sse_version(), ""); \ |
duke@435 | 2474 | \ |
duke@435 | 2475 | InstructionMark im(this); \ |
duke@435 | 2476 | if (prefix != 0) emit_byte(prefix); \ |
duke@435 | 2477 | emit_byte(0x0F); \ |
duke@435 | 2478 | emit_byte(opcode); \ |
duke@435 | 2479 | emit_sse_operand(dst, src); \ |
duke@435 | 2480 | } \ |
duke@435 | 2481 | \ |
duke@435 | 2482 | void Assembler:: name (dst_register_type dst, src_register_type src) { \ |
duke@435 | 2483 | assert(VM_Version::supports_##sse_version(), ""); \ |
duke@435 | 2484 | \ |
duke@435 | 2485 | if (prefix != 0) emit_byte(prefix); \ |
duke@435 | 2486 | emit_byte(0x0F); \ |
duke@435 | 2487 | emit_byte(opcode); \ |
duke@435 | 2488 | emit_sse_operand(dst, src); \ |
duke@435 | 2489 | } \ |
duke@435 | 2490 | |
duke@435 | 2491 | emit_sse_instruction(addss, sse, 0xF3, 0x58, XMMRegister, XMMRegister); |
duke@435 | 2492 | emit_sse_instruction(addsd, sse2, 0xF2, 0x58, XMMRegister, XMMRegister) |
duke@435 | 2493 | emit_sse_instruction(subss, sse, 0xF3, 0x5C, XMMRegister, XMMRegister) |
duke@435 | 2494 | emit_sse_instruction(subsd, sse2, 0xF2, 0x5C, XMMRegister, XMMRegister) |
duke@435 | 2495 | emit_sse_instruction(mulss, sse, 0xF3, 0x59, XMMRegister, XMMRegister) |
duke@435 | 2496 | emit_sse_instruction(mulsd, sse2, 0xF2, 0x59, XMMRegister, XMMRegister) |
duke@435 | 2497 | emit_sse_instruction(divss, sse, 0xF3, 0x5E, XMMRegister, XMMRegister) |
duke@435 | 2498 | emit_sse_instruction(divsd, sse2, 0xF2, 0x5E, XMMRegister, XMMRegister) |
duke@435 | 2499 | emit_sse_instruction(sqrtss, sse, 0xF3, 0x51, XMMRegister, XMMRegister) |
duke@435 | 2500 | emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister) |
duke@435 | 2501 | |
duke@435 | 2502 | emit_sse_instruction(pxor, sse2, 0x66, 0xEF, XMMRegister, XMMRegister) |
duke@435 | 2503 | |
duke@435 | 2504 | emit_sse_instruction(comiss, sse, 0, 0x2F, XMMRegister, XMMRegister) |
duke@435 | 2505 | emit_sse_instruction(comisd, sse2, 0x66, 0x2F, XMMRegister, XMMRegister) |
duke@435 | 2506 | emit_sse_instruction(ucomiss, sse, 0, 0x2E, XMMRegister, XMMRegister) |
duke@435 | 2507 | emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister) |
duke@435 | 2508 | |
duke@435 | 2509 | emit_sse_instruction(cvtss2sd, sse2, 0xF3, 0x5A, XMMRegister, XMMRegister); |
duke@435 | 2510 | emit_sse_instruction(cvtsd2ss, sse2, 0xF2, 0x5A, XMMRegister, XMMRegister) |
duke@435 | 2511 | emit_sse_instruction(cvtsi2ss, sse, 0xF3, 0x2A, XMMRegister, Register); |
duke@435 | 2512 | emit_sse_instruction(cvtsi2sd, sse2, 0xF2, 0x2A, XMMRegister, Register) |
duke@435 | 2513 | emit_sse_instruction(cvtss2si, sse, 0xF3, 0x2D, Register, XMMRegister); |
duke@435 | 2514 | emit_sse_instruction(cvtsd2si, sse2, 0xF2, 0x2D, Register, XMMRegister) |
duke@435 | 2515 | emit_sse_instruction(cvttss2si, sse, 0xF3, 0x2C, Register, XMMRegister); |
duke@435 | 2516 | emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister) |
duke@435 | 2517 | |
duke@435 | 2518 | emit_sse_instruction(movss, sse, 0xF3, 0x10, XMMRegister, XMMRegister) |
duke@435 | 2519 | emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister) |
duke@435 | 2520 | |
duke@435 | 2521 | emit_sse_instruction(movq, sse2, 0xF3, 0x7E, XMMRegister, XMMRegister); |
duke@435 | 2522 | emit_sse_instruction(movd, sse2, 0x66, 0x6E, XMMRegister, Register); |
duke@435 | 2523 | emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister); |
duke@435 | 2524 | |
duke@435 | 2525 | emit_sse_instruction(punpcklbw, sse2, 0x66, 0x60, XMMRegister, XMMRegister); |
duke@435 | 2526 | |
duke@435 | 2527 | |
duke@435 | 2528 | // Instruction not covered by macro |
duke@435 | 2529 | void Assembler::movq(Address dst, XMMRegister src) { |
duke@435 | 2530 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2531 | |
duke@435 | 2532 | InstructionMark im(this); |
duke@435 | 2533 | emit_byte(0x66); |
duke@435 | 2534 | emit_byte(0x0F); |
duke@435 | 2535 | emit_byte(0xD6); |
duke@435 | 2536 | emit_sse_operand(src, dst); |
duke@435 | 2537 | } |
duke@435 | 2538 | |
duke@435 | 2539 | void Assembler::movd(Address dst, XMMRegister src) { |
duke@435 | 2540 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2541 | |
duke@435 | 2542 | InstructionMark im(this); |
duke@435 | 2543 | emit_byte(0x66); |
duke@435 | 2544 | emit_byte(0x0F); |
duke@435 | 2545 | emit_byte(0x7E); |
duke@435 | 2546 | emit_sse_operand(src, dst); |
duke@435 | 2547 | } |
duke@435 | 2548 | |
duke@435 | 2549 | void Assembler::movd(Register dst, XMMRegister src) { |
duke@435 | 2550 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2551 | |
duke@435 | 2552 | emit_byte(0x66); |
duke@435 | 2553 | emit_byte(0x0F); |
duke@435 | 2554 | emit_byte(0x7E); |
duke@435 | 2555 | emit_sse_operand(src, dst); |
duke@435 | 2556 | } |
duke@435 | 2557 | |
duke@435 | 2558 | void Assembler::movdqa(Address dst, XMMRegister src) { |
duke@435 | 2559 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2560 | |
duke@435 | 2561 | InstructionMark im(this); |
duke@435 | 2562 | emit_byte(0x66); |
duke@435 | 2563 | emit_byte(0x0F); |
duke@435 | 2564 | emit_byte(0x7F); |
duke@435 | 2565 | emit_sse_operand(src, dst); |
duke@435 | 2566 | } |
duke@435 | 2567 | |
duke@435 | 2568 | void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
duke@435 | 2569 | assert(isByte(mode), "invalid value"); |
duke@435 | 2570 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2571 | |
duke@435 | 2572 | emit_byte(0x66); |
duke@435 | 2573 | emit_byte(0x0F); |
duke@435 | 2574 | emit_byte(0x70); |
duke@435 | 2575 | emit_sse_operand(dst, src); |
duke@435 | 2576 | emit_byte(mode & 0xFF); |
duke@435 | 2577 | } |
duke@435 | 2578 | |
duke@435 | 2579 | void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
duke@435 | 2580 | assert(isByte(mode), "invalid value"); |
duke@435 | 2581 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2582 | |
duke@435 | 2583 | InstructionMark im(this); |
duke@435 | 2584 | emit_byte(0x66); |
duke@435 | 2585 | emit_byte(0x0F); |
duke@435 | 2586 | emit_byte(0x70); |
duke@435 | 2587 | emit_sse_operand(dst, src); |
duke@435 | 2588 | emit_byte(mode & 0xFF); |
duke@435 | 2589 | } |
duke@435 | 2590 | |
duke@435 | 2591 | void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
duke@435 | 2592 | assert(isByte(mode), "invalid value"); |
duke@435 | 2593 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2594 | |
duke@435 | 2595 | emit_byte(0xF2); |
duke@435 | 2596 | emit_byte(0x0F); |
duke@435 | 2597 | emit_byte(0x70); |
duke@435 | 2598 | emit_sse_operand(dst, src); |
duke@435 | 2599 | emit_byte(mode & 0xFF); |
duke@435 | 2600 | } |
duke@435 | 2601 | |
duke@435 | 2602 | void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
duke@435 | 2603 | assert(isByte(mode), "invalid value"); |
duke@435 | 2604 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2605 | |
duke@435 | 2606 | InstructionMark im(this); |
duke@435 | 2607 | emit_byte(0xF2); |
duke@435 | 2608 | emit_byte(0x0F); |
duke@435 | 2609 | emit_byte(0x70); |
duke@435 | 2610 | emit_sse_operand(dst, src); |
duke@435 | 2611 | emit_byte(mode & 0xFF); |
duke@435 | 2612 | } |
duke@435 | 2613 | |
duke@435 | 2614 | void Assembler::psrlq(XMMRegister dst, int shift) { |
duke@435 | 2615 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2616 | |
duke@435 | 2617 | emit_byte(0x66); |
duke@435 | 2618 | emit_byte(0x0F); |
duke@435 | 2619 | emit_byte(0x73); |
duke@435 | 2620 | emit_sse_operand(xmm2, dst); |
duke@435 | 2621 | emit_byte(shift); |
duke@435 | 2622 | } |
duke@435 | 2623 | |
duke@435 | 2624 | void Assembler::movss( Address dst, XMMRegister src ) { |
duke@435 | 2625 | assert(VM_Version::supports_sse(), ""); |
duke@435 | 2626 | |
duke@435 | 2627 | InstructionMark im(this); |
duke@435 | 2628 | emit_byte(0xF3); // single |
duke@435 | 2629 | emit_byte(0x0F); |
duke@435 | 2630 | emit_byte(0x11); // store |
duke@435 | 2631 | emit_sse_operand(src, dst); |
duke@435 | 2632 | } |
duke@435 | 2633 | |
duke@435 | 2634 | void Assembler::movsd( Address dst, XMMRegister src ) { |
duke@435 | 2635 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2636 | |
duke@435 | 2637 | InstructionMark im(this); |
duke@435 | 2638 | emit_byte(0xF2); // double |
duke@435 | 2639 | emit_byte(0x0F); |
duke@435 | 2640 | emit_byte(0x11); // store |
duke@435 | 2641 | emit_sse_operand(src,dst); |
duke@435 | 2642 | } |
duke@435 | 2643 | |
duke@435 | 2644 | // New cpus require to use movaps and movapd to avoid partial register stall |
duke@435 | 2645 | // when moving between registers. |
duke@435 | 2646 | void Assembler::movaps(XMMRegister dst, XMMRegister src) { |
duke@435 | 2647 | assert(VM_Version::supports_sse(), ""); |
duke@435 | 2648 | |
duke@435 | 2649 | emit_byte(0x0F); |
duke@435 | 2650 | emit_byte(0x28); |
duke@435 | 2651 | emit_sse_operand(dst, src); |
duke@435 | 2652 | } |
duke@435 | 2653 | void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
duke@435 | 2654 | assert(VM_Version::supports_sse2(), ""); |
duke@435 | 2655 | |
duke@435 | 2656 | emit_byte(0x66); |
duke@435 | 2657 | emit_byte(0x0F); |
duke@435 | 2658 | emit_byte(0x28); |
duke@435 | 2659 | emit_sse_operand(dst, src); |
duke@435 | 2660 | } |
duke@435 | 2661 | |
duke@435 | 2662 | // New cpus require to use movsd and movss to avoid partial register stall |
duke@435 | 2663 | // when loading from memory. But for old Opteron use movlpd instead of movsd. |
duke@435 | 2664 | // The selection is done in MacroAssembler::movdbl() and movflt(). |
duke@435 | 2665 | void Assembler::movlpd(XMMRegister dst, Address src) { |
duke@435 | 2666 | assert(VM_Version::supports_sse(), ""); |
duke@435 | 2667 | |
duke@435 | 2668 | InstructionMark im(this); |
duke@435 | 2669 | emit_byte(0x66); |
duke@435 | 2670 | emit_byte(0x0F); |
duke@435 | 2671 | emit_byte(0x12); |
duke@435 | 2672 | emit_sse_operand(dst, src); |
duke@435 | 2673 | } |
duke@435 | 2674 | |
kvn@506 | 2675 | void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
kvn@506 | 2676 | assert(VM_Version::supports_sse2(), ""); |
kvn@506 | 2677 | |
kvn@506 | 2678 | emit_byte(0xF3); |
kvn@506 | 2679 | emit_byte(0x0F); |
kvn@506 | 2680 | emit_byte(0xE6); |
kvn@506 | 2681 | emit_sse_operand(dst, src); |
kvn@506 | 2682 | } |
kvn@506 | 2683 | |
kvn@506 | 2684 | void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
kvn@506 | 2685 | assert(VM_Version::supports_sse2(), ""); |
kvn@506 | 2686 | |
kvn@506 | 2687 | emit_byte(0x0F); |
kvn@506 | 2688 | emit_byte(0x5B); |
kvn@506 | 2689 | emit_sse_operand(dst, src); |
kvn@506 | 2690 | } |
duke@435 | 2691 | |
duke@435 | 2692 | emit_sse_instruction(andps, sse, 0, 0x54, XMMRegister, XMMRegister); |
duke@435 | 2693 | emit_sse_instruction(andpd, sse2, 0x66, 0x54, XMMRegister, XMMRegister); |
duke@435 | 2694 | emit_sse_instruction(andnps, sse, 0, 0x55, XMMRegister, XMMRegister); |
duke@435 | 2695 | emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister); |
duke@435 | 2696 | emit_sse_instruction(orps, sse, 0, 0x56, XMMRegister, XMMRegister); |
duke@435 | 2697 | emit_sse_instruction(orpd, sse2, 0x66, 0x56, XMMRegister, XMMRegister); |
duke@435 | 2698 | emit_sse_instruction(xorps, sse, 0, 0x57, XMMRegister, XMMRegister); |
duke@435 | 2699 | emit_sse_instruction(xorpd, sse2, 0x66, 0x57, XMMRegister, XMMRegister); |
duke@435 | 2700 | |
duke@435 | 2701 | |
duke@435 | 2702 | void Assembler::ldmxcsr( Address src) { |
duke@435 | 2703 | InstructionMark im(this); |
duke@435 | 2704 | emit_byte(0x0F); |
duke@435 | 2705 | emit_byte(0xAE); |
duke@435 | 2706 | emit_operand(rdx /* 2 */, src); |
duke@435 | 2707 | } |
duke@435 | 2708 | |
duke@435 | 2709 | void Assembler::stmxcsr( Address dst) { |
duke@435 | 2710 | InstructionMark im(this); |
duke@435 | 2711 | emit_byte(0x0F); |
duke@435 | 2712 | emit_byte(0xAE); |
duke@435 | 2713 | emit_operand(rbx /* 3 */, dst); |
duke@435 | 2714 | } |
duke@435 | 2715 | |
duke@435 | 2716 | // Implementation of MacroAssembler |
duke@435 | 2717 | |
duke@435 | 2718 | Address MacroAssembler::as_Address(AddressLiteral adr) { |
duke@435 | 2719 | // amd64 always does this as a pc-rel |
duke@435 | 2720 | // we can be absolute or disp based on the instruction type |
duke@435 | 2721 | // jmp/call are displacements others are absolute |
duke@435 | 2722 | assert(!adr.is_lval(), "must be rval"); |
duke@435 | 2723 | |
duke@435 | 2724 | return Address(adr.target(), adr.rspec()); |
duke@435 | 2725 | } |
duke@435 | 2726 | |
duke@435 | 2727 | Address MacroAssembler::as_Address(ArrayAddress adr) { |
duke@435 | 2728 | return Address::make_array(adr); |
duke@435 | 2729 | } |
duke@435 | 2730 | |
duke@435 | 2731 | void MacroAssembler::fat_nop() { |
duke@435 | 2732 | // A 5 byte nop that is safe for patching (see patch_verified_entry) |
duke@435 | 2733 | emit_byte(0x26); // es: |
duke@435 | 2734 | emit_byte(0x2e); // cs: |
duke@435 | 2735 | emit_byte(0x64); // fs: |
duke@435 | 2736 | emit_byte(0x65); // gs: |
duke@435 | 2737 | emit_byte(0x90); |
duke@435 | 2738 | } |
duke@435 | 2739 | |
duke@435 | 2740 | // 32bit can do a case table jump in one instruction but we no longer allow the base |
duke@435 | 2741 | // to be installed in the Address class |
duke@435 | 2742 | void MacroAssembler::jump(ArrayAddress entry) { |
duke@435 | 2743 | jmp(as_Address(entry)); |
duke@435 | 2744 | } |
duke@435 | 2745 | |
duke@435 | 2746 | void MacroAssembler::jump(AddressLiteral dst) { |
duke@435 | 2747 | jmp_literal(dst.target(), dst.rspec()); |
duke@435 | 2748 | } |
duke@435 | 2749 | |
duke@435 | 2750 | void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { |
duke@435 | 2751 | assert((0 <= cc) && (cc < 16), "illegal cc"); |
duke@435 | 2752 | |
duke@435 | 2753 | InstructionMark im(this); |
duke@435 | 2754 | |
duke@435 | 2755 | relocInfo::relocType rtype = dst.reloc(); |
duke@435 | 2756 | relocate(rtype); |
duke@435 | 2757 | const int short_size = 2; |
duke@435 | 2758 | const int long_size = 6; |
duke@435 | 2759 | int offs = (int)dst.target() - ((int)_code_pos); |
duke@435 | 2760 | if (rtype == relocInfo::none && is8bit(offs - short_size)) { |
duke@435 | 2761 | // 0111 tttn #8-bit disp |
duke@435 | 2762 | emit_byte(0x70 | cc); |
duke@435 | 2763 | emit_byte((offs - short_size) & 0xFF); |
duke@435 | 2764 | } else { |
duke@435 | 2765 | // 0000 1111 1000 tttn #32-bit disp |
duke@435 | 2766 | emit_byte(0x0F); |
duke@435 | 2767 | emit_byte(0x80 | cc); |
duke@435 | 2768 | emit_long(offs - long_size); |
duke@435 | 2769 | } |
duke@435 | 2770 | } |
duke@435 | 2771 | |
duke@435 | 2772 | // Calls |
duke@435 | 2773 | void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { |
duke@435 | 2774 | Assembler::call(L, rtype); |
duke@435 | 2775 | } |
duke@435 | 2776 | |
duke@435 | 2777 | void MacroAssembler::call(Register entry) { |
duke@435 | 2778 | Assembler::call(entry); |
duke@435 | 2779 | } |
duke@435 | 2780 | |
duke@435 | 2781 | void MacroAssembler::call(AddressLiteral entry) { |
duke@435 | 2782 | Assembler::call_literal(entry.target(), entry.rspec()); |
duke@435 | 2783 | } |
duke@435 | 2784 | |
duke@435 | 2785 | |
duke@435 | 2786 | void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) { |
duke@435 | 2787 | Assembler::cmpb(as_Address(src1), imm); |
duke@435 | 2788 | } |
duke@435 | 2789 | |
duke@435 | 2790 | void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { |
duke@435 | 2791 | Assembler::cmpl(as_Address(src1), imm); |
duke@435 | 2792 | } |
duke@435 | 2793 | |
duke@435 | 2794 | void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { |
duke@435 | 2795 | if (src2.is_lval()) { |
duke@435 | 2796 | cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); |
duke@435 | 2797 | } else { |
duke@435 | 2798 | Assembler::cmpl(src1, as_Address(src2)); |
duke@435 | 2799 | } |
duke@435 | 2800 | } |
duke@435 | 2801 | |
duke@435 | 2802 | void MacroAssembler::cmp32(Register src1, int32_t imm) { |
duke@435 | 2803 | Assembler::cmpl(src1, imm); |
duke@435 | 2804 | } |
duke@435 | 2805 | |
duke@435 | 2806 | void MacroAssembler::cmp32(Register src1, Address src2) { |
duke@435 | 2807 | Assembler::cmpl(src1, src2); |
duke@435 | 2808 | } |
duke@435 | 2809 | |
duke@435 | 2810 | void MacroAssembler::cmpoop(Address src1, jobject obj) { |
duke@435 | 2811 | cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); |
duke@435 | 2812 | } |
duke@435 | 2813 | |
duke@435 | 2814 | void MacroAssembler::cmpoop(Register src1, jobject obj) { |
duke@435 | 2815 | cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); |
duke@435 | 2816 | } |
duke@435 | 2817 | |
duke@435 | 2818 | void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { |
duke@435 | 2819 | if (src2.is_lval()) { |
duke@435 | 2820 | // compare the effect address of src2 to src1 |
duke@435 | 2821 | cmp_literal32(src1, (int32_t)src2.target(), src2.rspec()); |
duke@435 | 2822 | } else { |
duke@435 | 2823 | Assembler::cmpl(src1, as_Address(src2)); |
duke@435 | 2824 | } |
duke@435 | 2825 | } |
duke@435 | 2826 | |
duke@435 | 2827 | void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { |
duke@435 | 2828 | assert(src2.is_lval(), "not a mem-mem compare"); |
duke@435 | 2829 | cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); |
duke@435 | 2830 | } |
duke@435 | 2831 | |
duke@435 | 2832 | |
duke@435 | 2833 | void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) { |
duke@435 | 2834 | cmpxchg(reg, as_Address(adr)); |
duke@435 | 2835 | } |
duke@435 | 2836 | |
duke@435 | 2837 | void MacroAssembler::increment(AddressLiteral dst) { |
duke@435 | 2838 | increment(as_Address(dst)); |
duke@435 | 2839 | } |
duke@435 | 2840 | |
duke@435 | 2841 | void MacroAssembler::increment(ArrayAddress dst) { |
duke@435 | 2842 | increment(as_Address(dst)); |
duke@435 | 2843 | } |
duke@435 | 2844 | |
duke@435 | 2845 | void MacroAssembler::lea(Register dst, AddressLiteral adr) { |
duke@435 | 2846 | // leal(dst, as_Address(adr)); |
duke@435 | 2847 | // see note in movl as to why we musr use a move |
duke@435 | 2848 | mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
duke@435 | 2849 | } |
duke@435 | 2850 | |
duke@435 | 2851 | void MacroAssembler::lea(Address dst, AddressLiteral adr) { |
duke@435 | 2852 | // leal(dst, as_Address(adr)); |
duke@435 | 2853 | // see note in movl as to why we musr use a move |
duke@435 | 2854 | mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
duke@435 | 2855 | } |
duke@435 | 2856 | |
duke@435 | 2857 | void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
duke@435 | 2858 | Assembler::movl(as_Address(dst), src); |
duke@435 | 2859 | } |
duke@435 | 2860 | |
duke@435 | 2861 | void MacroAssembler::mov32(Register dst, AddressLiteral src) { |
duke@435 | 2862 | Assembler::movl(dst, as_Address(src)); |
duke@435 | 2863 | } |
duke@435 | 2864 | |
duke@435 | 2865 | void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
duke@435 | 2866 | movb(as_Address(dst), src); |
duke@435 | 2867 | } |
duke@435 | 2868 | |
duke@435 | 2869 | void MacroAssembler::movoop(Address dst, jobject obj) { |
duke@435 | 2870 | mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); |
duke@435 | 2871 | } |
duke@435 | 2872 | |
duke@435 | 2873 | void MacroAssembler::movoop(Register dst, jobject obj) { |
duke@435 | 2874 | mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); |
duke@435 | 2875 | } |
duke@435 | 2876 | |
duke@435 | 2877 | void MacroAssembler::movptr(Register dst, AddressLiteral src) { |
duke@435 | 2878 | if (src.is_lval()) { |
duke@435 | 2879 | // essentially an lea |
duke@435 | 2880 | mov_literal32(dst, (int32_t) src.target(), src.rspec()); |
duke@435 | 2881 | } else { |
duke@435 | 2882 | // mov 32bits from an absolute address |
duke@435 | 2883 | movl(dst, as_Address(src)); |
duke@435 | 2884 | } |
duke@435 | 2885 | } |
duke@435 | 2886 | |
duke@435 | 2887 | void MacroAssembler::movptr(ArrayAddress dst, Register src) { |
duke@435 | 2888 | movl(as_Address(dst), src); |
duke@435 | 2889 | } |
duke@435 | 2890 | |
duke@435 | 2891 | void MacroAssembler::movptr(Register dst, ArrayAddress src) { |
duke@435 | 2892 | movl(dst, as_Address(src)); |
duke@435 | 2893 | } |
duke@435 | 2894 | |
duke@435 | 2895 | void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2896 | movss(dst, as_Address(src)); |
duke@435 | 2897 | } |
duke@435 | 2898 | |
duke@435 | 2899 | void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2900 | if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; } |
duke@435 | 2901 | else { movlpd(dst, as_Address(src)); return; } |
duke@435 | 2902 | } |
duke@435 | 2903 | |
duke@435 | 2904 | void Assembler::pushoop(jobject obj) { |
duke@435 | 2905 | push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); |
duke@435 | 2906 | } |
duke@435 | 2907 | |
duke@435 | 2908 | |
duke@435 | 2909 | void MacroAssembler::pushptr(AddressLiteral src) { |
duke@435 | 2910 | if (src.is_lval()) { |
duke@435 | 2911 | push_literal32((int32_t)src.target(), src.rspec()); |
duke@435 | 2912 | } else { |
duke@435 | 2913 | pushl(as_Address(src)); |
duke@435 | 2914 | } |
duke@435 | 2915 | } |
duke@435 | 2916 | |
duke@435 | 2917 | void MacroAssembler::test32(Register src1, AddressLiteral src2) { |
duke@435 | 2918 | // src2 must be rval |
duke@435 | 2919 | testl(src1, as_Address(src2)); |
duke@435 | 2920 | } |
duke@435 | 2921 | |
duke@435 | 2922 | // FPU |
duke@435 | 2923 | |
duke@435 | 2924 | void MacroAssembler::fld_x(AddressLiteral src) { |
duke@435 | 2925 | Assembler::fld_x(as_Address(src)); |
duke@435 | 2926 | } |
duke@435 | 2927 | |
duke@435 | 2928 | void MacroAssembler::fld_d(AddressLiteral src) { |
duke@435 | 2929 | fld_d(as_Address(src)); |
duke@435 | 2930 | } |
duke@435 | 2931 | |
duke@435 | 2932 | void MacroAssembler::fld_s(AddressLiteral src) { |
duke@435 | 2933 | fld_s(as_Address(src)); |
duke@435 | 2934 | } |
duke@435 | 2935 | |
duke@435 | 2936 | void MacroAssembler::fldcw(AddressLiteral src) { |
duke@435 | 2937 | Assembler::fldcw(as_Address(src)); |
duke@435 | 2938 | } |
duke@435 | 2939 | |
duke@435 | 2940 | void MacroAssembler::ldmxcsr(AddressLiteral src) { |
duke@435 | 2941 | Assembler::ldmxcsr(as_Address(src)); |
duke@435 | 2942 | } |
duke@435 | 2943 | |
duke@435 | 2944 | // SSE |
duke@435 | 2945 | |
duke@435 | 2946 | void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2947 | andpd(dst, as_Address(src)); |
duke@435 | 2948 | } |
duke@435 | 2949 | |
duke@435 | 2950 | void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2951 | comisd(dst, as_Address(src)); |
duke@435 | 2952 | } |
duke@435 | 2953 | |
duke@435 | 2954 | void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2955 | comiss(dst, as_Address(src)); |
duke@435 | 2956 | } |
duke@435 | 2957 | |
duke@435 | 2958 | void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2959 | movsd(dst, as_Address(src)); |
duke@435 | 2960 | } |
duke@435 | 2961 | |
duke@435 | 2962 | void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2963 | movss(dst, as_Address(src)); |
duke@435 | 2964 | } |
duke@435 | 2965 | |
duke@435 | 2966 | void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2967 | xorpd(dst, as_Address(src)); |
duke@435 | 2968 | } |
duke@435 | 2969 | |
duke@435 | 2970 | void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2971 | xorps(dst, as_Address(src)); |
duke@435 | 2972 | } |
duke@435 | 2973 | |
duke@435 | 2974 | void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2975 | ucomisd(dst, as_Address(src)); |
duke@435 | 2976 | } |
duke@435 | 2977 | |
duke@435 | 2978 | void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { |
duke@435 | 2979 | ucomiss(dst, as_Address(src)); |
duke@435 | 2980 | } |
duke@435 | 2981 | |
duke@435 | 2982 | void MacroAssembler::null_check(Register reg, int offset) { |
duke@435 | 2983 | if (needs_explicit_null_check(offset)) { |
duke@435 | 2984 | // provoke OS NULL exception if reg = NULL by |
duke@435 | 2985 | // accessing M[reg] w/o changing any (non-CC) registers |
duke@435 | 2986 | cmpl(rax, Address(reg, 0)); |
duke@435 | 2987 | // Note: should probably use testl(rax, Address(reg, 0)); |
duke@435 | 2988 | // may be shorter code (however, this version of |
duke@435 | 2989 | // testl needs to be implemented first) |
duke@435 | 2990 | } else { |
duke@435 | 2991 | // nothing to do, (later) access of M[reg + offset] |
duke@435 | 2992 | // will provoke OS NULL exception if reg = NULL |
duke@435 | 2993 | } |
duke@435 | 2994 | } |
duke@435 | 2995 | |
duke@435 | 2996 | |
duke@435 | 2997 | int MacroAssembler::load_unsigned_byte(Register dst, Address src) { |
duke@435 | 2998 | // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
duke@435 | 2999 | // and "3.9 Partial Register Penalties", p. 22). |
duke@435 | 3000 | int off; |
duke@435 | 3001 | if (VM_Version::is_P6() || src.uses(dst)) { |
duke@435 | 3002 | off = offset(); |
duke@435 | 3003 | movzxb(dst, src); |
duke@435 | 3004 | } else { |
duke@435 | 3005 | xorl(dst, dst); |
duke@435 | 3006 | off = offset(); |
duke@435 | 3007 | movb(dst, src); |
duke@435 | 3008 | } |
duke@435 | 3009 | return off; |
duke@435 | 3010 | } |
duke@435 | 3011 | |
duke@435 | 3012 | |
duke@435 | 3013 | int MacroAssembler::load_unsigned_word(Register dst, Address src) { |
duke@435 | 3014 | // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
duke@435 | 3015 | // and "3.9 Partial Register Penalties", p. 22). |
duke@435 | 3016 | int off; |
duke@435 | 3017 | if (VM_Version::is_P6() || src.uses(dst)) { |
duke@435 | 3018 | off = offset(); |
duke@435 | 3019 | movzxw(dst, src); |
duke@435 | 3020 | } else { |
duke@435 | 3021 | xorl(dst, dst); |
duke@435 | 3022 | off = offset(); |
duke@435 | 3023 | movw(dst, src); |
duke@435 | 3024 | } |
duke@435 | 3025 | return off; |
duke@435 | 3026 | } |
duke@435 | 3027 | |
duke@435 | 3028 | |
duke@435 | 3029 | int MacroAssembler::load_signed_byte(Register dst, Address src) { |
duke@435 | 3030 | int off; |
duke@435 | 3031 | if (VM_Version::is_P6()) { |
duke@435 | 3032 | off = offset(); |
duke@435 | 3033 | movsxb(dst, src); |
duke@435 | 3034 | } else { |
duke@435 | 3035 | off = load_unsigned_byte(dst, src); |
duke@435 | 3036 | shll(dst, 24); |
duke@435 | 3037 | sarl(dst, 24); |
duke@435 | 3038 | } |
duke@435 | 3039 | return off; |
duke@435 | 3040 | } |
duke@435 | 3041 | |
duke@435 | 3042 | |
duke@435 | 3043 | int MacroAssembler::load_signed_word(Register dst, Address src) { |
duke@435 | 3044 | int off; |
duke@435 | 3045 | if (VM_Version::is_P6()) { |
duke@435 | 3046 | off = offset(); |
duke@435 | 3047 | movsxw(dst, src); |
duke@435 | 3048 | } else { |
duke@435 | 3049 | off = load_unsigned_word(dst, src); |
duke@435 | 3050 | shll(dst, 16); |
duke@435 | 3051 | sarl(dst, 16); |
duke@435 | 3052 | } |
duke@435 | 3053 | return off; |
duke@435 | 3054 | } |
duke@435 | 3055 | |
duke@435 | 3056 | |
duke@435 | 3057 | void MacroAssembler::extend_sign(Register hi, Register lo) { |
duke@435 | 3058 | // According to Intel Doc. AP-526, "Integer Divide", p.18. |
duke@435 | 3059 | if (VM_Version::is_P6() && hi == rdx && lo == rax) { |
duke@435 | 3060 | cdql(); |
duke@435 | 3061 | } else { |
duke@435 | 3062 | movl(hi, lo); |
duke@435 | 3063 | sarl(hi, 31); |
duke@435 | 3064 | } |
duke@435 | 3065 | } |
duke@435 | 3066 | |
duke@435 | 3067 | |
duke@435 | 3068 | void MacroAssembler::increment(Register reg, int value) { |
duke@435 | 3069 | if (value == min_jint) {addl(reg, value); return; } |
duke@435 | 3070 | if (value < 0) { decrement(reg, -value); return; } |
duke@435 | 3071 | if (value == 0) { ; return; } |
duke@435 | 3072 | if (value == 1 && UseIncDec) { incl(reg); return; } |
duke@435 | 3073 | /* else */ { addl(reg, value) ; return; } |
duke@435 | 3074 | } |
duke@435 | 3075 | |
duke@435 | 3076 | void MacroAssembler::increment(Address dst, int value) { |
duke@435 | 3077 | if (value == min_jint) {addl(dst, value); return; } |
duke@435 | 3078 | if (value < 0) { decrement(dst, -value); return; } |
duke@435 | 3079 | if (value == 0) { ; return; } |
duke@435 | 3080 | if (value == 1 && UseIncDec) { incl(dst); return; } |
duke@435 | 3081 | /* else */ { addl(dst, value) ; return; } |
duke@435 | 3082 | } |
duke@435 | 3083 | |
duke@435 | 3084 | void MacroAssembler::decrement(Register reg, int value) { |
duke@435 | 3085 | if (value == min_jint) {subl(reg, value); return; } |
duke@435 | 3086 | if (value < 0) { increment(reg, -value); return; } |
duke@435 | 3087 | if (value == 0) { ; return; } |
duke@435 | 3088 | if (value == 1 && UseIncDec) { decl(reg); return; } |
duke@435 | 3089 | /* else */ { subl(reg, value) ; return; } |
duke@435 | 3090 | } |
duke@435 | 3091 | |
duke@435 | 3092 | void MacroAssembler::decrement(Address dst, int value) { |
duke@435 | 3093 | if (value == min_jint) {subl(dst, value); return; } |
duke@435 | 3094 | if (value < 0) { increment(dst, -value); return; } |
duke@435 | 3095 | if (value == 0) { ; return; } |
duke@435 | 3096 | if (value == 1 && UseIncDec) { decl(dst); return; } |
duke@435 | 3097 | /* else */ { subl(dst, value) ; return; } |
duke@435 | 3098 | } |
duke@435 | 3099 | |
duke@435 | 3100 | void MacroAssembler::align(int modulus) { |
duke@435 | 3101 | if (offset() % modulus != 0) nop(modulus - (offset() % modulus)); |
duke@435 | 3102 | } |
duke@435 | 3103 | |
duke@435 | 3104 | |
duke@435 | 3105 | void MacroAssembler::enter() { |
duke@435 | 3106 | pushl(rbp); |
duke@435 | 3107 | movl(rbp, rsp); |
duke@435 | 3108 | } |
duke@435 | 3109 | |
duke@435 | 3110 | |
duke@435 | 3111 | void MacroAssembler::leave() { |
duke@435 | 3112 | movl(rsp, rbp); |
duke@435 | 3113 | popl(rbp); |
duke@435 | 3114 | } |
duke@435 | 3115 | |
duke@435 | 3116 | void MacroAssembler::set_last_Java_frame(Register java_thread, |
duke@435 | 3117 | Register last_java_sp, |
duke@435 | 3118 | Register last_java_fp, |
duke@435 | 3119 | address last_java_pc) { |
duke@435 | 3120 | // determine java_thread register |
duke@435 | 3121 | if (!java_thread->is_valid()) { |
duke@435 | 3122 | java_thread = rdi; |
duke@435 | 3123 | get_thread(java_thread); |
duke@435 | 3124 | } |
duke@435 | 3125 | // determine last_java_sp register |
duke@435 | 3126 | if (!last_java_sp->is_valid()) { |
duke@435 | 3127 | last_java_sp = rsp; |
duke@435 | 3128 | } |
duke@435 | 3129 | |
duke@435 | 3130 | // last_java_fp is optional |
duke@435 | 3131 | |
duke@435 | 3132 | if (last_java_fp->is_valid()) { |
duke@435 | 3133 | movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); |
duke@435 | 3134 | } |
duke@435 | 3135 | |
duke@435 | 3136 | // last_java_pc is optional |
duke@435 | 3137 | |
duke@435 | 3138 | if (last_java_pc != NULL) { |
duke@435 | 3139 | lea(Address(java_thread, |
duke@435 | 3140 | JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), |
duke@435 | 3141 | InternalAddress(last_java_pc)); |
duke@435 | 3142 | |
duke@435 | 3143 | } |
duke@435 | 3144 | movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); |
duke@435 | 3145 | } |
duke@435 | 3146 | |
duke@435 | 3147 | void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { |
duke@435 | 3148 | // determine java_thread register |
duke@435 | 3149 | if (!java_thread->is_valid()) { |
duke@435 | 3150 | java_thread = rdi; |
duke@435 | 3151 | get_thread(java_thread); |
duke@435 | 3152 | } |
duke@435 | 3153 | // we must set sp to zero to clear frame |
duke@435 | 3154 | movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0); |
duke@435 | 3155 | if (clear_fp) { |
duke@435 | 3156 | movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0); |
duke@435 | 3157 | } |
duke@435 | 3158 | |
duke@435 | 3159 | if (clear_pc) |
duke@435 | 3160 | movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0); |
duke@435 | 3161 | |
duke@435 | 3162 | } |
duke@435 | 3163 | |
duke@435 | 3164 | |
duke@435 | 3165 | |
duke@435 | 3166 | // Implementation of call_VM versions |
duke@435 | 3167 | |
duke@435 | 3168 | void MacroAssembler::call_VM_leaf_base( |
duke@435 | 3169 | address entry_point, |
duke@435 | 3170 | int number_of_arguments |
duke@435 | 3171 | ) { |
duke@435 | 3172 | call(RuntimeAddress(entry_point)); |
duke@435 | 3173 | increment(rsp, number_of_arguments * wordSize); |
duke@435 | 3174 | } |
duke@435 | 3175 | |
duke@435 | 3176 | |
duke@435 | 3177 | void MacroAssembler::call_VM_base( |
duke@435 | 3178 | Register oop_result, |
duke@435 | 3179 | Register java_thread, |
duke@435 | 3180 | Register last_java_sp, |
duke@435 | 3181 | address entry_point, |
duke@435 | 3182 | int number_of_arguments, |
duke@435 | 3183 | bool check_exceptions |
duke@435 | 3184 | ) { |
duke@435 | 3185 | // determine java_thread register |
duke@435 | 3186 | if (!java_thread->is_valid()) { |
duke@435 | 3187 | java_thread = rdi; |
duke@435 | 3188 | get_thread(java_thread); |
duke@435 | 3189 | } |
duke@435 | 3190 | // determine last_java_sp register |
duke@435 | 3191 | if (!last_java_sp->is_valid()) { |
duke@435 | 3192 | last_java_sp = rsp; |
duke@435 | 3193 | } |
duke@435 | 3194 | // debugging support |
duke@435 | 3195 | assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); |
duke@435 | 3196 | assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
duke@435 | 3197 | assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); |
duke@435 | 3198 | // push java thread (becomes first argument of C function) |
duke@435 | 3199 | pushl(java_thread); |
duke@435 | 3200 | // set last Java frame before call |
duke@435 | 3201 | assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,"); |
duke@435 | 3202 | // Only interpreter should have to set fp |
duke@435 | 3203 | set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); |
duke@435 | 3204 | // do the call |
duke@435 | 3205 | call(RuntimeAddress(entry_point)); |
duke@435 | 3206 | // restore the thread (cannot use the pushed argument since arguments |
duke@435 | 3207 | // may be overwritten by C code generated by an optimizing compiler); |
duke@435 | 3208 | // however can use the register value directly if it is callee saved. |
duke@435 | 3209 | if (java_thread == rdi || java_thread == rsi) { |
duke@435 | 3210 | // rdi & rsi are callee saved -> nothing to do |
duke@435 | 3211 | #ifdef ASSERT |
duke@435 | 3212 | guarantee(java_thread != rax, "change this code"); |
duke@435 | 3213 | pushl(rax); |
duke@435 | 3214 | { Label L; |
duke@435 | 3215 | get_thread(rax); |
duke@435 | 3216 | cmpl(java_thread, rax); |
duke@435 | 3217 | jcc(Assembler::equal, L); |
duke@435 | 3218 | stop("MacroAssembler::call_VM_base: rdi not callee saved?"); |
duke@435 | 3219 | bind(L); |
duke@435 | 3220 | } |
duke@435 | 3221 | popl(rax); |
duke@435 | 3222 | #endif |
duke@435 | 3223 | } else { |
duke@435 | 3224 | get_thread(java_thread); |
duke@435 | 3225 | } |
duke@435 | 3226 | // reset last Java frame |
duke@435 | 3227 | // Only interpreter should have to clear fp |
duke@435 | 3228 | reset_last_Java_frame(java_thread, true, false); |
duke@435 | 3229 | // discard thread and arguments |
duke@435 | 3230 | addl(rsp, (1 + number_of_arguments)*wordSize); |
duke@435 | 3231 | |
duke@435 | 3232 | #ifndef CC_INTERP |
duke@435 | 3233 | // C++ interp handles this in the interpreter |
duke@435 | 3234 | check_and_handle_popframe(java_thread); |
duke@435 | 3235 | check_and_handle_earlyret(java_thread); |
duke@435 | 3236 | #endif /* CC_INTERP */ |
duke@435 | 3237 | |
duke@435 | 3238 | if (check_exceptions) { |
duke@435 | 3239 | // check for pending exceptions (java_thread is set upon return) |
duke@435 | 3240 | cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD); |
duke@435 | 3241 | jump_cc(Assembler::notEqual, |
duke@435 | 3242 | RuntimeAddress(StubRoutines::forward_exception_entry())); |
duke@435 | 3243 | } |
duke@435 | 3244 | |
duke@435 | 3245 | // get oop result if there is one and reset the value in the thread |
duke@435 | 3246 | if (oop_result->is_valid()) { |
duke@435 | 3247 | movl(oop_result, Address(java_thread, JavaThread::vm_result_offset())); |
duke@435 | 3248 | movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
duke@435 | 3249 | verify_oop(oop_result); |
duke@435 | 3250 | } |
duke@435 | 3251 | } |
duke@435 | 3252 | |
duke@435 | 3253 | |
duke@435 | 3254 | void MacroAssembler::check_and_handle_popframe(Register java_thread) { |
duke@435 | 3255 | } |
duke@435 | 3256 | |
duke@435 | 3257 | void MacroAssembler::check_and_handle_earlyret(Register java_thread) { |
duke@435 | 3258 | } |
duke@435 | 3259 | |
duke@435 | 3260 | void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { |
duke@435 | 3261 | leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); |
duke@435 | 3262 | call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); |
duke@435 | 3263 | } |
duke@435 | 3264 | |
duke@435 | 3265 | |
duke@435 | 3266 | void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) { |
duke@435 | 3267 | Label C, E; |
duke@435 | 3268 | call(C, relocInfo::none); |
duke@435 | 3269 | jmp(E); |
duke@435 | 3270 | |
duke@435 | 3271 | bind(C); |
duke@435 | 3272 | call_VM_helper(oop_result, entry_point, 0, check_exceptions); |
duke@435 | 3273 | ret(0); |
duke@435 | 3274 | |
duke@435 | 3275 | bind(E); |
duke@435 | 3276 | } |
duke@435 | 3277 | |
duke@435 | 3278 | |
duke@435 | 3279 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { |
duke@435 | 3280 | Label C, E; |
duke@435 | 3281 | call(C, relocInfo::none); |
duke@435 | 3282 | jmp(E); |
duke@435 | 3283 | |
duke@435 | 3284 | bind(C); |
duke@435 | 3285 | pushl(arg_1); |
duke@435 | 3286 | call_VM_helper(oop_result, entry_point, 1, check_exceptions); |
duke@435 | 3287 | ret(0); |
duke@435 | 3288 | |
duke@435 | 3289 | bind(E); |
duke@435 | 3290 | } |
duke@435 | 3291 | |
duke@435 | 3292 | |
duke@435 | 3293 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { |
duke@435 | 3294 | Label C, E; |
duke@435 | 3295 | call(C, relocInfo::none); |
duke@435 | 3296 | jmp(E); |
duke@435 | 3297 | |
duke@435 | 3298 | bind(C); |
duke@435 | 3299 | pushl(arg_2); |
duke@435 | 3300 | pushl(arg_1); |
duke@435 | 3301 | call_VM_helper(oop_result, entry_point, 2, check_exceptions); |
duke@435 | 3302 | ret(0); |
duke@435 | 3303 | |
duke@435 | 3304 | bind(E); |
duke@435 | 3305 | } |
duke@435 | 3306 | |
duke@435 | 3307 | |
duke@435 | 3308 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { |
duke@435 | 3309 | Label C, E; |
duke@435 | 3310 | call(C, relocInfo::none); |
duke@435 | 3311 | jmp(E); |
duke@435 | 3312 | |
duke@435 | 3313 | bind(C); |
duke@435 | 3314 | pushl(arg_3); |
duke@435 | 3315 | pushl(arg_2); |
duke@435 | 3316 | pushl(arg_1); |
duke@435 | 3317 | call_VM_helper(oop_result, entry_point, 3, check_exceptions); |
duke@435 | 3318 | ret(0); |
duke@435 | 3319 | |
duke@435 | 3320 | bind(E); |
duke@435 | 3321 | } |
duke@435 | 3322 | |
duke@435 | 3323 | |
duke@435 | 3324 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { |
duke@435 | 3325 | call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
duke@435 | 3326 | } |
duke@435 | 3327 | |
duke@435 | 3328 | |
duke@435 | 3329 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { |
duke@435 | 3330 | pushl(arg_1); |
duke@435 | 3331 | call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
duke@435 | 3332 | } |
duke@435 | 3333 | |
duke@435 | 3334 | |
duke@435 | 3335 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { |
duke@435 | 3336 | pushl(arg_2); |
duke@435 | 3337 | pushl(arg_1); |
duke@435 | 3338 | call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
duke@435 | 3339 | } |
duke@435 | 3340 | |
duke@435 | 3341 | |
duke@435 | 3342 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { |
duke@435 | 3343 | pushl(arg_3); |
duke@435 | 3344 | pushl(arg_2); |
duke@435 | 3345 | pushl(arg_1); |
duke@435 | 3346 | call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
duke@435 | 3347 | } |
duke@435 | 3348 | |
duke@435 | 3349 | |
duke@435 | 3350 | void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { |
duke@435 | 3351 | call_VM_leaf_base(entry_point, number_of_arguments); |
duke@435 | 3352 | } |
duke@435 | 3353 | |
duke@435 | 3354 | |
duke@435 | 3355 | void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) { |
duke@435 | 3356 | pushl(arg_1); |
duke@435 | 3357 | call_VM_leaf(entry_point, 1); |
duke@435 | 3358 | } |
duke@435 | 3359 | |
duke@435 | 3360 | |
duke@435 | 3361 | void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) { |
duke@435 | 3362 | pushl(arg_2); |
duke@435 | 3363 | pushl(arg_1); |
duke@435 | 3364 | call_VM_leaf(entry_point, 2); |
duke@435 | 3365 | } |
duke@435 | 3366 | |
duke@435 | 3367 | |
duke@435 | 3368 | void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) { |
duke@435 | 3369 | pushl(arg_3); |
duke@435 | 3370 | pushl(arg_2); |
duke@435 | 3371 | pushl(arg_1); |
duke@435 | 3372 | call_VM_leaf(entry_point, 3); |
duke@435 | 3373 | } |
duke@435 | 3374 | |
duke@435 | 3375 | // Calls to C land |
duke@435 | 3376 | // |
duke@435 | 3377 | // When entering C land, the rbp, & rsp of the last Java frame have to be recorded |
duke@435 | 3378 | // in the (thread-local) JavaThread object. When leaving C land, the last Java fp |
duke@435 | 3379 | // has to be reset to 0. This is required to allow proper stack traversal. |
duke@435 | 3380 | |
ysr@777 | 3381 | ////////////////////////////////////////////////////////////////////////////////// |
ysr@777 | 3382 | #ifndef SERIALGC |
ysr@777 | 3383 | |
ysr@777 | 3384 | void MacroAssembler::g1_write_barrier_pre(Register obj, |
ysr@777 | 3385 | Register thread, |
ysr@777 | 3386 | Register tmp, |
ysr@777 | 3387 | Register tmp2, |
ysr@777 | 3388 | bool tosca_live) { |
ysr@777 | 3389 | Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
ysr@777 | 3390 | PtrQueue::byte_offset_of_active())); |
ysr@777 | 3391 | |
ysr@777 | 3392 | Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
ysr@777 | 3393 | PtrQueue::byte_offset_of_index())); |
ysr@777 | 3394 | Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
ysr@777 | 3395 | PtrQueue::byte_offset_of_buf())); |
ysr@777 | 3396 | |
ysr@777 | 3397 | |
ysr@777 | 3398 | Label done; |
ysr@777 | 3399 | Label runtime; |
ysr@777 | 3400 | |
ysr@777 | 3401 | // if (!marking_in_progress) goto done; |
ysr@777 | 3402 | if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
ysr@777 | 3403 | cmpl(in_progress, 0); |
ysr@777 | 3404 | } else { |
ysr@777 | 3405 | assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); |
ysr@777 | 3406 | cmpb(in_progress, 0); |
ysr@777 | 3407 | } |
ysr@777 | 3408 | jcc(Assembler::equal, done); |
ysr@777 | 3409 | |
ysr@777 | 3410 | // if (x.f == NULL) goto done; |
ysr@777 | 3411 | cmpl(Address(obj, 0), NULL_WORD); |
ysr@777 | 3412 | jcc(Assembler::equal, done); |
ysr@777 | 3413 | |
ysr@777 | 3414 | // Can we store original value in the thread's buffer? |
ysr@777 | 3415 | |
ysr@777 | 3416 | movl(tmp2, Address(obj, 0)); |
ysr@777 | 3417 | cmpl(index, 0); |
ysr@777 | 3418 | jcc(Assembler::equal, runtime); |
ysr@777 | 3419 | subl(index, wordSize); |
ysr@777 | 3420 | movl(tmp, buffer); |
ysr@777 | 3421 | addl(tmp, index); |
ysr@777 | 3422 | movl(Address(tmp, 0), tmp2); |
ysr@777 | 3423 | jmp(done); |
ysr@777 | 3424 | bind(runtime); |
ysr@777 | 3425 | // save the live input values |
ysr@777 | 3426 | if(tosca_live) pushl(rax); |
ysr@777 | 3427 | pushl(obj); |
ysr@777 | 3428 | pushl(thread); |
ysr@777 | 3429 | call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); |
ysr@777 | 3430 | popl(thread); |
ysr@777 | 3431 | popl(obj); |
ysr@777 | 3432 | if(tosca_live) popl(rax); |
ysr@777 | 3433 | bind(done); |
ysr@777 | 3434 | |
ysr@777 | 3435 | } |
ysr@777 | 3436 | |
ysr@777 | 3437 | void MacroAssembler::g1_write_barrier_post(Register store_addr, |
ysr@777 | 3438 | Register new_val, |
ysr@777 | 3439 | Register thread, |
ysr@777 | 3440 | Register tmp, |
ysr@777 | 3441 | Register tmp2) { |
ysr@777 | 3442 | |
ysr@777 | 3443 | Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
ysr@777 | 3444 | PtrQueue::byte_offset_of_index())); |
ysr@777 | 3445 | Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
ysr@777 | 3446 | PtrQueue::byte_offset_of_buf())); |
ysr@777 | 3447 | BarrierSet* bs = Universe::heap()->barrier_set(); |
ysr@777 | 3448 | CardTableModRefBS* ct = (CardTableModRefBS*)bs; |
ysr@777 | 3449 | Label done; |
ysr@777 | 3450 | Label runtime; |
ysr@777 | 3451 | |
ysr@777 | 3452 | // Does store cross heap regions? |
ysr@777 | 3453 | |
ysr@777 | 3454 | movl(tmp, store_addr); // ebx = edx |
ysr@777 | 3455 | xorl(tmp, new_val); // ebx ^= eax |
ysr@777 | 3456 | shrl(tmp, HeapRegion::LogOfHRGrainBytes); // ebx <<= 9 |
ysr@777 | 3457 | jcc(Assembler::equal, done); |
ysr@777 | 3458 | |
ysr@777 | 3459 | // crosses regions, storing NULL? |
ysr@777 | 3460 | |
ysr@777 | 3461 | cmpl(new_val, NULL_WORD); |
ysr@777 | 3462 | jcc(Assembler::equal, done); |
ysr@777 | 3463 | |
ysr@777 | 3464 | // storing region crossing non-NULL, is card already dirty? |
ysr@777 | 3465 | |
ysr@777 | 3466 | const Register card_index = tmp; |
ysr@777 | 3467 | |
ysr@777 | 3468 | movl(card_index, store_addr); // ebx = edx |
ysr@777 | 3469 | shrl(card_index, CardTableModRefBS::card_shift); // ebx >>= 9 |
ysr@777 | 3470 | assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); |
ysr@777 | 3471 | |
ysr@777 | 3472 | ExternalAddress cardtable((address)ct->byte_map_base); |
ysr@777 | 3473 | Address index(noreg, card_index, Address::times_1); |
ysr@777 | 3474 | const Register card_addr = tmp; |
ysr@777 | 3475 | leal(card_addr, as_Address(ArrayAddress(cardtable, index))); |
ysr@777 | 3476 | cmpb(Address(card_addr, 0), 0); |
ysr@777 | 3477 | jcc(Assembler::equal, done); |
ysr@777 | 3478 | |
ysr@777 | 3479 | // storing a region crossing, non-NULL oop, card is clean. |
ysr@777 | 3480 | // dirty card and log. |
ysr@777 | 3481 | |
ysr@777 | 3482 | movb(Address(card_addr, 0), 0); |
ysr@777 | 3483 | |
ysr@777 | 3484 | cmpl(queue_index, 0); |
ysr@777 | 3485 | jcc(Assembler::equal, runtime); |
ysr@777 | 3486 | subl(queue_index, wordSize); |
ysr@777 | 3487 | movl(tmp2, buffer); |
ysr@777 | 3488 | addl(tmp2, queue_index); |
ysr@777 | 3489 | movl(Address(tmp2, 0), card_index); |
ysr@777 | 3490 | jmp(done); |
ysr@777 | 3491 | |
ysr@777 | 3492 | bind(runtime); |
ysr@777 | 3493 | // save the live input values |
ysr@777 | 3494 | pushl(store_addr); |
ysr@777 | 3495 | pushl(new_val); |
ysr@777 | 3496 | pushl(thread); |
ysr@777 | 3497 | call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); |
ysr@777 | 3498 | popl(thread); |
ysr@777 | 3499 | popl(new_val); |
ysr@777 | 3500 | popl(store_addr); |
ysr@777 | 3501 | |
ysr@777 | 3502 | bind(done); |
ysr@777 | 3503 | |
ysr@777 | 3504 | |
ysr@777 | 3505 | } |
ysr@777 | 3506 | |
ysr@777 | 3507 | #endif // SERIALGC |
ysr@777 | 3508 | ////////////////////////////////////////////////////////////////////////////////// |
ysr@777 | 3509 | |
ysr@777 | 3510 | |
duke@435 | 3511 | void MacroAssembler::store_check(Register obj) { |
duke@435 | 3512 | // Does a store check for the oop in register obj. The content of |
duke@435 | 3513 | // register obj is destroyed afterwards. |
duke@435 | 3514 | store_check_part_1(obj); |
duke@435 | 3515 | store_check_part_2(obj); |
duke@435 | 3516 | } |
duke@435 | 3517 | |
duke@435 | 3518 | |
duke@435 | 3519 | void MacroAssembler::store_check(Register obj, Address dst) { |
duke@435 | 3520 | store_check(obj); |
duke@435 | 3521 | } |
duke@435 | 3522 | |
duke@435 | 3523 | |
duke@435 | 3524 | // split the store check operation so that other instructions can be scheduled inbetween |
duke@435 | 3525 | void MacroAssembler::store_check_part_1(Register obj) { |
duke@435 | 3526 | BarrierSet* bs = Universe::heap()->barrier_set(); |
duke@435 | 3527 | assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); |
duke@435 | 3528 | shrl(obj, CardTableModRefBS::card_shift); |
duke@435 | 3529 | } |
duke@435 | 3530 | |
duke@435 | 3531 | |
duke@435 | 3532 | void MacroAssembler::store_check_part_2(Register obj) { |
duke@435 | 3533 | BarrierSet* bs = Universe::heap()->barrier_set(); |
duke@435 | 3534 | assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); |
duke@435 | 3535 | CardTableModRefBS* ct = (CardTableModRefBS*)bs; |
duke@435 | 3536 | assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); |
sgoldman@552 | 3537 | |
sgoldman@552 | 3538 | // The calculation for byte_map_base is as follows: |
sgoldman@552 | 3539 | // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); |
sgoldman@552 | 3540 | // So this essentially converts an address to a displacement and |
sgoldman@552 | 3541 | // it will never need to be relocated. On 64bit however the value may be too |
sgoldman@552 | 3542 | // large for a 32bit displacement |
sgoldman@552 | 3543 | |
sgoldman@552 | 3544 | intptr_t disp = (intptr_t) ct->byte_map_base; |
sgoldman@552 | 3545 | Address cardtable(noreg, obj, Address::times_1, disp); |
sgoldman@552 | 3546 | movb(cardtable, 0); |
duke@435 | 3547 | } |
duke@435 | 3548 | |
duke@435 | 3549 | |
duke@435 | 3550 | void MacroAssembler::c2bool(Register x) { |
duke@435 | 3551 | // implements x == 0 ? 0 : 1 |
duke@435 | 3552 | // note: must only look at least-significant byte of x |
duke@435 | 3553 | // since C-style booleans are stored in one byte |
duke@435 | 3554 | // only! (was bug) |
duke@435 | 3555 | andl(x, 0xFF); |
duke@435 | 3556 | setb(Assembler::notZero, x); |
duke@435 | 3557 | } |
duke@435 | 3558 | |
duke@435 | 3559 | |
duke@435 | 3560 | int MacroAssembler::corrected_idivl(Register reg) { |
duke@435 | 3561 | // Full implementation of Java idiv and irem; checks for |
duke@435 | 3562 | // special case as described in JVM spec., p.243 & p.271. |
duke@435 | 3563 | // The function returns the (pc) offset of the idivl |
duke@435 | 3564 | // instruction - may be needed for implicit exceptions. |
duke@435 | 3565 | // |
duke@435 | 3566 | // normal case special case |
duke@435 | 3567 | // |
duke@435 | 3568 | // input : rax,: dividend min_int |
duke@435 | 3569 | // reg: divisor (may not be rax,/rdx) -1 |
duke@435 | 3570 | // |
duke@435 | 3571 | // output: rax,: quotient (= rax, idiv reg) min_int |
duke@435 | 3572 | // rdx: remainder (= rax, irem reg) 0 |
duke@435 | 3573 | assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); |
duke@435 | 3574 | const int min_int = 0x80000000; |
duke@435 | 3575 | Label normal_case, special_case; |
duke@435 | 3576 | |
duke@435 | 3577 | // check for special case |
duke@435 | 3578 | cmpl(rax, min_int); |
duke@435 | 3579 | jcc(Assembler::notEqual, normal_case); |
duke@435 | 3580 | xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) |
duke@435 | 3581 | cmpl(reg, -1); |
duke@435 | 3582 | jcc(Assembler::equal, special_case); |
duke@435 | 3583 | |
duke@435 | 3584 | // handle normal case |
duke@435 | 3585 | bind(normal_case); |
duke@435 | 3586 | cdql(); |
duke@435 | 3587 | int idivl_offset = offset(); |
duke@435 | 3588 | idivl(reg); |
duke@435 | 3589 | |
duke@435 | 3590 | // normal and special case exit |
duke@435 | 3591 | bind(special_case); |
duke@435 | 3592 | |
duke@435 | 3593 | return idivl_offset; |
duke@435 | 3594 | } |
duke@435 | 3595 | |
duke@435 | 3596 | |
duke@435 | 3597 | void MacroAssembler::lneg(Register hi, Register lo) { |
duke@435 | 3598 | negl(lo); |
duke@435 | 3599 | adcl(hi, 0); |
duke@435 | 3600 | negl(hi); |
duke@435 | 3601 | } |
duke@435 | 3602 | |
duke@435 | 3603 | |
duke@435 | 3604 | void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { |
duke@435 | 3605 | // Multiplication of two Java long values stored on the stack |
duke@435 | 3606 | // as illustrated below. Result is in rdx:rax. |
duke@435 | 3607 | // |
duke@435 | 3608 | // rsp ---> [ ?? ] \ \ |
duke@435 | 3609 | // .... | y_rsp_offset | |
duke@435 | 3610 | // [ y_lo ] / (in bytes) | x_rsp_offset |
duke@435 | 3611 | // [ y_hi ] | (in bytes) |
duke@435 | 3612 | // .... | |
duke@435 | 3613 | // [ x_lo ] / |
duke@435 | 3614 | // [ x_hi ] |
duke@435 | 3615 | // .... |
duke@435 | 3616 | // |
duke@435 | 3617 | // Basic idea: lo(result) = lo(x_lo * y_lo) |
duke@435 | 3618 | // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) |
duke@435 | 3619 | Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); |
duke@435 | 3620 | Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); |
duke@435 | 3621 | Label quick; |
duke@435 | 3622 | // load x_hi, y_hi and check if quick |
duke@435 | 3623 | // multiplication is possible |
duke@435 | 3624 | movl(rbx, x_hi); |
duke@435 | 3625 | movl(rcx, y_hi); |
duke@435 | 3626 | movl(rax, rbx); |
duke@435 | 3627 | orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 |
duke@435 | 3628 | jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply |
duke@435 | 3629 | // do full multiplication |
duke@435 | 3630 | // 1st step |
duke@435 | 3631 | mull(y_lo); // x_hi * y_lo |
duke@435 | 3632 | movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, |
duke@435 | 3633 | // 2nd step |
duke@435 | 3634 | movl(rax, x_lo); |
duke@435 | 3635 | mull(rcx); // x_lo * y_hi |
duke@435 | 3636 | addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, |
duke@435 | 3637 | // 3rd step |
duke@435 | 3638 | bind(quick); // note: rbx, = 0 if quick multiply! |
duke@435 | 3639 | movl(rax, x_lo); |
duke@435 | 3640 | mull(y_lo); // x_lo * y_lo |
duke@435 | 3641 | addl(rdx, rbx); // correct hi(x_lo * y_lo) |
duke@435 | 3642 | } |
duke@435 | 3643 | |
duke@435 | 3644 | |
duke@435 | 3645 | void MacroAssembler::lshl(Register hi, Register lo) { |
duke@435 | 3646 | // Java shift left long support (semantics as described in JVM spec., p.305) |
duke@435 | 3647 | // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) |
duke@435 | 3648 | // shift value is in rcx ! |
duke@435 | 3649 | assert(hi != rcx, "must not use rcx"); |
duke@435 | 3650 | assert(lo != rcx, "must not use rcx"); |
duke@435 | 3651 | const Register s = rcx; // shift count |
duke@435 | 3652 | const int n = BitsPerWord; |
duke@435 | 3653 | Label L; |
duke@435 | 3654 | andl(s, 0x3f); // s := s & 0x3f (s < 0x40) |
duke@435 | 3655 | cmpl(s, n); // if (s < n) |
duke@435 | 3656 | jcc(Assembler::less, L); // else (s >= n) |
duke@435 | 3657 | movl(hi, lo); // x := x << n |
duke@435 | 3658 | xorl(lo, lo); |
duke@435 | 3659 | // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! |
duke@435 | 3660 | bind(L); // s (mod n) < n |
duke@435 | 3661 | shldl(hi, lo); // x := x << s |
duke@435 | 3662 | shll(lo); |
duke@435 | 3663 | } |
duke@435 | 3664 | |
duke@435 | 3665 | |
duke@435 | 3666 | void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { |
duke@435 | 3667 | // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) |
duke@435 | 3668 | // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) |
duke@435 | 3669 | assert(hi != rcx, "must not use rcx"); |
duke@435 | 3670 | assert(lo != rcx, "must not use rcx"); |
duke@435 | 3671 | const Register s = rcx; // shift count |
duke@435 | 3672 | const int n = BitsPerWord; |
duke@435 | 3673 | Label L; |
duke@435 | 3674 | andl(s, 0x3f); // s := s & 0x3f (s < 0x40) |
duke@435 | 3675 | cmpl(s, n); // if (s < n) |
duke@435 | 3676 | jcc(Assembler::less, L); // else (s >= n) |
duke@435 | 3677 | movl(lo, hi); // x := x >> n |
duke@435 | 3678 | if (sign_extension) sarl(hi, 31); |
duke@435 | 3679 | else xorl(hi, hi); |
duke@435 | 3680 | // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! |
duke@435 | 3681 | bind(L); // s (mod n) < n |
duke@435 | 3682 | shrdl(lo, hi); // x := x >> s |
duke@435 | 3683 | if (sign_extension) sarl(hi); |
duke@435 | 3684 | else shrl(hi); |
duke@435 | 3685 | } |
duke@435 | 3686 | |
duke@435 | 3687 | |
duke@435 | 3688 | // Note: y_lo will be destroyed |
duke@435 | 3689 | void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { |
duke@435 | 3690 | // Long compare for Java (semantics as described in JVM spec.) |
duke@435 | 3691 | Label high, low, done; |
duke@435 | 3692 | |
duke@435 | 3693 | cmpl(x_hi, y_hi); |
duke@435 | 3694 | jcc(Assembler::less, low); |
duke@435 | 3695 | jcc(Assembler::greater, high); |
duke@435 | 3696 | // x_hi is the return register |
duke@435 | 3697 | xorl(x_hi, x_hi); |
duke@435 | 3698 | cmpl(x_lo, y_lo); |
duke@435 | 3699 | jcc(Assembler::below, low); |
duke@435 | 3700 | jcc(Assembler::equal, done); |
duke@435 | 3701 | |
duke@435 | 3702 | bind(high); |
duke@435 | 3703 | xorl(x_hi, x_hi); |
duke@435 | 3704 | increment(x_hi); |
duke@435 | 3705 | jmp(done); |
duke@435 | 3706 | |
duke@435 | 3707 | bind(low); |
duke@435 | 3708 | xorl(x_hi, x_hi); |
duke@435 | 3709 | decrement(x_hi); |
duke@435 | 3710 | |
duke@435 | 3711 | bind(done); |
duke@435 | 3712 | } |
duke@435 | 3713 | |
duke@435 | 3714 | |
duke@435 | 3715 | void MacroAssembler::save_rax(Register tmp) { |
duke@435 | 3716 | if (tmp == noreg) pushl(rax); |
duke@435 | 3717 | else if (tmp != rax) movl(tmp, rax); |
duke@435 | 3718 | } |
duke@435 | 3719 | |
duke@435 | 3720 | |
duke@435 | 3721 | void MacroAssembler::restore_rax(Register tmp) { |
duke@435 | 3722 | if (tmp == noreg) popl(rax); |
duke@435 | 3723 | else if (tmp != rax) movl(rax, tmp); |
duke@435 | 3724 | } |
duke@435 | 3725 | |
duke@435 | 3726 | |
duke@435 | 3727 | void MacroAssembler::fremr(Register tmp) { |
duke@435 | 3728 | save_rax(tmp); |
duke@435 | 3729 | { Label L; |
duke@435 | 3730 | bind(L); |
duke@435 | 3731 | fprem(); |
duke@435 | 3732 | fwait(); fnstsw_ax(); |
duke@435 | 3733 | sahf(); |
duke@435 | 3734 | jcc(Assembler::parity, L); |
duke@435 | 3735 | } |
duke@435 | 3736 | restore_rax(tmp); |
duke@435 | 3737 | // Result is in ST0. |
duke@435 | 3738 | // Note: fxch & fpop to get rid of ST1 |
duke@435 | 3739 | // (otherwise FPU stack could overflow eventually) |
duke@435 | 3740 | fxch(1); |
duke@435 | 3741 | fpop(); |
duke@435 | 3742 | } |
duke@435 | 3743 | |
duke@435 | 3744 | |
duke@435 | 3745 | static const double pi_4 = 0.7853981633974483; |
duke@435 | 3746 | |
duke@435 | 3747 | void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { |
duke@435 | 3748 | // A hand-coded argument reduction for values in fabs(pi/4, pi/2) |
duke@435 | 3749 | // was attempted in this code; unfortunately it appears that the |
duke@435 | 3750 | // switch to 80-bit precision and back causes this to be |
duke@435 | 3751 | // unprofitable compared with simply performing a runtime call if |
duke@435 | 3752 | // the argument is out of the (-pi/4, pi/4) range. |
duke@435 | 3753 | |
duke@435 | 3754 | Register tmp = noreg; |
duke@435 | 3755 | if (!VM_Version::supports_cmov()) { |
duke@435 | 3756 | // fcmp needs a temporary so preserve rbx, |
duke@435 | 3757 | tmp = rbx; |
duke@435 | 3758 | pushl(tmp); |
duke@435 | 3759 | } |
duke@435 | 3760 | |
duke@435 | 3761 | Label slow_case, done; |
duke@435 | 3762 | |
duke@435 | 3763 | // x ?<= pi/4 |
duke@435 | 3764 | fld_d(ExternalAddress((address)&pi_4)); |
duke@435 | 3765 | fld_s(1); // Stack: X PI/4 X |
duke@435 | 3766 | fabs(); // Stack: |X| PI/4 X |
duke@435 | 3767 | fcmp(tmp); |
duke@435 | 3768 | jcc(Assembler::above, slow_case); |
duke@435 | 3769 | |
duke@435 | 3770 | // fastest case: -pi/4 <= x <= pi/4 |
duke@435 | 3771 | switch(trig) { |
duke@435 | 3772 | case 's': |
duke@435 | 3773 | fsin(); |
duke@435 | 3774 | break; |
duke@435 | 3775 | case 'c': |
duke@435 | 3776 | fcos(); |
duke@435 | 3777 | break; |
duke@435 | 3778 | case 't': |
duke@435 | 3779 | ftan(); |
duke@435 | 3780 | break; |
duke@435 | 3781 | default: |
duke@435 | 3782 | assert(false, "bad intrinsic"); |
duke@435 | 3783 | break; |
duke@435 | 3784 | } |
duke@435 | 3785 | jmp(done); |
duke@435 | 3786 | |
duke@435 | 3787 | // slow case: runtime call |
duke@435 | 3788 | bind(slow_case); |
duke@435 | 3789 | // Preserve registers across runtime call |
duke@435 | 3790 | pushad(); |
duke@435 | 3791 | int incoming_argument_and_return_value_offset = -1; |
duke@435 | 3792 | if (num_fpu_regs_in_use > 1) { |
duke@435 | 3793 | // Must preserve all other FPU regs (could alternatively convert |
duke@435 | 3794 | // SharedRuntime::dsin and dcos into assembly routines known not to trash |
duke@435 | 3795 | // FPU state, but can not trust C compiler) |
duke@435 | 3796 | NEEDS_CLEANUP; |
duke@435 | 3797 | // NOTE that in this case we also push the incoming argument to |
duke@435 | 3798 | // the stack and restore it later; we also use this stack slot to |
duke@435 | 3799 | // hold the return value from dsin or dcos. |
duke@435 | 3800 | for (int i = 0; i < num_fpu_regs_in_use; i++) { |
duke@435 | 3801 | subl(rsp, wordSize*2); |
duke@435 | 3802 | fstp_d(Address(rsp, 0)); |
duke@435 | 3803 | } |
duke@435 | 3804 | incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1); |
duke@435 | 3805 | fld_d(Address(rsp, incoming_argument_and_return_value_offset)); |
duke@435 | 3806 | } |
duke@435 | 3807 | subl(rsp, wordSize*2); |
duke@435 | 3808 | fstp_d(Address(rsp, 0)); |
duke@435 | 3809 | // NOTE: we must not use call_VM_leaf here because that requires a |
duke@435 | 3810 | // complete interpreter frame in debug mode -- same bug as 4387334 |
duke@435 | 3811 | NEEDS_CLEANUP; |
duke@435 | 3812 | // Need to add stack banging before this runtime call if it needs to |
duke@435 | 3813 | // be taken; however, there is no generic stack banging routine at |
duke@435 | 3814 | // the MacroAssembler level |
duke@435 | 3815 | switch(trig) { |
duke@435 | 3816 | case 's': |
duke@435 | 3817 | { |
duke@435 | 3818 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin))); |
duke@435 | 3819 | } |
duke@435 | 3820 | break; |
duke@435 | 3821 | case 'c': |
duke@435 | 3822 | { |
duke@435 | 3823 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos))); |
duke@435 | 3824 | } |
duke@435 | 3825 | break; |
duke@435 | 3826 | case 't': |
duke@435 | 3827 | { |
duke@435 | 3828 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan))); |
duke@435 | 3829 | } |
duke@435 | 3830 | break; |
duke@435 | 3831 | default: |
duke@435 | 3832 | assert(false, "bad intrinsic"); |
duke@435 | 3833 | break; |
duke@435 | 3834 | } |
duke@435 | 3835 | addl(rsp, wordSize * 2); |
duke@435 | 3836 | if (num_fpu_regs_in_use > 1) { |
duke@435 | 3837 | // Must save return value to stack and then restore entire FPU stack |
duke@435 | 3838 | fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); |
duke@435 | 3839 | for (int i = 0; i < num_fpu_regs_in_use; i++) { |
duke@435 | 3840 | fld_d(Address(rsp, 0)); |
duke@435 | 3841 | addl(rsp, wordSize*2); |
duke@435 | 3842 | } |
duke@435 | 3843 | } |
duke@435 | 3844 | popad(); |
duke@435 | 3845 | |
duke@435 | 3846 | // Come here with result in F-TOS |
duke@435 | 3847 | bind(done); |
duke@435 | 3848 | |
duke@435 | 3849 | if (tmp != noreg) { |
duke@435 | 3850 | popl(tmp); |
duke@435 | 3851 | } |
duke@435 | 3852 | } |
duke@435 | 3853 | |
duke@435 | 3854 | void MacroAssembler::jC2(Register tmp, Label& L) { |
duke@435 | 3855 | // set parity bit if FPU flag C2 is set (via rax) |
duke@435 | 3856 | save_rax(tmp); |
duke@435 | 3857 | fwait(); fnstsw_ax(); |
duke@435 | 3858 | sahf(); |
duke@435 | 3859 | restore_rax(tmp); |
duke@435 | 3860 | // branch |
duke@435 | 3861 | jcc(Assembler::parity, L); |
duke@435 | 3862 | } |
duke@435 | 3863 | |
duke@435 | 3864 | |
duke@435 | 3865 | void MacroAssembler::jnC2(Register tmp, Label& L) { |
duke@435 | 3866 | // set parity bit if FPU flag C2 is set (via rax) |
duke@435 | 3867 | save_rax(tmp); |
duke@435 | 3868 | fwait(); fnstsw_ax(); |
duke@435 | 3869 | sahf(); |
duke@435 | 3870 | restore_rax(tmp); |
duke@435 | 3871 | // branch |
duke@435 | 3872 | jcc(Assembler::noParity, L); |
duke@435 | 3873 | } |
duke@435 | 3874 | |
duke@435 | 3875 | |
duke@435 | 3876 | void MacroAssembler::fcmp(Register tmp) { |
duke@435 | 3877 | fcmp(tmp, 1, true, true); |
duke@435 | 3878 | } |
duke@435 | 3879 | |
duke@435 | 3880 | |
duke@435 | 3881 | void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { |
duke@435 | 3882 | assert(!pop_right || pop_left, "usage error"); |
duke@435 | 3883 | if (VM_Version::supports_cmov()) { |
duke@435 | 3884 | assert(tmp == noreg, "unneeded temp"); |
duke@435 | 3885 | if (pop_left) { |
duke@435 | 3886 | fucomip(index); |
duke@435 | 3887 | } else { |
duke@435 | 3888 | fucomi(index); |
duke@435 | 3889 | } |
duke@435 | 3890 | if (pop_right) { |
duke@435 | 3891 | fpop(); |
duke@435 | 3892 | } |
duke@435 | 3893 | } else { |
duke@435 | 3894 | assert(tmp != noreg, "need temp"); |
duke@435 | 3895 | if (pop_left) { |
duke@435 | 3896 | if (pop_right) { |
duke@435 | 3897 | fcompp(); |
duke@435 | 3898 | } else { |
duke@435 | 3899 | fcomp(index); |
duke@435 | 3900 | } |
duke@435 | 3901 | } else { |
duke@435 | 3902 | fcom(index); |
duke@435 | 3903 | } |
duke@435 | 3904 | // convert FPU condition into eflags condition via rax, |
duke@435 | 3905 | save_rax(tmp); |
duke@435 | 3906 | fwait(); fnstsw_ax(); |
duke@435 | 3907 | sahf(); |
duke@435 | 3908 | restore_rax(tmp); |
duke@435 | 3909 | } |
duke@435 | 3910 | // condition codes set as follows: |
duke@435 | 3911 | // |
duke@435 | 3912 | // CF (corresponds to C0) if x < y |
duke@435 | 3913 | // PF (corresponds to C2) if unordered |
duke@435 | 3914 | // ZF (corresponds to C3) if x = y |
duke@435 | 3915 | } |
duke@435 | 3916 | |
duke@435 | 3917 | |
duke@435 | 3918 | void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { |
duke@435 | 3919 | fcmp2int(dst, unordered_is_less, 1, true, true); |
duke@435 | 3920 | } |
duke@435 | 3921 | |
duke@435 | 3922 | |
duke@435 | 3923 | void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { |
duke@435 | 3924 | fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); |
duke@435 | 3925 | Label L; |
duke@435 | 3926 | if (unordered_is_less) { |
duke@435 | 3927 | movl(dst, -1); |
duke@435 | 3928 | jcc(Assembler::parity, L); |
duke@435 | 3929 | jcc(Assembler::below , L); |
duke@435 | 3930 | movl(dst, 0); |
duke@435 | 3931 | jcc(Assembler::equal , L); |
duke@435 | 3932 | increment(dst); |
duke@435 | 3933 | } else { // unordered is greater |
duke@435 | 3934 | movl(dst, 1); |
duke@435 | 3935 | jcc(Assembler::parity, L); |
duke@435 | 3936 | jcc(Assembler::above , L); |
duke@435 | 3937 | movl(dst, 0); |
duke@435 | 3938 | jcc(Assembler::equal , L); |
duke@435 | 3939 | decrement(dst); |
duke@435 | 3940 | } |
duke@435 | 3941 | bind(L); |
duke@435 | 3942 | } |
duke@435 | 3943 | |
duke@435 | 3944 | void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { |
duke@435 | 3945 | ucomiss(opr1, opr2); |
duke@435 | 3946 | |
duke@435 | 3947 | Label L; |
duke@435 | 3948 | if (unordered_is_less) { |
duke@435 | 3949 | movl(dst, -1); |
duke@435 | 3950 | jcc(Assembler::parity, L); |
duke@435 | 3951 | jcc(Assembler::below , L); |
duke@435 | 3952 | movl(dst, 0); |
duke@435 | 3953 | jcc(Assembler::equal , L); |
duke@435 | 3954 | increment(dst); |
duke@435 | 3955 | } else { // unordered is greater |
duke@435 | 3956 | movl(dst, 1); |
duke@435 | 3957 | jcc(Assembler::parity, L); |
duke@435 | 3958 | jcc(Assembler::above , L); |
duke@435 | 3959 | movl(dst, 0); |
duke@435 | 3960 | jcc(Assembler::equal , L); |
duke@435 | 3961 | decrement(dst); |
duke@435 | 3962 | } |
duke@435 | 3963 | bind(L); |
duke@435 | 3964 | } |
duke@435 | 3965 | |
duke@435 | 3966 | void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { |
duke@435 | 3967 | ucomisd(opr1, opr2); |
duke@435 | 3968 | |
duke@435 | 3969 | Label L; |
duke@435 | 3970 | if (unordered_is_less) { |
duke@435 | 3971 | movl(dst, -1); |
duke@435 | 3972 | jcc(Assembler::parity, L); |
duke@435 | 3973 | jcc(Assembler::below , L); |
duke@435 | 3974 | movl(dst, 0); |
duke@435 | 3975 | jcc(Assembler::equal , L); |
duke@435 | 3976 | increment(dst); |
duke@435 | 3977 | } else { // unordered is greater |
duke@435 | 3978 | movl(dst, 1); |
duke@435 | 3979 | jcc(Assembler::parity, L); |
duke@435 | 3980 | jcc(Assembler::above , L); |
duke@435 | 3981 | movl(dst, 0); |
duke@435 | 3982 | jcc(Assembler::equal , L); |
duke@435 | 3983 | decrement(dst); |
duke@435 | 3984 | } |
duke@435 | 3985 | bind(L); |
duke@435 | 3986 | } |
duke@435 | 3987 | |
duke@435 | 3988 | |
duke@435 | 3989 | |
duke@435 | 3990 | void MacroAssembler::fpop() { |
duke@435 | 3991 | ffree(); |
duke@435 | 3992 | fincstp(); |
duke@435 | 3993 | } |
duke@435 | 3994 | |
duke@435 | 3995 | |
duke@435 | 3996 | void MacroAssembler::sign_extend_short(Register reg) { |
duke@435 | 3997 | if (VM_Version::is_P6()) { |
duke@435 | 3998 | movsxw(reg, reg); |
duke@435 | 3999 | } else { |
duke@435 | 4000 | shll(reg, 16); |
duke@435 | 4001 | sarl(reg, 16); |
duke@435 | 4002 | } |
duke@435 | 4003 | } |
duke@435 | 4004 | |
duke@435 | 4005 | |
duke@435 | 4006 | void MacroAssembler::sign_extend_byte(Register reg) { |
duke@435 | 4007 | if (VM_Version::is_P6() && reg->has_byte_register()) { |
duke@435 | 4008 | movsxb(reg, reg); |
duke@435 | 4009 | } else { |
duke@435 | 4010 | shll(reg, 24); |
duke@435 | 4011 | sarl(reg, 24); |
duke@435 | 4012 | } |
duke@435 | 4013 | } |
duke@435 | 4014 | |
duke@435 | 4015 | |
duke@435 | 4016 | void MacroAssembler::division_with_shift (Register reg, int shift_value) { |
duke@435 | 4017 | assert (shift_value > 0, "illegal shift value"); |
duke@435 | 4018 | Label _is_positive; |
duke@435 | 4019 | testl (reg, reg); |
duke@435 | 4020 | jcc (Assembler::positive, _is_positive); |
duke@435 | 4021 | int offset = (1 << shift_value) - 1 ; |
duke@435 | 4022 | |
duke@435 | 4023 | increment(reg, offset); |
duke@435 | 4024 | |
duke@435 | 4025 | bind (_is_positive); |
duke@435 | 4026 | sarl(reg, shift_value); |
duke@435 | 4027 | } |
duke@435 | 4028 | |
duke@435 | 4029 | |
duke@435 | 4030 | void MacroAssembler::round_to(Register reg, int modulus) { |
duke@435 | 4031 | addl(reg, modulus - 1); |
duke@435 | 4032 | andl(reg, -modulus); |
duke@435 | 4033 | } |
duke@435 | 4034 | |
duke@435 | 4035 | // C++ bool manipulation |
duke@435 | 4036 | |
duke@435 | 4037 | void MacroAssembler::movbool(Register dst, Address src) { |
duke@435 | 4038 | if(sizeof(bool) == 1) |
duke@435 | 4039 | movb(dst, src); |
duke@435 | 4040 | else if(sizeof(bool) == 2) |
duke@435 | 4041 | movw(dst, src); |
duke@435 | 4042 | else if(sizeof(bool) == 4) |
duke@435 | 4043 | movl(dst, src); |
duke@435 | 4044 | else |
duke@435 | 4045 | // unsupported |
duke@435 | 4046 | ShouldNotReachHere(); |
duke@435 | 4047 | } |
duke@435 | 4048 | |
duke@435 | 4049 | void MacroAssembler::movbool(Address dst, bool boolconst) { |
duke@435 | 4050 | if(sizeof(bool) == 1) |
duke@435 | 4051 | movb(dst, (int) boolconst); |
duke@435 | 4052 | else if(sizeof(bool) == 2) |
duke@435 | 4053 | movw(dst, (int) boolconst); |
duke@435 | 4054 | else if(sizeof(bool) == 4) |
duke@435 | 4055 | movl(dst, (int) boolconst); |
duke@435 | 4056 | else |
duke@435 | 4057 | // unsupported |
duke@435 | 4058 | ShouldNotReachHere(); |
duke@435 | 4059 | } |
duke@435 | 4060 | |
duke@435 | 4061 | void MacroAssembler::movbool(Address dst, Register src) { |
duke@435 | 4062 | if(sizeof(bool) == 1) |
duke@435 | 4063 | movb(dst, src); |
duke@435 | 4064 | else if(sizeof(bool) == 2) |
duke@435 | 4065 | movw(dst, src); |
duke@435 | 4066 | else if(sizeof(bool) == 4) |
duke@435 | 4067 | movl(dst, src); |
duke@435 | 4068 | else |
duke@435 | 4069 | // unsupported |
duke@435 | 4070 | ShouldNotReachHere(); |
duke@435 | 4071 | } |
duke@435 | 4072 | |
duke@435 | 4073 | void MacroAssembler::testbool(Register dst) { |
duke@435 | 4074 | if(sizeof(bool) == 1) |
duke@435 | 4075 | testb(dst, (int) 0xff); |
duke@435 | 4076 | else if(sizeof(bool) == 2) { |
duke@435 | 4077 | // testw implementation needed for two byte bools |
duke@435 | 4078 | ShouldNotReachHere(); |
duke@435 | 4079 | } else if(sizeof(bool) == 4) |
duke@435 | 4080 | testl(dst, dst); |
duke@435 | 4081 | else |
duke@435 | 4082 | // unsupported |
duke@435 | 4083 | ShouldNotReachHere(); |
duke@435 | 4084 | } |
duke@435 | 4085 | |
duke@435 | 4086 | void MacroAssembler::verify_oop(Register reg, const char* s) { |
duke@435 | 4087 | if (!VerifyOops) return; |
duke@435 | 4088 | // Pass register number to verify_oop_subroutine |
duke@435 | 4089 | char* b = new char[strlen(s) + 50]; |
duke@435 | 4090 | sprintf(b, "verify_oop: %s: %s", reg->name(), s); |
duke@435 | 4091 | pushl(rax); // save rax, |
duke@435 | 4092 | pushl(reg); // pass register argument |
duke@435 | 4093 | ExternalAddress buffer((address) b); |
duke@435 | 4094 | pushptr(buffer.addr()); |
duke@435 | 4095 | // call indirectly to solve generation ordering problem |
duke@435 | 4096 | movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); |
duke@435 | 4097 | call(rax); |
duke@435 | 4098 | } |
duke@435 | 4099 | |
duke@435 | 4100 | |
duke@435 | 4101 | void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
duke@435 | 4102 | if (!VerifyOops) return; |
duke@435 | 4103 | // QQQ fix this |
duke@435 | 4104 | // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
duke@435 | 4105 | // Pass register number to verify_oop_subroutine |
duke@435 | 4106 | char* b = new char[strlen(s) + 50]; |
duke@435 | 4107 | sprintf(b, "verify_oop_addr: %s", s); |
duke@435 | 4108 | pushl(rax); // save rax, |
duke@435 | 4109 | // addr may contain rsp so we will have to adjust it based on the push |
duke@435 | 4110 | // we just did |
duke@435 | 4111 | if (addr.uses(rsp)) { |
duke@435 | 4112 | leal(rax, addr); |
duke@435 | 4113 | pushl(Address(rax, BytesPerWord)); |
duke@435 | 4114 | } else { |
duke@435 | 4115 | pushl(addr); |
duke@435 | 4116 | } |
duke@435 | 4117 | ExternalAddress buffer((address) b); |
duke@435 | 4118 | // pass msg argument |
duke@435 | 4119 | pushptr(buffer.addr()); |
duke@435 | 4120 | // call indirectly to solve generation ordering problem |
duke@435 | 4121 | movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); |
duke@435 | 4122 | call(rax); |
duke@435 | 4123 | // Caller pops the arguments and restores rax, from the stack |
duke@435 | 4124 | } |
duke@435 | 4125 | |
duke@435 | 4126 | |
duke@435 | 4127 | void MacroAssembler::stop(const char* msg) { |
duke@435 | 4128 | ExternalAddress message((address)msg); |
duke@435 | 4129 | // push address of message |
duke@435 | 4130 | pushptr(message.addr()); |
duke@435 | 4131 | { Label L; call(L, relocInfo::none); bind(L); } // push eip |
duke@435 | 4132 | pushad(); // push registers |
duke@435 | 4133 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug))); |
duke@435 | 4134 | hlt(); |
duke@435 | 4135 | } |
duke@435 | 4136 | |
duke@435 | 4137 | |
duke@435 | 4138 | void MacroAssembler::warn(const char* msg) { |
duke@435 | 4139 | push_CPU_state(); |
duke@435 | 4140 | |
duke@435 | 4141 | ExternalAddress message((address) msg); |
duke@435 | 4142 | // push address of message |
duke@435 | 4143 | pushptr(message.addr()); |
duke@435 | 4144 | |
duke@435 | 4145 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); |
duke@435 | 4146 | addl(rsp, wordSize); // discard argument |
duke@435 | 4147 | pop_CPU_state(); |
duke@435 | 4148 | } |
duke@435 | 4149 | |
duke@435 | 4150 | |
duke@435 | 4151 | void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { |
duke@435 | 4152 | // In order to get locks to work, we need to fake a in_VM state |
duke@435 | 4153 | JavaThread* thread = JavaThread::current(); |
duke@435 | 4154 | JavaThreadState saved_state = thread->thread_state(); |
duke@435 | 4155 | thread->set_thread_state(_thread_in_vm); |
duke@435 | 4156 | if (ShowMessageBoxOnError) { |
duke@435 | 4157 | JavaThread* thread = JavaThread::current(); |
duke@435 | 4158 | JavaThreadState saved_state = thread->thread_state(); |
duke@435 | 4159 | thread->set_thread_state(_thread_in_vm); |
duke@435 | 4160 | ttyLocker ttyl; |
duke@435 | 4161 | if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { |
duke@435 | 4162 | BytecodeCounter::print(); |
duke@435 | 4163 | } |
duke@435 | 4164 | // To see where a verify_oop failed, get $ebx+40/X for this frame. |
duke@435 | 4165 | // This is the value of eip which points to where verify_oop will return. |
duke@435 | 4166 | if (os::message_box(msg, "Execution stopped, print registers?")) { |
duke@435 | 4167 | tty->print_cr("eip = 0x%08x", eip); |
duke@435 | 4168 | tty->print_cr("rax, = 0x%08x", rax); |
duke@435 | 4169 | tty->print_cr("rbx, = 0x%08x", rbx); |
duke@435 | 4170 | tty->print_cr("rcx = 0x%08x", rcx); |
duke@435 | 4171 | tty->print_cr("rdx = 0x%08x", rdx); |
duke@435 | 4172 | tty->print_cr("rdi = 0x%08x", rdi); |
duke@435 | 4173 | tty->print_cr("rsi = 0x%08x", rsi); |
duke@435 | 4174 | tty->print_cr("rbp, = 0x%08x", rbp); |
duke@435 | 4175 | tty->print_cr("rsp = 0x%08x", rsp); |
duke@435 | 4176 | BREAKPOINT; |
duke@435 | 4177 | } |
duke@435 | 4178 | } else { |
duke@435 | 4179 | ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); |
duke@435 | 4180 | assert(false, "DEBUG MESSAGE"); |
duke@435 | 4181 | } |
duke@435 | 4182 | ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
duke@435 | 4183 | } |
duke@435 | 4184 | |
duke@435 | 4185 | |
duke@435 | 4186 | |
duke@435 | 4187 | void MacroAssembler::os_breakpoint() { |
duke@435 | 4188 | // instead of directly emitting a breakpoint, call os:breakpoint for better debugability |
duke@435 | 4189 | // (e.g., MSVC can't call ps() otherwise) |
duke@435 | 4190 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); |
duke@435 | 4191 | } |
duke@435 | 4192 | |
duke@435 | 4193 | |
duke@435 | 4194 | void MacroAssembler::push_fTOS() { |
duke@435 | 4195 | subl(rsp, 2 * wordSize); |
duke@435 | 4196 | fstp_d(Address(rsp, 0)); |
duke@435 | 4197 | } |
duke@435 | 4198 | |
duke@435 | 4199 | |
duke@435 | 4200 | void MacroAssembler::pop_fTOS() { |
duke@435 | 4201 | fld_d(Address(rsp, 0)); |
duke@435 | 4202 | addl(rsp, 2 * wordSize); |
duke@435 | 4203 | } |
duke@435 | 4204 | |
duke@435 | 4205 | |
duke@435 | 4206 | void MacroAssembler::empty_FPU_stack() { |
duke@435 | 4207 | if (VM_Version::supports_mmx()) { |
duke@435 | 4208 | emms(); |
duke@435 | 4209 | } else { |
duke@435 | 4210 | for (int i = 8; i-- > 0; ) ffree(i); |
duke@435 | 4211 | } |
duke@435 | 4212 | } |
duke@435 | 4213 | |
duke@435 | 4214 | |
duke@435 | 4215 | class ControlWord { |
duke@435 | 4216 | public: |
duke@435 | 4217 | int32_t _value; |
duke@435 | 4218 | |
duke@435 | 4219 | int rounding_control() const { return (_value >> 10) & 3 ; } |
duke@435 | 4220 | int precision_control() const { return (_value >> 8) & 3 ; } |
duke@435 | 4221 | bool precision() const { return ((_value >> 5) & 1) != 0; } |
duke@435 | 4222 | bool underflow() const { return ((_value >> 4) & 1) != 0; } |
duke@435 | 4223 | bool overflow() const { return ((_value >> 3) & 1) != 0; } |
duke@435 | 4224 | bool zero_divide() const { return ((_value >> 2) & 1) != 0; } |
duke@435 | 4225 | bool denormalized() const { return ((_value >> 1) & 1) != 0; } |
duke@435 | 4226 | bool invalid() const { return ((_value >> 0) & 1) != 0; } |
duke@435 | 4227 | |
duke@435 | 4228 | void print() const { |
duke@435 | 4229 | // rounding control |
duke@435 | 4230 | const char* rc; |
duke@435 | 4231 | switch (rounding_control()) { |
duke@435 | 4232 | case 0: rc = "round near"; break; |
duke@435 | 4233 | case 1: rc = "round down"; break; |
duke@435 | 4234 | case 2: rc = "round up "; break; |
duke@435 | 4235 | case 3: rc = "chop "; break; |
duke@435 | 4236 | }; |
duke@435 | 4237 | // precision control |
duke@435 | 4238 | const char* pc; |
duke@435 | 4239 | switch (precision_control()) { |
duke@435 | 4240 | case 0: pc = "24 bits "; break; |
duke@435 | 4241 | case 1: pc = "reserved"; break; |
duke@435 | 4242 | case 2: pc = "53 bits "; break; |
duke@435 | 4243 | case 3: pc = "64 bits "; break; |
duke@435 | 4244 | }; |
duke@435 | 4245 | // flags |
duke@435 | 4246 | char f[9]; |
duke@435 | 4247 | f[0] = ' '; |
duke@435 | 4248 | f[1] = ' '; |
duke@435 | 4249 | f[2] = (precision ()) ? 'P' : 'p'; |
duke@435 | 4250 | f[3] = (underflow ()) ? 'U' : 'u'; |
duke@435 | 4251 | f[4] = (overflow ()) ? 'O' : 'o'; |
duke@435 | 4252 | f[5] = (zero_divide ()) ? 'Z' : 'z'; |
duke@435 | 4253 | f[6] = (denormalized()) ? 'D' : 'd'; |
duke@435 | 4254 | f[7] = (invalid ()) ? 'I' : 'i'; |
duke@435 | 4255 | f[8] = '\x0'; |
duke@435 | 4256 | // output |
duke@435 | 4257 | printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); |
duke@435 | 4258 | } |
duke@435 | 4259 | |
duke@435 | 4260 | }; |
duke@435 | 4261 | |
duke@435 | 4262 | |
duke@435 | 4263 | class StatusWord { |
duke@435 | 4264 | public: |
duke@435 | 4265 | int32_t _value; |
duke@435 | 4266 | |
duke@435 | 4267 | bool busy() const { return ((_value >> 15) & 1) != 0; } |
duke@435 | 4268 | bool C3() const { return ((_value >> 14) & 1) != 0; } |
duke@435 | 4269 | bool C2() const { return ((_value >> 10) & 1) != 0; } |
duke@435 | 4270 | bool C1() const { return ((_value >> 9) & 1) != 0; } |
duke@435 | 4271 | bool C0() const { return ((_value >> 8) & 1) != 0; } |
duke@435 | 4272 | int top() const { return (_value >> 11) & 7 ; } |
duke@435 | 4273 | bool error_status() const { return ((_value >> 7) & 1) != 0; } |
duke@435 | 4274 | bool stack_fault() const { return ((_value >> 6) & 1) != 0; } |
duke@435 | 4275 | bool precision() const { return ((_value >> 5) & 1) != 0; } |
duke@435 | 4276 | bool underflow() const { return ((_value >> 4) & 1) != 0; } |
duke@435 | 4277 | bool overflow() const { return ((_value >> 3) & 1) != 0; } |
duke@435 | 4278 | bool zero_divide() const { return ((_value >> 2) & 1) != 0; } |
duke@435 | 4279 | bool denormalized() const { return ((_value >> 1) & 1) != 0; } |
duke@435 | 4280 | bool invalid() const { return ((_value >> 0) & 1) != 0; } |
duke@435 | 4281 | |
duke@435 | 4282 | void print() const { |
duke@435 | 4283 | // condition codes |
duke@435 | 4284 | char c[5]; |
duke@435 | 4285 | c[0] = (C3()) ? '3' : '-'; |
duke@435 | 4286 | c[1] = (C2()) ? '2' : '-'; |
duke@435 | 4287 | c[2] = (C1()) ? '1' : '-'; |
duke@435 | 4288 | c[3] = (C0()) ? '0' : '-'; |
duke@435 | 4289 | c[4] = '\x0'; |
duke@435 | 4290 | // flags |
duke@435 | 4291 | char f[9]; |
duke@435 | 4292 | f[0] = (error_status()) ? 'E' : '-'; |
duke@435 | 4293 | f[1] = (stack_fault ()) ? 'S' : '-'; |
duke@435 | 4294 | f[2] = (precision ()) ? 'P' : '-'; |
duke@435 | 4295 | f[3] = (underflow ()) ? 'U' : '-'; |
duke@435 | 4296 | f[4] = (overflow ()) ? 'O' : '-'; |
duke@435 | 4297 | f[5] = (zero_divide ()) ? 'Z' : '-'; |
duke@435 | 4298 | f[6] = (denormalized()) ? 'D' : '-'; |
duke@435 | 4299 | f[7] = (invalid ()) ? 'I' : '-'; |
duke@435 | 4300 | f[8] = '\x0'; |
duke@435 | 4301 | // output |
duke@435 | 4302 | printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); |
duke@435 | 4303 | } |
duke@435 | 4304 | |
duke@435 | 4305 | }; |
duke@435 | 4306 | |
duke@435 | 4307 | |
duke@435 | 4308 | class TagWord { |
duke@435 | 4309 | public: |
duke@435 | 4310 | int32_t _value; |
duke@435 | 4311 | |
duke@435 | 4312 | int tag_at(int i) const { return (_value >> (i*2)) & 3; } |
duke@435 | 4313 | |
duke@435 | 4314 | void print() const { |
duke@435 | 4315 | printf("%04x", _value & 0xFFFF); |
duke@435 | 4316 | } |
duke@435 | 4317 | |
duke@435 | 4318 | }; |
duke@435 | 4319 | |
duke@435 | 4320 | |
duke@435 | 4321 | class FPU_Register { |
duke@435 | 4322 | public: |
duke@435 | 4323 | int32_t _m0; |
duke@435 | 4324 | int32_t _m1; |
duke@435 | 4325 | int16_t _ex; |
duke@435 | 4326 | |
duke@435 | 4327 | bool is_indefinite() const { |
duke@435 | 4328 | return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; |
duke@435 | 4329 | } |
duke@435 | 4330 | |
duke@435 | 4331 | void print() const { |
duke@435 | 4332 | char sign = (_ex < 0) ? '-' : '+'; |
duke@435 | 4333 | const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; |
duke@435 | 4334 | printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); |
duke@435 | 4335 | }; |
duke@435 | 4336 | |
duke@435 | 4337 | }; |
duke@435 | 4338 | |
duke@435 | 4339 | |
duke@435 | 4340 | class FPU_State { |
duke@435 | 4341 | public: |
duke@435 | 4342 | enum { |
duke@435 | 4343 | register_size = 10, |
duke@435 | 4344 | number_of_registers = 8, |
duke@435 | 4345 | register_mask = 7 |
duke@435 | 4346 | }; |
duke@435 | 4347 | |
duke@435 | 4348 | ControlWord _control_word; |
duke@435 | 4349 | StatusWord _status_word; |
duke@435 | 4350 | TagWord _tag_word; |
duke@435 | 4351 | int32_t _error_offset; |
duke@435 | 4352 | int32_t _error_selector; |
duke@435 | 4353 | int32_t _data_offset; |
duke@435 | 4354 | int32_t _data_selector; |
duke@435 | 4355 | int8_t _register[register_size * number_of_registers]; |
duke@435 | 4356 | |
duke@435 | 4357 | int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } |
duke@435 | 4358 | FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } |
duke@435 | 4359 | |
duke@435 | 4360 | const char* tag_as_string(int tag) const { |
duke@435 | 4361 | switch (tag) { |
duke@435 | 4362 | case 0: return "valid"; |
duke@435 | 4363 | case 1: return "zero"; |
duke@435 | 4364 | case 2: return "special"; |
duke@435 | 4365 | case 3: return "empty"; |
duke@435 | 4366 | } |
duke@435 | 4367 | ShouldNotReachHere() |
duke@435 | 4368 | return NULL; |
duke@435 | 4369 | } |
duke@435 | 4370 | |
duke@435 | 4371 | void print() const { |
duke@435 | 4372 | // print computation registers |
duke@435 | 4373 | { int t = _status_word.top(); |
duke@435 | 4374 | for (int i = 0; i < number_of_registers; i++) { |
duke@435 | 4375 | int j = (i - t) & register_mask; |
duke@435 | 4376 | printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); |
duke@435 | 4377 | st(j)->print(); |
duke@435 | 4378 | printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); |
duke@435 | 4379 | } |
duke@435 | 4380 | } |
duke@435 | 4381 | printf("\n"); |
duke@435 | 4382 | // print control registers |
duke@435 | 4383 | printf("ctrl = "); _control_word.print(); printf("\n"); |
duke@435 | 4384 | printf("stat = "); _status_word .print(); printf("\n"); |
duke@435 | 4385 | printf("tags = "); _tag_word .print(); printf("\n"); |
duke@435 | 4386 | } |
duke@435 | 4387 | |
duke@435 | 4388 | }; |
duke@435 | 4389 | |
duke@435 | 4390 | |
duke@435 | 4391 | class Flag_Register { |
duke@435 | 4392 | public: |
duke@435 | 4393 | int32_t _value; |
duke@435 | 4394 | |
duke@435 | 4395 | bool overflow() const { return ((_value >> 11) & 1) != 0; } |
duke@435 | 4396 | bool direction() const { return ((_value >> 10) & 1) != 0; } |
duke@435 | 4397 | bool sign() const { return ((_value >> 7) & 1) != 0; } |
duke@435 | 4398 | bool zero() const { return ((_value >> 6) & 1) != 0; } |
duke@435 | 4399 | bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } |
duke@435 | 4400 | bool parity() const { return ((_value >> 2) & 1) != 0; } |
duke@435 | 4401 | bool carry() const { return ((_value >> 0) & 1) != 0; } |
duke@435 | 4402 | |
duke@435 | 4403 | void print() const { |
duke@435 | 4404 | // flags |
duke@435 | 4405 | char f[8]; |
duke@435 | 4406 | f[0] = (overflow ()) ? 'O' : '-'; |
duke@435 | 4407 | f[1] = (direction ()) ? 'D' : '-'; |
duke@435 | 4408 | f[2] = (sign ()) ? 'S' : '-'; |
duke@435 | 4409 | f[3] = (zero ()) ? 'Z' : '-'; |
duke@435 | 4410 | f[4] = (auxiliary_carry()) ? 'A' : '-'; |
duke@435 | 4411 | f[5] = (parity ()) ? 'P' : '-'; |
duke@435 | 4412 | f[6] = (carry ()) ? 'C' : '-'; |
duke@435 | 4413 | f[7] = '\x0'; |
duke@435 | 4414 | // output |
duke@435 | 4415 | printf("%08x flags = %s", _value, f); |
duke@435 | 4416 | } |
duke@435 | 4417 | |
duke@435 | 4418 | }; |
duke@435 | 4419 | |
duke@435 | 4420 | |
duke@435 | 4421 | class IU_Register { |
duke@435 | 4422 | public: |
duke@435 | 4423 | int32_t _value; |
duke@435 | 4424 | |
duke@435 | 4425 | void print() const { |
duke@435 | 4426 | printf("%08x %11d", _value, _value); |
duke@435 | 4427 | } |
duke@435 | 4428 | |
duke@435 | 4429 | }; |
duke@435 | 4430 | |
duke@435 | 4431 | |
duke@435 | 4432 | class IU_State { |
duke@435 | 4433 | public: |
duke@435 | 4434 | Flag_Register _eflags; |
duke@435 | 4435 | IU_Register _rdi; |
duke@435 | 4436 | IU_Register _rsi; |
duke@435 | 4437 | IU_Register _rbp; |
duke@435 | 4438 | IU_Register _rsp; |
duke@435 | 4439 | IU_Register _rbx; |
duke@435 | 4440 | IU_Register _rdx; |
duke@435 | 4441 | IU_Register _rcx; |
duke@435 | 4442 | IU_Register _rax; |
duke@435 | 4443 | |
duke@435 | 4444 | void print() const { |
duke@435 | 4445 | // computation registers |
duke@435 | 4446 | printf("rax, = "); _rax.print(); printf("\n"); |
duke@435 | 4447 | printf("rbx, = "); _rbx.print(); printf("\n"); |
duke@435 | 4448 | printf("rcx = "); _rcx.print(); printf("\n"); |
duke@435 | 4449 | printf("rdx = "); _rdx.print(); printf("\n"); |
duke@435 | 4450 | printf("rdi = "); _rdi.print(); printf("\n"); |
duke@435 | 4451 | printf("rsi = "); _rsi.print(); printf("\n"); |
duke@435 | 4452 | printf("rbp, = "); _rbp.print(); printf("\n"); |
duke@435 | 4453 | printf("rsp = "); _rsp.print(); printf("\n"); |
duke@435 | 4454 | printf("\n"); |
duke@435 | 4455 | // control registers |
duke@435 | 4456 | printf("flgs = "); _eflags.print(); printf("\n"); |
duke@435 | 4457 | } |
duke@435 | 4458 | }; |
duke@435 | 4459 | |
duke@435 | 4460 | |
duke@435 | 4461 | class CPU_State { |
duke@435 | 4462 | public: |
duke@435 | 4463 | FPU_State _fpu_state; |
duke@435 | 4464 | IU_State _iu_state; |
duke@435 | 4465 | |
duke@435 | 4466 | void print() const { |
duke@435 | 4467 | printf("--------------------------------------------------\n"); |
duke@435 | 4468 | _iu_state .print(); |
duke@435 | 4469 | printf("\n"); |
duke@435 | 4470 | _fpu_state.print(); |
duke@435 | 4471 | printf("--------------------------------------------------\n"); |
duke@435 | 4472 | } |
duke@435 | 4473 | |
duke@435 | 4474 | }; |
duke@435 | 4475 | |
duke@435 | 4476 | |
duke@435 | 4477 | static void _print_CPU_state(CPU_State* state) { |
duke@435 | 4478 | state->print(); |
duke@435 | 4479 | }; |
duke@435 | 4480 | |
duke@435 | 4481 | |
duke@435 | 4482 | void MacroAssembler::print_CPU_state() { |
duke@435 | 4483 | push_CPU_state(); |
duke@435 | 4484 | pushl(rsp); // pass CPU state |
duke@435 | 4485 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
duke@435 | 4486 | addl(rsp, wordSize); // discard argument |
duke@435 | 4487 | pop_CPU_state(); |
duke@435 | 4488 | } |
duke@435 | 4489 | |
duke@435 | 4490 | |
duke@435 | 4491 | static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { |
duke@435 | 4492 | static int counter = 0; |
duke@435 | 4493 | FPU_State* fs = &state->_fpu_state; |
duke@435 | 4494 | counter++; |
duke@435 | 4495 | // For leaf calls, only verify that the top few elements remain empty. |
duke@435 | 4496 | // We only need 1 empty at the top for C2 code. |
duke@435 | 4497 | if( stack_depth < 0 ) { |
duke@435 | 4498 | if( fs->tag_for_st(7) != 3 ) { |
duke@435 | 4499 | printf("FPR7 not empty\n"); |
duke@435 | 4500 | state->print(); |
duke@435 | 4501 | assert(false, "error"); |
duke@435 | 4502 | return false; |
duke@435 | 4503 | } |
duke@435 | 4504 | return true; // All other stack states do not matter |
duke@435 | 4505 | } |
duke@435 | 4506 | |
duke@435 | 4507 | assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, |
duke@435 | 4508 | "bad FPU control word"); |
duke@435 | 4509 | |
duke@435 | 4510 | // compute stack depth |
duke@435 | 4511 | int i = 0; |
duke@435 | 4512 | while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; |
duke@435 | 4513 | int d = i; |
duke@435 | 4514 | while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; |
duke@435 | 4515 | // verify findings |
duke@435 | 4516 | if (i != FPU_State::number_of_registers) { |
duke@435 | 4517 | // stack not contiguous |
duke@435 | 4518 | printf("%s: stack not contiguous at ST%d\n", s, i); |
duke@435 | 4519 | state->print(); |
duke@435 | 4520 | assert(false, "error"); |
duke@435 | 4521 | return false; |
duke@435 | 4522 | } |
duke@435 | 4523 | // check if computed stack depth corresponds to expected stack depth |
duke@435 | 4524 | if (stack_depth < 0) { |
duke@435 | 4525 | // expected stack depth is -stack_depth or less |
duke@435 | 4526 | if (d > -stack_depth) { |
duke@435 | 4527 | // too many elements on the stack |
duke@435 | 4528 | printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); |
duke@435 | 4529 | state->print(); |
duke@435 | 4530 | assert(false, "error"); |
duke@435 | 4531 | return false; |
duke@435 | 4532 | } |
duke@435 | 4533 | } else { |
duke@435 | 4534 | // expected stack depth is stack_depth |
duke@435 | 4535 | if (d != stack_depth) { |
duke@435 | 4536 | // wrong stack depth |
duke@435 | 4537 | printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); |
duke@435 | 4538 | state->print(); |
duke@435 | 4539 | assert(false, "error"); |
duke@435 | 4540 | return false; |
duke@435 | 4541 | } |
duke@435 | 4542 | } |
duke@435 | 4543 | // everything is cool |
duke@435 | 4544 | return true; |
duke@435 | 4545 | } |
duke@435 | 4546 | |
duke@435 | 4547 | |
duke@435 | 4548 | void MacroAssembler::verify_FPU(int stack_depth, const char* s) { |
duke@435 | 4549 | if (!VerifyFPU) return; |
duke@435 | 4550 | push_CPU_state(); |
duke@435 | 4551 | pushl(rsp); // pass CPU state |
duke@435 | 4552 | ExternalAddress msg((address) s); |
duke@435 | 4553 | // pass message string s |
duke@435 | 4554 | pushptr(msg.addr()); |
duke@435 | 4555 | pushl(stack_depth); // pass stack depth |
duke@435 | 4556 | call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
duke@435 | 4557 | addl(rsp, 3 * wordSize); // discard arguments |
duke@435 | 4558 | // check for error |
duke@435 | 4559 | { Label L; |
duke@435 | 4560 | testl(rax, rax); |
duke@435 | 4561 | jcc(Assembler::notZero, L); |
duke@435 | 4562 | int3(); // break if error condition |
duke@435 | 4563 | bind(L); |
duke@435 | 4564 | } |
duke@435 | 4565 | pop_CPU_state(); |
duke@435 | 4566 | } |
duke@435 | 4567 | |
duke@435 | 4568 | |
duke@435 | 4569 | void MacroAssembler::push_IU_state() { |
duke@435 | 4570 | pushad(); |
duke@435 | 4571 | pushfd(); |
duke@435 | 4572 | } |
duke@435 | 4573 | |
duke@435 | 4574 | |
duke@435 | 4575 | void MacroAssembler::pop_IU_state() { |
duke@435 | 4576 | popfd(); |
duke@435 | 4577 | popad(); |
duke@435 | 4578 | } |
duke@435 | 4579 | |
duke@435 | 4580 | |
duke@435 | 4581 | void MacroAssembler::push_FPU_state() { |
duke@435 | 4582 | subl(rsp, FPUStateSizeInWords * wordSize); |
duke@435 | 4583 | fnsave(Address(rsp, 0)); |
duke@435 | 4584 | fwait(); |
duke@435 | 4585 | } |
duke@435 | 4586 | |
duke@435 | 4587 | |
duke@435 | 4588 | void MacroAssembler::pop_FPU_state() { |
duke@435 | 4589 | frstor(Address(rsp, 0)); |
duke@435 | 4590 | addl(rsp, FPUStateSizeInWords * wordSize); |
duke@435 | 4591 | } |
duke@435 | 4592 | |
duke@435 | 4593 | |
duke@435 | 4594 | void MacroAssembler::push_CPU_state() { |
duke@435 | 4595 | push_IU_state(); |
duke@435 | 4596 | push_FPU_state(); |
duke@435 | 4597 | } |
duke@435 | 4598 | |
duke@435 | 4599 | |
duke@435 | 4600 | void MacroAssembler::pop_CPU_state() { |
duke@435 | 4601 | pop_FPU_state(); |
duke@435 | 4602 | pop_IU_state(); |
duke@435 | 4603 | } |
duke@435 | 4604 | |
duke@435 | 4605 | |
duke@435 | 4606 | void MacroAssembler::push_callee_saved_registers() { |
duke@435 | 4607 | pushl(rsi); |
duke@435 | 4608 | pushl(rdi); |
duke@435 | 4609 | pushl(rdx); |
duke@435 | 4610 | pushl(rcx); |
duke@435 | 4611 | } |
duke@435 | 4612 | |
duke@435 | 4613 | |
duke@435 | 4614 | void MacroAssembler::pop_callee_saved_registers() { |
duke@435 | 4615 | popl(rcx); |
duke@435 | 4616 | popl(rdx); |
duke@435 | 4617 | popl(rdi); |
duke@435 | 4618 | popl(rsi); |
duke@435 | 4619 | } |
duke@435 | 4620 | |
duke@435 | 4621 | |
duke@435 | 4622 | void MacroAssembler::set_word_if_not_zero(Register dst) { |
duke@435 | 4623 | xorl(dst, dst); |
duke@435 | 4624 | set_byte_if_not_zero(dst); |
duke@435 | 4625 | } |
duke@435 | 4626 | |
duke@435 | 4627 | // Write serialization page so VM thread can do a pseudo remote membar. |
duke@435 | 4628 | // We use the current thread pointer to calculate a thread specific |
duke@435 | 4629 | // offset to write to within the page. This minimizes bus traffic |
duke@435 | 4630 | // due to cache line collision. |
duke@435 | 4631 | void MacroAssembler::serialize_memory(Register thread, Register tmp) { |
duke@435 | 4632 | movl(tmp, thread); |
duke@435 | 4633 | shrl(tmp, os::get_serialize_page_shift_count()); |
duke@435 | 4634 | andl(tmp, (os::vm_page_size() - sizeof(int))); |
duke@435 | 4635 | |
duke@435 | 4636 | Address index(noreg, tmp, Address::times_1); |
duke@435 | 4637 | ExternalAddress page(os::get_memory_serialize_page()); |
duke@435 | 4638 | |
duke@435 | 4639 | movptr(ArrayAddress(page, index), tmp); |
duke@435 | 4640 | } |
duke@435 | 4641 | |
duke@435 | 4642 | |
duke@435 | 4643 | void MacroAssembler::verify_tlab() { |
duke@435 | 4644 | #ifdef ASSERT |
duke@435 | 4645 | if (UseTLAB && VerifyOops) { |
duke@435 | 4646 | Label next, ok; |
duke@435 | 4647 | Register t1 = rsi; |
duke@435 | 4648 | Register thread_reg = rbx; |
duke@435 | 4649 | |
duke@435 | 4650 | pushl(t1); |
duke@435 | 4651 | pushl(thread_reg); |
duke@435 | 4652 | get_thread(thread_reg); |
duke@435 | 4653 | |
duke@435 | 4654 | movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); |
duke@435 | 4655 | cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
duke@435 | 4656 | jcc(Assembler::aboveEqual, next); |
duke@435 | 4657 | stop("assert(top >= start)"); |
duke@435 | 4658 | should_not_reach_here(); |
duke@435 | 4659 | |
duke@435 | 4660 | bind(next); |
duke@435 | 4661 | movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); |
duke@435 | 4662 | cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); |
duke@435 | 4663 | jcc(Assembler::aboveEqual, ok); |
duke@435 | 4664 | stop("assert(top <= end)"); |
duke@435 | 4665 | should_not_reach_here(); |
duke@435 | 4666 | |
duke@435 | 4667 | bind(ok); |
duke@435 | 4668 | popl(thread_reg); |
duke@435 | 4669 | popl(t1); |
duke@435 | 4670 | } |
duke@435 | 4671 | #endif |
duke@435 | 4672 | } |
duke@435 | 4673 | |
duke@435 | 4674 | |
duke@435 | 4675 | // Defines obj, preserves var_size_in_bytes |
duke@435 | 4676 | void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, |
duke@435 | 4677 | Register t1, Label& slow_case) { |
duke@435 | 4678 | assert(obj == rax, "obj must be in rax, for cmpxchg"); |
duke@435 | 4679 | assert_different_registers(obj, var_size_in_bytes, t1); |
ysr@777 | 4680 | if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
ysr@777 | 4681 | jmp(slow_case); |
duke@435 | 4682 | } else { |
ysr@777 | 4683 | Register end = t1; |
ysr@777 | 4684 | Label retry; |
ysr@777 | 4685 | bind(retry); |
ysr@777 | 4686 | ExternalAddress heap_top((address) Universe::heap()->top_addr()); |
ysr@777 | 4687 | movptr(obj, heap_top); |
ysr@777 | 4688 | if (var_size_in_bytes == noreg) { |
ysr@777 | 4689 | leal(end, Address(obj, con_size_in_bytes)); |
ysr@777 | 4690 | } else { |
ysr@777 | 4691 | leal(end, Address(obj, var_size_in_bytes, Address::times_1)); |
ysr@777 | 4692 | } |
ysr@777 | 4693 | // if end < obj then we wrapped around => object too long => slow case |
ysr@777 | 4694 | cmpl(end, obj); |
ysr@777 | 4695 | jcc(Assembler::below, slow_case); |
ysr@777 | 4696 | cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); |
ysr@777 | 4697 | jcc(Assembler::above, slow_case); |
ysr@777 | 4698 | // Compare obj with the top addr, and if still equal, store the new top addr in |
ysr@777 | 4699 | // end at the address of the top addr pointer. Sets ZF if was equal, and clears |
ysr@777 | 4700 | // it otherwise. Use lock prefix for atomicity on MPs. |
ysr@777 | 4701 | if (os::is_MP()) { |
ysr@777 | 4702 | lock(); |
ysr@777 | 4703 | } |
ysr@777 | 4704 | cmpxchgptr(end, heap_top); |
ysr@777 | 4705 | jcc(Assembler::notEqual, retry); |
duke@435 | 4706 | } |
duke@435 | 4707 | } |
duke@435 | 4708 | |
duke@435 | 4709 | |
duke@435 | 4710 | // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. |
duke@435 | 4711 | void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, |
duke@435 | 4712 | Register t1, Register t2, Label& slow_case) { |
duke@435 | 4713 | assert_different_registers(obj, t1, t2); |
duke@435 | 4714 | assert_different_registers(obj, var_size_in_bytes, t1); |
duke@435 | 4715 | Register end = t2; |
duke@435 | 4716 | Register thread = t1; |
duke@435 | 4717 | |
duke@435 | 4718 | verify_tlab(); |
duke@435 | 4719 | |
duke@435 | 4720 | get_thread(thread); |
duke@435 | 4721 | |
duke@435 | 4722 | movl(obj, Address(thread, JavaThread::tlab_top_offset())); |
duke@435 | 4723 | if (var_size_in_bytes == noreg) { |
duke@435 | 4724 | leal(end, Address(obj, con_size_in_bytes)); |
duke@435 | 4725 | } else { |
duke@435 | 4726 | leal(end, Address(obj, var_size_in_bytes, Address::times_1)); |
duke@435 | 4727 | } |
duke@435 | 4728 | cmpl(end, Address(thread, JavaThread::tlab_end_offset())); |
duke@435 | 4729 | jcc(Assembler::above, slow_case); |
duke@435 | 4730 | |
duke@435 | 4731 | // update the tlab top pointer |
duke@435 | 4732 | movl(Address(thread, JavaThread::tlab_top_offset()), end); |
duke@435 | 4733 | |
duke@435 | 4734 | // recover var_size_in_bytes if necessary |
duke@435 | 4735 | if (var_size_in_bytes == end) { |
duke@435 | 4736 | subl(var_size_in_bytes, obj); |
duke@435 | 4737 | } |
duke@435 | 4738 | verify_tlab(); |
duke@435 | 4739 | } |
duke@435 | 4740 | |
duke@435 | 4741 | // Preserves rbx, and rdx. |
duke@435 | 4742 | void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { |
duke@435 | 4743 | Register top = rax; |
duke@435 | 4744 | Register t1 = rcx; |
duke@435 | 4745 | Register t2 = rsi; |
duke@435 | 4746 | Register thread_reg = rdi; |
duke@435 | 4747 | assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); |
duke@435 | 4748 | Label do_refill, discard_tlab; |
duke@435 | 4749 | |
duke@435 | 4750 | if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
duke@435 | 4751 | // No allocation in the shared eden. |
duke@435 | 4752 | jmp(slow_case); |
duke@435 | 4753 | } |
duke@435 | 4754 | |
duke@435 | 4755 | get_thread(thread_reg); |
duke@435 | 4756 | |
duke@435 | 4757 | movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); |
duke@435 | 4758 | movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); |
duke@435 | 4759 | |
duke@435 | 4760 | // calculate amount of free space |
duke@435 | 4761 | subl(t1, top); |
duke@435 | 4762 | shrl(t1, LogHeapWordSize); |
duke@435 | 4763 | |
duke@435 | 4764 | // Retain tlab and allocate object in shared space if |
duke@435 | 4765 | // the amount free in the tlab is too large to discard. |
duke@435 | 4766 | cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); |
duke@435 | 4767 | jcc(Assembler::lessEqual, discard_tlab); |
duke@435 | 4768 | |
duke@435 | 4769 | // Retain |
duke@435 | 4770 | movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment()); |
duke@435 | 4771 | addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); |
duke@435 | 4772 | if (TLABStats) { |
duke@435 | 4773 | // increment number of slow_allocations |
duke@435 | 4774 | addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); |
duke@435 | 4775 | } |
duke@435 | 4776 | jmp(try_eden); |
duke@435 | 4777 | |
duke@435 | 4778 | bind(discard_tlab); |
duke@435 | 4779 | if (TLABStats) { |
duke@435 | 4780 | // increment number of refills |
duke@435 | 4781 | addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); |
duke@435 | 4782 | // accumulate wastage -- t1 is amount free in tlab |
duke@435 | 4783 | addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); |
duke@435 | 4784 | } |
duke@435 | 4785 | |
duke@435 | 4786 | // if tlab is currently allocated (top or end != null) then |
duke@435 | 4787 | // fill [top, end + alignment_reserve) with array object |
duke@435 | 4788 | testl (top, top); |
duke@435 | 4789 | jcc(Assembler::zero, do_refill); |
duke@435 | 4790 | |
duke@435 | 4791 | // set up the mark word |
duke@435 | 4792 | movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2)); |
duke@435 | 4793 | // set the length to the remaining space |
duke@435 | 4794 | subl(t1, typeArrayOopDesc::header_size(T_INT)); |
duke@435 | 4795 | addl(t1, ThreadLocalAllocBuffer::alignment_reserve()); |
duke@435 | 4796 | shll(t1, log2_intptr(HeapWordSize/sizeof(jint))); |
duke@435 | 4797 | movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
duke@435 | 4798 | // set klass to intArrayKlass |
duke@435 | 4799 | // dubious reloc why not an oop reloc? |
duke@435 | 4800 | movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); |
duke@435 | 4801 | movl(Address(top, oopDesc::klass_offset_in_bytes()), t1); |
duke@435 | 4802 | |
duke@435 | 4803 | // refill the tlab with an eden allocation |
duke@435 | 4804 | bind(do_refill); |
duke@435 | 4805 | movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); |
duke@435 | 4806 | shll(t1, LogHeapWordSize); |
duke@435 | 4807 | // add object_size ?? |
duke@435 | 4808 | eden_allocate(top, t1, 0, t2, slow_case); |
duke@435 | 4809 | |
duke@435 | 4810 | // Check that t1 was preserved in eden_allocate. |
duke@435 | 4811 | #ifdef ASSERT |
duke@435 | 4812 | if (UseTLAB) { |
duke@435 | 4813 | Label ok; |
duke@435 | 4814 | Register tsize = rsi; |
duke@435 | 4815 | assert_different_registers(tsize, thread_reg, t1); |
duke@435 | 4816 | pushl(tsize); |
duke@435 | 4817 | movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); |
duke@435 | 4818 | shll(tsize, LogHeapWordSize); |
duke@435 | 4819 | cmpl(t1, tsize); |
duke@435 | 4820 | jcc(Assembler::equal, ok); |
duke@435 | 4821 | stop("assert(t1 != tlab size)"); |
duke@435 | 4822 | should_not_reach_here(); |
duke@435 | 4823 | |
duke@435 | 4824 | bind(ok); |
duke@435 | 4825 | popl(tsize); |
duke@435 | 4826 | } |
duke@435 | 4827 | #endif |
duke@435 | 4828 | movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); |
duke@435 | 4829 | movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); |
duke@435 | 4830 | addl(top, t1); |
duke@435 | 4831 | subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); |
duke@435 | 4832 | movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); |
duke@435 | 4833 | verify_tlab(); |
duke@435 | 4834 | jmp(retry); |
duke@435 | 4835 | } |
duke@435 | 4836 | |
duke@435 | 4837 | |
duke@435 | 4838 | int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, |
duke@435 | 4839 | bool swap_reg_contains_mark, |
duke@435 | 4840 | Label& done, Label* slow_case, |
duke@435 | 4841 | BiasedLockingCounters* counters) { |
duke@435 | 4842 | assert(UseBiasedLocking, "why call this otherwise?"); |
duke@435 | 4843 | assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); |
duke@435 | 4844 | assert_different_registers(lock_reg, obj_reg, swap_reg); |
duke@435 | 4845 | |
duke@435 | 4846 | if (PrintBiasedLockingStatistics && counters == NULL) |
duke@435 | 4847 | counters = BiasedLocking::counters(); |
duke@435 | 4848 | |
duke@435 | 4849 | bool need_tmp_reg = false; |
duke@435 | 4850 | if (tmp_reg == noreg) { |
duke@435 | 4851 | need_tmp_reg = true; |
duke@435 | 4852 | tmp_reg = lock_reg; |
duke@435 | 4853 | } else { |
duke@435 | 4854 | assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); |
duke@435 | 4855 | } |
duke@435 | 4856 | assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); |
duke@435 | 4857 | Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); |
duke@435 | 4858 | Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); |
duke@435 | 4859 | Address saved_mark_addr(lock_reg, 0); |
duke@435 | 4860 | |
duke@435 | 4861 | // Biased locking |
duke@435 | 4862 | // See whether the lock is currently biased toward our thread and |
duke@435 | 4863 | // whether the epoch is still valid |
duke@435 | 4864 | // Note that the runtime guarantees sufficient alignment of JavaThread |
duke@435 | 4865 | // pointers to allow age to be placed into low bits |
duke@435 | 4866 | // First check to see whether biasing is even enabled for this object |
duke@435 | 4867 | Label cas_label; |
duke@435 | 4868 | int null_check_offset = -1; |
duke@435 | 4869 | if (!swap_reg_contains_mark) { |
duke@435 | 4870 | null_check_offset = offset(); |
duke@435 | 4871 | movl(swap_reg, mark_addr); |
duke@435 | 4872 | } |
duke@435 | 4873 | if (need_tmp_reg) { |
duke@435 | 4874 | pushl(tmp_reg); |
duke@435 | 4875 | } |
duke@435 | 4876 | movl(tmp_reg, swap_reg); |
duke@435 | 4877 | andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); |
duke@435 | 4878 | cmpl(tmp_reg, markOopDesc::biased_lock_pattern); |
duke@435 | 4879 | if (need_tmp_reg) { |
duke@435 | 4880 | popl(tmp_reg); |
duke@435 | 4881 | } |
duke@435 | 4882 | jcc(Assembler::notEqual, cas_label); |
duke@435 | 4883 | // The bias pattern is present in the object's header. Need to check |
duke@435 | 4884 | // whether the bias owner and the epoch are both still current. |
duke@435 | 4885 | // Note that because there is no current thread register on x86 we |
duke@435 | 4886 | // need to store off the mark word we read out of the object to |
duke@435 | 4887 | // avoid reloading it and needing to recheck invariants below. This |
duke@435 | 4888 | // store is unfortunate but it makes the overall code shorter and |
duke@435 | 4889 | // simpler. |
duke@435 | 4890 | movl(saved_mark_addr, swap_reg); |
duke@435 | 4891 | if (need_tmp_reg) { |
duke@435 | 4892 | pushl(tmp_reg); |
duke@435 | 4893 | } |
duke@435 | 4894 | get_thread(tmp_reg); |
duke@435 | 4895 | xorl(swap_reg, tmp_reg); |
duke@435 | 4896 | if (swap_reg_contains_mark) { |
duke@435 | 4897 | null_check_offset = offset(); |
duke@435 | 4898 | } |
duke@435 | 4899 | movl(tmp_reg, klass_addr); |
duke@435 | 4900 | xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
duke@435 | 4901 | andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); |
duke@435 | 4902 | if (need_tmp_reg) { |
duke@435 | 4903 | popl(tmp_reg); |
duke@435 | 4904 | } |
duke@435 | 4905 | if (counters != NULL) { |
duke@435 | 4906 | cond_inc32(Assembler::zero, |
duke@435 | 4907 | ExternalAddress((address)counters->biased_lock_entry_count_addr())); |
duke@435 | 4908 | } |
duke@435 | 4909 | jcc(Assembler::equal, done); |
duke@435 | 4910 | |
duke@435 | 4911 | Label try_revoke_bias; |
duke@435 | 4912 | Label try_rebias; |
duke@435 | 4913 | |
duke@435 | 4914 | // At this point we know that the header has the bias pattern and |
duke@435 | 4915 | // that we are not the bias owner in the current epoch. We need to |
duke@435 | 4916 | // figure out more details about the state of the header in order to |
duke@435 | 4917 | // know what operations can be legally performed on the object's |
duke@435 | 4918 | // header. |
duke@435 | 4919 | |
duke@435 | 4920 | // If the low three bits in the xor result aren't clear, that means |
duke@435 | 4921 | // the prototype header is no longer biased and we have to revoke |
duke@435 | 4922 | // the bias on this object. |
duke@435 | 4923 | testl(swap_reg, markOopDesc::biased_lock_mask_in_place); |
duke@435 | 4924 | jcc(Assembler::notZero, try_revoke_bias); |
duke@435 | 4925 | |
duke@435 | 4926 | // Biasing is still enabled for this data type. See whether the |
duke@435 | 4927 | // epoch of the current bias is still valid, meaning that the epoch |
duke@435 | 4928 | // bits of the mark word are equal to the epoch bits of the |
duke@435 | 4929 | // prototype header. (Note that the prototype header's epoch bits |
duke@435 | 4930 | // only change at a safepoint.) If not, attempt to rebias the object |
duke@435 | 4931 | // toward the current thread. Note that we must be absolutely sure |
duke@435 | 4932 | // that the current epoch is invalid in order to do this because |
duke@435 | 4933 | // otherwise the manipulations it performs on the mark word are |
duke@435 | 4934 | // illegal. |
duke@435 | 4935 | testl(swap_reg, markOopDesc::epoch_mask_in_place); |
duke@435 | 4936 | jcc(Assembler::notZero, try_rebias); |
duke@435 | 4937 | |
duke@435 | 4938 | // The epoch of the current bias is still valid but we know nothing |
duke@435 | 4939 | // about the owner; it might be set or it might be clear. Try to |
duke@435 | 4940 | // acquire the bias of the object using an atomic operation. If this |
duke@435 | 4941 | // fails we will go in to the runtime to revoke the object's bias. |
duke@435 | 4942 | // Note that we first construct the presumed unbiased header so we |
duke@435 | 4943 | // don't accidentally blow away another thread's valid bias. |
duke@435 | 4944 | movl(swap_reg, saved_mark_addr); |
duke@435 | 4945 | andl(swap_reg, |
duke@435 | 4946 | markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); |
duke@435 | 4947 | if (need_tmp_reg) { |
duke@435 | 4948 | pushl(tmp_reg); |
duke@435 | 4949 | } |
duke@435 | 4950 | get_thread(tmp_reg); |
duke@435 | 4951 | orl(tmp_reg, swap_reg); |
duke@435 | 4952 | if (os::is_MP()) { |
duke@435 | 4953 | lock(); |
duke@435 | 4954 | } |
duke@435 | 4955 | cmpxchg(tmp_reg, Address(obj_reg, 0)); |
duke@435 | 4956 | if (need_tmp_reg) { |
duke@435 | 4957 | popl(tmp_reg); |
duke@435 | 4958 | } |
duke@435 | 4959 | // If the biasing toward our thread failed, this means that |
duke@435 | 4960 | // another thread succeeded in biasing it toward itself and we |
duke@435 | 4961 | // need to revoke that bias. The revocation will occur in the |
duke@435 | 4962 | // interpreter runtime in the slow case. |
duke@435 | 4963 | if (counters != NULL) { |
duke@435 | 4964 | cond_inc32(Assembler::zero, |
duke@435 | 4965 | ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); |
duke@435 | 4966 | } |
duke@435 | 4967 | if (slow_case != NULL) { |
duke@435 | 4968 | jcc(Assembler::notZero, *slow_case); |
duke@435 | 4969 | } |
duke@435 | 4970 | jmp(done); |
duke@435 | 4971 | |
duke@435 | 4972 | bind(try_rebias); |
duke@435 | 4973 | // At this point we know the epoch has expired, meaning that the |
duke@435 | 4974 | // current "bias owner", if any, is actually invalid. Under these |
duke@435 | 4975 | // circumstances _only_, we are allowed to use the current header's |
duke@435 | 4976 | // value as the comparison value when doing the cas to acquire the |
duke@435 | 4977 | // bias in the current epoch. In other words, we allow transfer of |
duke@435 | 4978 | // the bias from one thread to another directly in this situation. |
duke@435 | 4979 | // |
duke@435 | 4980 | // FIXME: due to a lack of registers we currently blow away the age |
duke@435 | 4981 | // bits in this situation. Should attempt to preserve them. |
duke@435 | 4982 | if (need_tmp_reg) { |
duke@435 | 4983 | pushl(tmp_reg); |
duke@435 | 4984 | } |
duke@435 | 4985 | get_thread(tmp_reg); |
duke@435 | 4986 | movl(swap_reg, klass_addr); |
duke@435 | 4987 | orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
duke@435 | 4988 | movl(swap_reg, saved_mark_addr); |
duke@435 | 4989 | if (os::is_MP()) { |
duke@435 | 4990 | lock(); |
duke@435 | 4991 | } |
duke@435 | 4992 | cmpxchg(tmp_reg, Address(obj_reg, 0)); |
duke@435 | 4993 | if (need_tmp_reg) { |
duke@435 | 4994 | popl(tmp_reg); |
duke@435 | 4995 | } |
duke@435 | 4996 | // If the biasing toward our thread failed, then another thread |
duke@435 | 4997 | // succeeded in biasing it toward itself and we need to revoke that |
duke@435 | 4998 | // bias. The revocation will occur in the runtime in the slow case. |
duke@435 | 4999 | if (counters != NULL) { |
duke@435 | 5000 | cond_inc32(Assembler::zero, |
duke@435 | 5001 | ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); |
duke@435 | 5002 | } |
duke@435 | 5003 | if (slow_case != NULL) { |
duke@435 | 5004 | jcc(Assembler::notZero, *slow_case); |
duke@435 | 5005 | } |
duke@435 | 5006 | jmp(done); |
duke@435 | 5007 | |
duke@435 | 5008 | bind(try_revoke_bias); |
duke@435 | 5009 | // The prototype mark in the klass doesn't have the bias bit set any |
duke@435 | 5010 | // more, indicating that objects of this data type are not supposed |
duke@435 | 5011 | // to be biased any more. We are going to try to reset the mark of |
duke@435 | 5012 | // this object to the prototype value and fall through to the |
duke@435 | 5013 | // CAS-based locking scheme. Note that if our CAS fails, it means |
duke@435 | 5014 | // that another thread raced us for the privilege of revoking the |
duke@435 | 5015 | // bias of this particular object, so it's okay to continue in the |
duke@435 | 5016 | // normal locking code. |
duke@435 | 5017 | // |
duke@435 | 5018 | // FIXME: due to a lack of registers we currently blow away the age |
duke@435 | 5019 | // bits in this situation. Should attempt to preserve them. |
duke@435 | 5020 | movl(swap_reg, saved_mark_addr); |
duke@435 | 5021 | if (need_tmp_reg) { |
duke@435 | 5022 | pushl(tmp_reg); |
duke@435 | 5023 | } |
duke@435 | 5024 | movl(tmp_reg, klass_addr); |
duke@435 | 5025 | movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
duke@435 | 5026 | if (os::is_MP()) { |
duke@435 | 5027 | lock(); |
duke@435 | 5028 | } |
duke@435 | 5029 | cmpxchg(tmp_reg, Address(obj_reg, 0)); |
duke@435 | 5030 | if (need_tmp_reg) { |
duke@435 | 5031 | popl(tmp_reg); |
duke@435 | 5032 | } |
duke@435 | 5033 | // Fall through to the normal CAS-based lock, because no matter what |
duke@435 | 5034 | // the result of the above CAS, some thread must have succeeded in |
duke@435 | 5035 | // removing the bias bit from the object's header. |
duke@435 | 5036 | if (counters != NULL) { |
duke@435 | 5037 | cond_inc32(Assembler::zero, |
duke@435 | 5038 | ExternalAddress((address)counters->revoked_lock_entry_count_addr())); |
duke@435 | 5039 | } |
duke@435 | 5040 | |
duke@435 | 5041 | bind(cas_label); |
duke@435 | 5042 | |
duke@435 | 5043 | return null_check_offset; |
duke@435 | 5044 | } |
duke@435 | 5045 | |
duke@435 | 5046 | |
duke@435 | 5047 | void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { |
duke@435 | 5048 | assert(UseBiasedLocking, "why call this otherwise?"); |
duke@435 | 5049 | |
duke@435 | 5050 | // Check for biased locking unlock case, which is a no-op |
duke@435 | 5051 | // Note: we do not have to check the thread ID for two reasons. |
duke@435 | 5052 | // First, the interpreter checks for IllegalMonitorStateException at |
duke@435 | 5053 | // a higher level. Second, if the bias was revoked while we held the |
duke@435 | 5054 | // lock, the object could not be rebiased toward another thread, so |
duke@435 | 5055 | // the bias bit would be clear. |
duke@435 | 5056 | movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); |
duke@435 | 5057 | andl(temp_reg, markOopDesc::biased_lock_mask_in_place); |
duke@435 | 5058 | cmpl(temp_reg, markOopDesc::biased_lock_pattern); |
duke@435 | 5059 | jcc(Assembler::equal, done); |
duke@435 | 5060 | } |
duke@435 | 5061 | |
duke@435 | 5062 | |
duke@435 | 5063 | Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
duke@435 | 5064 | switch (cond) { |
duke@435 | 5065 | // Note some conditions are synonyms for others |
duke@435 | 5066 | case Assembler::zero: return Assembler::notZero; |
duke@435 | 5067 | case Assembler::notZero: return Assembler::zero; |
duke@435 | 5068 | case Assembler::less: return Assembler::greaterEqual; |
duke@435 | 5069 | case Assembler::lessEqual: return Assembler::greater; |
duke@435 | 5070 | case Assembler::greater: return Assembler::lessEqual; |
duke@435 | 5071 | case Assembler::greaterEqual: return Assembler::less; |
duke@435 | 5072 | case Assembler::below: return Assembler::aboveEqual; |
duke@435 | 5073 | case Assembler::belowEqual: return Assembler::above; |
duke@435 | 5074 | case Assembler::above: return Assembler::belowEqual; |
duke@435 | 5075 | case Assembler::aboveEqual: return Assembler::below; |
duke@435 | 5076 | case Assembler::overflow: return Assembler::noOverflow; |
duke@435 | 5077 | case Assembler::noOverflow: return Assembler::overflow; |
duke@435 | 5078 | case Assembler::negative: return Assembler::positive; |
duke@435 | 5079 | case Assembler::positive: return Assembler::negative; |
duke@435 | 5080 | case Assembler::parity: return Assembler::noParity; |
duke@435 | 5081 | case Assembler::noParity: return Assembler::parity; |
duke@435 | 5082 | } |
duke@435 | 5083 | ShouldNotReachHere(); return Assembler::overflow; |
duke@435 | 5084 | } |
duke@435 | 5085 | |
duke@435 | 5086 | |
duke@435 | 5087 | void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { |
duke@435 | 5088 | Condition negated_cond = negate_condition(cond); |
duke@435 | 5089 | Label L; |
duke@435 | 5090 | jcc(negated_cond, L); |
duke@435 | 5091 | atomic_incl(counter_addr); |
duke@435 | 5092 | bind(L); |
duke@435 | 5093 | } |
duke@435 | 5094 | |
duke@435 | 5095 | void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { |
duke@435 | 5096 | pushfd(); |
duke@435 | 5097 | if (os::is_MP()) |
duke@435 | 5098 | lock(); |
duke@435 | 5099 | increment(counter_addr); |
duke@435 | 5100 | popfd(); |
duke@435 | 5101 | } |
duke@435 | 5102 | |
duke@435 | 5103 | SkipIfEqual::SkipIfEqual( |
duke@435 | 5104 | MacroAssembler* masm, const bool* flag_addr, bool value) { |
duke@435 | 5105 | _masm = masm; |
duke@435 | 5106 | _masm->cmp8(ExternalAddress((address)flag_addr), value); |
duke@435 | 5107 | _masm->jcc(Assembler::equal, _label); |
duke@435 | 5108 | } |
duke@435 | 5109 | |
duke@435 | 5110 | SkipIfEqual::~SkipIfEqual() { |
duke@435 | 5111 | _masm->bind(_label); |
duke@435 | 5112 | } |
duke@435 | 5113 | |
duke@435 | 5114 | |
duke@435 | 5115 | // Writes to stack successive pages until offset reached to check for |
duke@435 | 5116 | // stack overflow + shadow pages. This clobbers tmp. |
duke@435 | 5117 | void MacroAssembler::bang_stack_size(Register size, Register tmp) { |
duke@435 | 5118 | movl(tmp, rsp); |
duke@435 | 5119 | // Bang stack for total size given plus shadow page size. |
duke@435 | 5120 | // Bang one page at a time because large size can bang beyond yellow and |
duke@435 | 5121 | // red zones. |
duke@435 | 5122 | Label loop; |
duke@435 | 5123 | bind(loop); |
duke@435 | 5124 | movl(Address(tmp, (-os::vm_page_size())), size ); |
duke@435 | 5125 | subl(tmp, os::vm_page_size()); |
duke@435 | 5126 | subl(size, os::vm_page_size()); |
duke@435 | 5127 | jcc(Assembler::greater, loop); |
duke@435 | 5128 | |
duke@435 | 5129 | // Bang down shadow pages too. |
duke@435 | 5130 | // The -1 because we already subtracted 1 page. |
duke@435 | 5131 | for (int i = 0; i< StackShadowPages-1; i++) { |
duke@435 | 5132 | movl(Address(tmp, (-i*os::vm_page_size())), size ); |
duke@435 | 5133 | } |
duke@435 | 5134 | } |