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src/cpu/x86/vm/c1_FrameMap_x86.hpp@18a08a7e16b5 (annotated)

src/cpu/x86/vm/c1_FrameMap_x86.hpp

Fri, 26 Jun 2009 07:26:10 -0700

author

twisti

date

Fri, 26 Jun 2009 07:26:10 -0700

changeset 1259

18a08a7e16b5

parent 772

9ee9cf798b59

child 1736

fc2c71045ada

permissions

-rw-r--r--

5057225: Remove useless I2L conversions
Summary: The optimizer should be told to normalize (AndL (ConvI2L x) 0xFF) to (ConvI2L (AndI x 0xFF)), and then the existing matcher rule will work for free.
Reviewed-by: kvn

duke@435	1	/*
xdono@772	2	* Copyright 1999-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
duke@435	19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@435	20	* CA 95054 USA or visit www.sun.com if you need additional information or
duke@435	21	* have any questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
duke@435	25	// On i486 the frame looks as follows:
duke@435	26	//
duke@435	27	// +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435	28	// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
duke@435	29	// +-----------------------------+---------+----------------------------------------+----------------+-----------
duke@435	30	//
duke@435	31	// The FPU registers are mapped with their offset from TOS; therefore the
duke@435	32	// status of FPU stack must be updated during code emission.
duke@435	33
duke@435	34	public:
duke@435	35	static const int pd_c_runtime_reserved_arg_size;
duke@435	36
duke@435	37	enum {
duke@435	38	nof_xmm_regs = pd_nof_xmm_regs_frame_map,
duke@435	39	nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
duke@435	40	first_available_sp_in_frame = 0,
never@739	41	#ifndef _LP64
duke@435	42	frame_pad_in_bytes = 8,
duke@435	43	nof_reg_args = 2
never@739	44	#else
never@739	45	frame_pad_in_bytes = 16,
never@739	46	nof_reg_args = 6
never@739	47	#endif // _LP64
duke@435	48	};
duke@435	49
duke@435	50	private:
duke@435	51	static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs];
duke@435	52
duke@435	53	static XMMRegister _xmm_regs[nof_xmm_regs];
duke@435	54
duke@435	55	public:
duke@435	56	static LIR_Opr receiver_opr;
duke@435	57
duke@435	58	static LIR_Opr rsi_opr;
duke@435	59	static LIR_Opr rdi_opr;
duke@435	60	static LIR_Opr rbx_opr;
duke@435	61	static LIR_Opr rax_opr;
duke@435	62	static LIR_Opr rdx_opr;
duke@435	63	static LIR_Opr rcx_opr;
duke@435	64	static LIR_Opr rsp_opr;
duke@435	65	static LIR_Opr rbp_opr;
duke@435	66
duke@435	67	static LIR_Opr rsi_oop_opr;
duke@435	68	static LIR_Opr rdi_oop_opr;
duke@435	69	static LIR_Opr rbx_oop_opr;
duke@435	70	static LIR_Opr rax_oop_opr;
duke@435	71	static LIR_Opr rdx_oop_opr;
duke@435	72	static LIR_Opr rcx_oop_opr;
never@739	73	#ifdef _LP64
duke@435	74
never@739	75	static LIR_Opr r8_opr;
never@739	76	static LIR_Opr r9_opr;
never@739	77	static LIR_Opr r10_opr;
never@739	78	static LIR_Opr r11_opr;
never@739	79	static LIR_Opr r12_opr;
never@739	80	static LIR_Opr r13_opr;
never@739	81	static LIR_Opr r14_opr;
never@739	82	static LIR_Opr r15_opr;
never@739	83
never@739	84	static LIR_Opr r8_oop_opr;
never@739	85	static LIR_Opr r9_oop_opr;
never@739	86
never@739	87	static LIR_Opr r11_oop_opr;
never@739	88	static LIR_Opr r12_oop_opr;
never@739	89	static LIR_Opr r13_oop_opr;
never@739	90	static LIR_Opr r14_oop_opr;
never@739	91
never@739	92	#endif // _LP64
never@739	93
never@739	94	static LIR_Opr long0_opr;
never@739	95	static LIR_Opr long1_opr;
duke@435	96	static LIR_Opr fpu0_float_opr;
duke@435	97	static LIR_Opr fpu0_double_opr;
duke@435	98	static LIR_Opr xmm0_float_opr;
duke@435	99	static LIR_Opr xmm0_double_opr;
duke@435	100
never@739	101	#ifdef _LP64
never@739	102	static LIR_Opr as_long_opr(Register r) {
never@739	103	return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
never@739	104	}
never@739	105	static LIR_Opr as_pointer_opr(Register r) {
never@739	106	return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
never@739	107	}
never@739	108	#else
duke@435	109	static LIR_Opr as_long_opr(Register r, Register r2) {
duke@435	110	return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
duke@435	111	}
never@739	112	static LIR_Opr as_pointer_opr(Register r) {
never@739	113	return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
never@739	114	}
never@739	115	#endif // _LP64
duke@435	116
duke@435	117	// VMReg name for spilled physical FPU stack slot n
duke@435	118	static VMReg fpu_regname (int n);
duke@435	119
duke@435	120	static XMMRegister nr2xmmreg(int rnr);
duke@435	121
duke@435	122	static bool is_caller_save_register (LIR_Opr opr) { return true; }
duke@435	123	static bool is_caller_save_register (Register r) { return true; }
duke@435	124
duke@435	125	static LIR_Opr caller_save_xmm_reg_at(int i) {
duke@435	126	assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
duke@435	127	return _caller_save_xmm_regs[i];
duke@435	128	}