Mon, 09 Mar 2009 13:28:46 -0700
6814575: Update copyright year
Summary: Update copyright for files that have been modified in 2009, up to 03/09
Reviewed-by: katleman, tbell, ohair
duke@435 | 1 | /* |
xdono@631 | 2 | * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_vm_version_x86_64.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | int VM_Version::_cpu; |
duke@435 | 29 | int VM_Version::_model; |
duke@435 | 30 | int VM_Version::_stepping; |
duke@435 | 31 | int VM_Version::_cpuFeatures; |
duke@435 | 32 | const char* VM_Version::_features_str = ""; |
duke@435 | 33 | VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
duke@435 | 34 | |
duke@435 | 35 | static BufferBlob* stub_blob; |
duke@435 | 36 | static const int stub_size = 300; |
duke@435 | 37 | |
duke@435 | 38 | extern "C" { |
duke@435 | 39 | typedef void (*getPsrInfo_stub_t)(void*); |
duke@435 | 40 | } |
duke@435 | 41 | static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
duke@435 | 42 | |
duke@435 | 43 | |
duke@435 | 44 | class VM_Version_StubGenerator: public StubCodeGenerator { |
duke@435 | 45 | public: |
duke@435 | 46 | |
duke@435 | 47 | VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
duke@435 | 48 | |
duke@435 | 49 | address generate_getPsrInfo() { |
duke@435 | 50 | |
duke@435 | 51 | Label std_cpuid1, ext_cpuid1, ext_cpuid5, done; |
duke@435 | 52 | |
duke@435 | 53 | StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
duke@435 | 54 | # define __ _masm-> |
duke@435 | 55 | |
duke@435 | 56 | address start = __ pc(); |
duke@435 | 57 | |
duke@435 | 58 | // |
duke@435 | 59 | // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
duke@435 | 60 | // |
duke@435 | 61 | // rcx and rdx are first and second argument registers on windows |
duke@435 | 62 | |
never@739 | 63 | __ push(rbp); |
never@739 | 64 | __ mov(rbp, c_rarg0); // cpuid_info address |
never@739 | 65 | __ push(rbx); |
never@739 | 66 | __ push(rsi); |
duke@435 | 67 | |
duke@435 | 68 | // |
duke@435 | 69 | // we have a chip which supports the "cpuid" instruction |
duke@435 | 70 | // |
duke@435 | 71 | __ xorl(rax, rax); |
duke@435 | 72 | __ cpuid(); |
never@739 | 73 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
duke@435 | 74 | __ movl(Address(rsi, 0), rax); |
duke@435 | 75 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 76 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 77 | __ movl(Address(rsi,12), rdx); |
duke@435 | 78 | |
duke@435 | 79 | __ cmpl(rax, 3); // Is cpuid(0x4) supported? |
duke@435 | 80 | __ jccb(Assembler::belowEqual, std_cpuid1); |
duke@435 | 81 | |
duke@435 | 82 | // |
duke@435 | 83 | // cpuid(0x4) Deterministic cache params |
duke@435 | 84 | // |
duke@435 | 85 | __ movl(rax, 4); |
duke@435 | 86 | __ xorl(rcx, rcx); // L1 cache |
duke@435 | 87 | __ cpuid(); |
never@739 | 88 | __ push(rax); |
duke@435 | 89 | __ andl(rax, 0x1f); // Determine if valid cache parameters used |
duke@435 | 90 | __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
never@739 | 91 | __ pop(rax); |
duke@435 | 92 | __ jccb(Assembler::equal, std_cpuid1); |
duke@435 | 93 | |
never@739 | 94 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
duke@435 | 95 | __ movl(Address(rsi, 0), rax); |
duke@435 | 96 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 97 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 98 | __ movl(Address(rsi,12), rdx); |
duke@435 | 99 | |
duke@435 | 100 | // |
duke@435 | 101 | // Standard cpuid(0x1) |
duke@435 | 102 | // |
duke@435 | 103 | __ bind(std_cpuid1); |
duke@435 | 104 | __ movl(rax, 1); |
duke@435 | 105 | __ cpuid(); |
never@739 | 106 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
duke@435 | 107 | __ movl(Address(rsi, 0), rax); |
duke@435 | 108 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 109 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 110 | __ movl(Address(rsi,12), rdx); |
duke@435 | 111 | |
duke@435 | 112 | __ movl(rax, 0x80000000); |
duke@435 | 113 | __ cpuid(); |
duke@435 | 114 | __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
duke@435 | 115 | __ jcc(Assembler::belowEqual, done); |
duke@435 | 116 | __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
duke@435 | 117 | __ jccb(Assembler::belowEqual, ext_cpuid1); |
duke@435 | 118 | __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
duke@435 | 119 | __ jccb(Assembler::belowEqual, ext_cpuid5); |
duke@435 | 120 | // |
duke@435 | 121 | // Extended cpuid(0x80000008) |
duke@435 | 122 | // |
duke@435 | 123 | __ movl(rax, 0x80000008); |
duke@435 | 124 | __ cpuid(); |
never@739 | 125 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
duke@435 | 126 | __ movl(Address(rsi, 0), rax); |
duke@435 | 127 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 128 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 129 | __ movl(Address(rsi,12), rdx); |
duke@435 | 130 | |
duke@435 | 131 | // |
duke@435 | 132 | // Extended cpuid(0x80000005) |
duke@435 | 133 | // |
duke@435 | 134 | __ bind(ext_cpuid5); |
duke@435 | 135 | __ movl(rax, 0x80000005); |
duke@435 | 136 | __ cpuid(); |
never@739 | 137 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
duke@435 | 138 | __ movl(Address(rsi, 0), rax); |
duke@435 | 139 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 140 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 141 | __ movl(Address(rsi,12), rdx); |
duke@435 | 142 | |
duke@435 | 143 | // |
duke@435 | 144 | // Extended cpuid(0x80000001) |
duke@435 | 145 | // |
duke@435 | 146 | __ bind(ext_cpuid1); |
duke@435 | 147 | __ movl(rax, 0x80000001); |
duke@435 | 148 | __ cpuid(); |
never@739 | 149 | __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
duke@435 | 150 | __ movl(Address(rsi, 0), rax); |
duke@435 | 151 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 152 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 153 | __ movl(Address(rsi,12), rdx); |
duke@435 | 154 | |
duke@435 | 155 | // |
duke@435 | 156 | // return |
duke@435 | 157 | // |
duke@435 | 158 | __ bind(done); |
never@739 | 159 | __ pop(rsi); |
never@739 | 160 | __ pop(rbx); |
never@739 | 161 | __ pop(rbp); |
duke@435 | 162 | __ ret(0); |
duke@435 | 163 | |
duke@435 | 164 | # undef __ |
duke@435 | 165 | |
duke@435 | 166 | return start; |
duke@435 | 167 | }; |
duke@435 | 168 | }; |
duke@435 | 169 | |
duke@435 | 170 | |
duke@435 | 171 | void VM_Version::get_processor_features() { |
duke@435 | 172 | |
duke@435 | 173 | _logical_processors_per_package = 1; |
duke@435 | 174 | // Get raw processor info |
duke@435 | 175 | getPsrInfo_stub(&_cpuid_info); |
duke@435 | 176 | assert_is_initialized(); |
duke@435 | 177 | _cpu = extended_cpu_family(); |
duke@435 | 178 | _model = extended_cpu_model(); |
duke@435 | 179 | _stepping = cpu_stepping(); |
duke@435 | 180 | _cpuFeatures = feature_flags(); |
duke@435 | 181 | // Logical processors are only available on P4s and above, |
duke@435 | 182 | // and only if hyperthreading is available. |
duke@435 | 183 | _logical_processors_per_package = logical_processor_count(); |
duke@435 | 184 | _supports_cx8 = supports_cmpxchg8(); |
duke@435 | 185 | // OS should support SSE for x64 and hardware should support at least SSE2. |
duke@435 | 186 | if (!VM_Version::supports_sse2()) { |
duke@435 | 187 | vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
duke@435 | 188 | } |
kvn@840 | 189 | if (UseSSE < 4) { |
kvn@840 | 190 | _cpuFeatures &= ~CPU_SSE4_1; |
kvn@840 | 191 | _cpuFeatures &= ~CPU_SSE4_2; |
kvn@840 | 192 | } |
duke@435 | 193 | if (UseSSE < 3) { |
duke@435 | 194 | _cpuFeatures &= ~CPU_SSE3; |
duke@435 | 195 | _cpuFeatures &= ~CPU_SSSE3; |
duke@435 | 196 | _cpuFeatures &= ~CPU_SSE4A; |
duke@435 | 197 | } |
duke@435 | 198 | if (UseSSE < 2) |
duke@435 | 199 | _cpuFeatures &= ~CPU_SSE2; |
duke@435 | 200 | if (UseSSE < 1) |
duke@435 | 201 | _cpuFeatures &= ~CPU_SSE; |
duke@435 | 202 | |
duke@435 | 203 | if (logical_processors_per_package() == 1) { |
duke@435 | 204 | // HT processor could be installed on a system which doesn't support HT. |
duke@435 | 205 | _cpuFeatures &= ~CPU_HT; |
duke@435 | 206 | } |
duke@435 | 207 | |
duke@435 | 208 | char buf[256]; |
kvn@840 | 209 | jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
duke@435 | 210 | cores_per_cpu(), threads_per_core(), |
duke@435 | 211 | cpu_family(), _model, _stepping, |
duke@435 | 212 | (supports_cmov() ? ", cmov" : ""), |
duke@435 | 213 | (supports_cmpxchg8() ? ", cx8" : ""), |
duke@435 | 214 | (supports_fxsr() ? ", fxsr" : ""), |
duke@435 | 215 | (supports_mmx() ? ", mmx" : ""), |
duke@435 | 216 | (supports_sse() ? ", sse" : ""), |
duke@435 | 217 | (supports_sse2() ? ", sse2" : ""), |
duke@435 | 218 | (supports_sse3() ? ", sse3" : ""), |
duke@435 | 219 | (supports_ssse3()? ", ssse3": ""), |
kvn@840 | 220 | (supports_sse4_1() ? ", sse4.1" : ""), |
kvn@840 | 221 | (supports_sse4_2() ? ", sse4.2" : ""), |
duke@435 | 222 | (supports_mmx_ext() ? ", mmxext" : ""), |
duke@435 | 223 | (supports_3dnow() ? ", 3dnow" : ""), |
duke@435 | 224 | (supports_3dnow2() ? ", 3dnowext" : ""), |
duke@435 | 225 | (supports_sse4a() ? ", sse4a": ""), |
duke@435 | 226 | (supports_ht() ? ", ht": "")); |
duke@435 | 227 | _features_str = strdup(buf); |
duke@435 | 228 | |
duke@435 | 229 | // UseSSE is set to the smaller of what hardware supports and what |
duke@435 | 230 | // the command line requires. I.e., you cannot set UseSSE to 2 on |
duke@435 | 231 | // older Pentiums which do not support it. |
duke@435 | 232 | if( UseSSE > 4 ) UseSSE=4; |
duke@435 | 233 | if( UseSSE < 0 ) UseSSE=0; |
kvn@840 | 234 | if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support |
duke@435 | 235 | UseSSE = MIN2((intx)3,UseSSE); |
duke@435 | 236 | if( !supports_sse3() ) // Drop to 2 if no SSE3 support |
duke@435 | 237 | UseSSE = MIN2((intx)2,UseSSE); |
duke@435 | 238 | if( !supports_sse2() ) // Drop to 1 if no SSE2 support |
duke@435 | 239 | UseSSE = MIN2((intx)1,UseSSE); |
duke@435 | 240 | if( !supports_sse () ) // Drop to 0 if no SSE support |
duke@435 | 241 | UseSSE = 0; |
duke@435 | 242 | |
duke@435 | 243 | // On new cpus instructions which update whole XMM register should be used |
duke@435 | 244 | // to prevent partial register stall due to dependencies on high half. |
duke@435 | 245 | // |
duke@435 | 246 | // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
duke@435 | 247 | // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
duke@435 | 248 | // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
duke@435 | 249 | // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
duke@435 | 250 | |
duke@435 | 251 | if( is_amd() ) { // AMD cpus specific settings |
duke@435 | 252 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
duke@435 | 253 | // Use it on all AMD cpus starting from Opteron (don't need |
duke@435 | 254 | // a cpu check since only Opteron and new cpus support 64-bits mode). |
duke@435 | 255 | UseAddressNop = true; |
duke@435 | 256 | } |
duke@435 | 257 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
duke@435 | 258 | if( supports_sse4a() ) { |
duke@435 | 259 | UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
duke@435 | 260 | } else { |
duke@435 | 261 | UseXmmLoadAndClearUpper = false; |
duke@435 | 262 | } |
duke@435 | 263 | } |
duke@435 | 264 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
duke@435 | 265 | if( supports_sse4a() ) { |
duke@435 | 266 | UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
duke@435 | 267 | } else { |
duke@435 | 268 | UseXmmRegToRegMoveAll = false; |
duke@435 | 269 | } |
duke@435 | 270 | } |
kvn@506 | 271 | if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
kvn@506 | 272 | if( supports_sse4a() ) { |
kvn@506 | 273 | UseXmmI2F = true; |
kvn@506 | 274 | } else { |
kvn@506 | 275 | UseXmmI2F = false; |
kvn@506 | 276 | } |
kvn@506 | 277 | } |
kvn@506 | 278 | if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
kvn@506 | 279 | if( supports_sse4a() ) { |
kvn@506 | 280 | UseXmmI2D = true; |
kvn@506 | 281 | } else { |
kvn@506 | 282 | UseXmmI2D = false; |
kvn@506 | 283 | } |
kvn@506 | 284 | } |
duke@435 | 285 | } |
duke@435 | 286 | |
duke@435 | 287 | if( is_intel() ) { // Intel cpus specific settings |
duke@435 | 288 | if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
duke@435 | 289 | UseStoreImmI16 = false; // don't use it on Intel cpus |
duke@435 | 290 | } |
duke@435 | 291 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
duke@435 | 292 | // Use it on all Intel cpus starting from PentiumPro |
duke@435 | 293 | // (don't need a cpu check since only new cpus support 64-bits mode). |
duke@435 | 294 | UseAddressNop = true; |
duke@435 | 295 | } |
duke@435 | 296 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
duke@435 | 297 | UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
duke@435 | 298 | } |
duke@435 | 299 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
duke@435 | 300 | if( supports_sse3() ) { |
duke@435 | 301 | UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
duke@435 | 302 | } else { |
duke@435 | 303 | UseXmmRegToRegMoveAll = false; |
duke@435 | 304 | } |
duke@435 | 305 | } |
duke@435 | 306 | if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
duke@435 | 307 | #ifdef COMPILER2 |
duke@435 | 308 | if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
duke@435 | 309 | // For new Intel cpus do the next optimization: |
duke@435 | 310 | // don't align the beginning of a loop if there are enough instructions |
duke@435 | 311 | // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
duke@435 | 312 | // in current fetch line (OptoLoopAlignment) or the padding |
duke@435 | 313 | // is big (> MaxLoopPad). |
duke@435 | 314 | // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
duke@435 | 315 | // generated NOP instructions. 11 is the largest size of one |
duke@435 | 316 | // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
duke@435 | 317 | MaxLoopPad = 11; |
duke@435 | 318 | } |
duke@435 | 319 | #endif // COMPILER2 |
kvn@840 | 320 | if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
kvn@840 | 321 | UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
kvn@840 | 322 | } |
kvn@840 | 323 | if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus |
kvn@840 | 324 | if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
kvn@840 | 325 | UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
kvn@840 | 326 | } |
kvn@840 | 327 | } |
duke@435 | 328 | } |
duke@435 | 329 | } |
duke@435 | 330 | |
duke@435 | 331 | assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
duke@435 | 332 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
duke@435 | 333 | |
duke@435 | 334 | // set valid Prefetch instruction |
duke@435 | 335 | if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
duke@435 | 336 | if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
duke@435 | 337 | if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; |
duke@435 | 338 | |
duke@435 | 339 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
duke@435 | 340 | if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
duke@435 | 341 | if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; |
duke@435 | 342 | |
duke@435 | 343 | // Allocation prefetch settings |
duke@435 | 344 | intx cache_line_size = L1_data_cache_line_size(); |
duke@435 | 345 | if( cache_line_size > AllocatePrefetchStepSize ) |
duke@435 | 346 | AllocatePrefetchStepSize = cache_line_size; |
duke@435 | 347 | if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) |
duke@435 | 348 | AllocatePrefetchLines = 3; // Optimistic value |
duke@435 | 349 | assert(AllocatePrefetchLines > 0, "invalid value"); |
duke@435 | 350 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
duke@435 | 351 | AllocatePrefetchLines = 1; // Conservative value |
duke@435 | 352 | |
duke@435 | 353 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
duke@435 | 354 | AllocatePrefetchStyle = allocate_prefetch_style(); |
duke@435 | 355 | |
duke@435 | 356 | if( AllocatePrefetchStyle == 2 && is_intel() && |
duke@435 | 357 | cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core |
duke@435 | 358 | AllocatePrefetchDistance = 384; |
duke@435 | 359 | } |
duke@435 | 360 | assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
duke@435 | 361 | |
duke@435 | 362 | // Prefetch settings |
duke@435 | 363 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
duke@435 | 364 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
duke@435 | 365 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
duke@435 | 366 | |
duke@435 | 367 | #ifndef PRODUCT |
duke@435 | 368 | if (PrintMiscellaneous && Verbose) { |
kvn@840 | 369 | tty->print_cr("Logical CPUs per core: %u", |
duke@435 | 370 | logical_processors_per_package()); |
duke@435 | 371 | tty->print_cr("UseSSE=%d",UseSSE); |
duke@435 | 372 | tty->print("Allocation: "); |
duke@435 | 373 | if (AllocatePrefetchStyle <= 0) { |
duke@435 | 374 | tty->print_cr("no prefetching"); |
duke@435 | 375 | } else { |
duke@435 | 376 | if (AllocatePrefetchInstr == 0) { |
duke@435 | 377 | tty->print("PREFETCHNTA"); |
duke@435 | 378 | } else if (AllocatePrefetchInstr == 1) { |
duke@435 | 379 | tty->print("PREFETCHT0"); |
duke@435 | 380 | } else if (AllocatePrefetchInstr == 2) { |
duke@435 | 381 | tty->print("PREFETCHT2"); |
duke@435 | 382 | } else if (AllocatePrefetchInstr == 3) { |
duke@435 | 383 | tty->print("PREFETCHW"); |
duke@435 | 384 | } |
duke@435 | 385 | if (AllocatePrefetchLines > 1) { |
duke@435 | 386 | tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
duke@435 | 387 | } else { |
duke@435 | 388 | tty->print_cr(" %d, one line", AllocatePrefetchDistance); |
duke@435 | 389 | } |
duke@435 | 390 | } |
duke@435 | 391 | if (PrefetchCopyIntervalInBytes > 0) { |
duke@435 | 392 | tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); |
duke@435 | 393 | } |
duke@435 | 394 | if (PrefetchScanIntervalInBytes > 0) { |
duke@435 | 395 | tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); |
duke@435 | 396 | } |
duke@435 | 397 | if (PrefetchFieldsAhead > 0) { |
duke@435 | 398 | tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); |
duke@435 | 399 | } |
duke@435 | 400 | } |
duke@435 | 401 | #endif // !PRODUCT |
duke@435 | 402 | } |
duke@435 | 403 | |
duke@435 | 404 | void VM_Version::initialize() { |
duke@435 | 405 | ResourceMark rm; |
duke@435 | 406 | // Making this stub must be FIRST use of assembler |
duke@435 | 407 | |
duke@435 | 408 | stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
duke@435 | 409 | if (stub_blob == NULL) { |
duke@435 | 410 | vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
duke@435 | 411 | } |
duke@435 | 412 | CodeBuffer c(stub_blob->instructions_begin(), |
duke@435 | 413 | stub_blob->instructions_size()); |
duke@435 | 414 | VM_Version_StubGenerator g(&c); |
duke@435 | 415 | getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
duke@435 | 416 | g.generate_getPsrInfo()); |
duke@435 | 417 | |
duke@435 | 418 | get_processor_features(); |
duke@435 | 419 | } |