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src/cpu/ppc/vm/vmreg_ppc.inline.hpp@04ff2f6cd0eb (annotated)
src/cpu/ppc/vm/vmreg_ppc.inline.hpp
Tue, 17 Oct 2017 12:58:25 +0800
- author
- aoqi
- date
- Tue, 17 Oct 2017 12:58:25 +0800
- changeset 7994
- 04ff2f6cd0eb
- parent 0
- f90c822e73f8
- permissions
- -rw-r--r--
merge
| aoqi@0 | 1 | /* |
| aoqi@0 | 2 | * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. |
| aoqi@0 | 3 | * Copyright 2012, 2013 SAP AG. All rights reserved. |
| aoqi@0 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@0 | 5 | * |
| aoqi@0 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@0 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@0 | 8 | * published by the Free Software Foundation. |
| aoqi@0 | 9 | * |
| aoqi@0 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@0 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@0 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@0 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@0 | 14 | * accompanied this code). |
| aoqi@0 | 15 | * |
| aoqi@0 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@0 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@0 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@0 | 19 | * |
| aoqi@0 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@0 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@0 | 22 | * questions. |
| aoqi@0 | 23 | * |
| aoqi@0 | 24 | */ |
| aoqi@0 | 25 | |
| aoqi@0 | 26 | #ifndef CPU_PPC_VM_VMREG_PPC_INLINE_HPP |
| aoqi@0 | 27 | #define CPU_PPC_VM_VMREG_PPC_INLINE_HPP |
| aoqi@0 | 28 | |
| aoqi@0 | 29 | inline VMReg RegisterImpl::as_VMReg() { |
| aoqi@0 | 30 | if (this == noreg) return VMRegImpl::Bad(); |
| aoqi@0 | 31 | return VMRegImpl::as_VMReg(encoding() << 1); |
| aoqi@0 | 32 | } |
| aoqi@0 | 33 | |
| aoqi@0 | 34 | // Since we don't have two halfs here, don't multiply by 2. |
| aoqi@0 | 35 | inline VMReg ConditionRegisterImpl::as_VMReg() { |
| aoqi@0 | 36 | return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_fpr); |
| aoqi@0 | 37 | } |
| aoqi@0 | 38 | |
| aoqi@0 | 39 | inline VMReg FloatRegisterImpl::as_VMReg() { |
| aoqi@0 | 40 | return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); |
| aoqi@0 | 41 | } |
| aoqi@0 | 42 | |
| aoqi@0 | 43 | inline VMReg SpecialRegisterImpl::as_VMReg() { |
| aoqi@0 | 44 | return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_cnd); |
| aoqi@0 | 45 | } |
| aoqi@0 | 46 | |
| aoqi@0 | 47 | inline bool VMRegImpl::is_Register() { |
| aoqi@0 | 48 | return (unsigned int)value() < (unsigned int)ConcreteRegisterImpl::max_gpr; |
| aoqi@0 | 49 | } |
| aoqi@0 | 50 | |
| aoqi@0 | 51 | inline bool VMRegImpl::is_FloatRegister() { |
| aoqi@0 | 52 | return value() >= ConcreteRegisterImpl::max_gpr && |
| aoqi@0 | 53 | value() < ConcreteRegisterImpl::max_fpr; |
| aoqi@0 | 54 | } |
| aoqi@0 | 55 | |
| aoqi@0 | 56 | inline Register VMRegImpl::as_Register() { |
| aoqi@0 | 57 | assert(is_Register() && is_even(value()), "even-aligned GPR name"); |
| aoqi@0 | 58 | return ::as_Register(value()>>1); |
| aoqi@0 | 59 | } |
| aoqi@0 | 60 | |
| aoqi@0 | 61 | inline FloatRegister VMRegImpl::as_FloatRegister() { |
| aoqi@0 | 62 | assert(is_FloatRegister() && is_even(value()), "must be"); |
| aoqi@0 | 63 | return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); |
| aoqi@0 | 64 | } |
| aoqi@0 | 65 | |
| aoqi@0 | 66 | inline bool VMRegImpl::is_concrete() { |
| aoqi@0 | 67 | assert(is_reg(), "must be"); |
| aoqi@0 | 68 | return is_even(value()); |
| aoqi@0 | 69 | } |
| aoqi@0 | 70 | |
| aoqi@0 | 71 | #endif // CPU_PPC_VM_VMREG_PPC_INLINE_HPP |
