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src/cpu/ppc/vm/register_ppc.hpp@04ff2f6cd0eb (annotated)

src/cpu/ppc/vm/register_ppc.hpp

Tue, 17 Oct 2017 12:58:25 +0800

author
aoqi
date
Tue, 17 Oct 2017 12:58:25 +0800
changeset 7994
04ff2f6cd0eb
parent 6876
710a3c8b516e
child 9703
2fdf635bcf28
permissions
-rw-r--r--

merge

aoqi@0 1 /*
aoqi@0 2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0 3 * Copyright 2012, 2014 SAP AG. All rights reserved.
aoqi@0 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0 5 *
aoqi@0 6 * This code is free software; you can redistribute it and/or modify it
aoqi@0 7 * under the terms of the GNU General Public License version 2 only, as
aoqi@0 8 * published by the Free Software Foundation.
aoqi@0 9 *
aoqi@0 10 * This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0 13 * version 2 for more details (a copy is included in the LICENSE file that
aoqi@0 14 * accompanied this code).
aoqi@0 15 *
aoqi@0 16 * You should have received a copy of the GNU General Public License version
aoqi@0 17 * 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0 19 *
aoqi@0 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0 21 * or visit www.oracle.com if you need additional information or have any
aoqi@0 22 * questions.
aoqi@0 23 *
aoqi@0 24 */
aoqi@0 25
aoqi@0 26 #ifndef CPU_PPC_VM_REGISTER_PPC_HPP
aoqi@0 27 #define CPU_PPC_VM_REGISTER_PPC_HPP
aoqi@0 28
aoqi@0 29 #include "asm/register.hpp"
aoqi@0 30 #include "vm_version_ppc.hpp"
aoqi@0 31
aoqi@0 32 // forward declaration
aoqi@0 33 class Address;
aoqi@0 34 class VMRegImpl;
aoqi@0 35 typedef VMRegImpl* VMReg;
aoqi@0 36
aoqi@0 37 // PPC64 registers
aoqi@0 38 //
aoqi@0 39 // See "64-bit PowerPC ELF ABI Supplement 1.7", IBM Corp. (2003-10-29).
aoqi@0 40 // (http://math-atlas.sourceforge.net/devel/assembly/PPC-elf64abi-1.7.pdf)
aoqi@0 41 //
aoqi@0 42 // r0 Register used in function prologs (volatile)
aoqi@0 43 // r1 Stack pointer (nonvolatile)
aoqi@0 44 // r2 TOC pointer (volatile)
aoqi@0 45 // r3 Parameter and return value (volatile)
aoqi@0 46 // r4-r10 Function parameters (volatile)
aoqi@0 47 // r11 Register used in calls by pointer and as an environment pointer for languages which require one (volatile)
aoqi@0 48 // r12 Register used for exception handling and glink code (volatile)
aoqi@0 49 // r13 Reserved for use as system thread ID
aoqi@0 50 // r14-r31 Local variables (nonvolatile)
aoqi@0 51 //
aoqi@0 52 // f0 Scratch register (volatile)
aoqi@0 53 // f1-f4 Floating point parameters and return value (volatile)
aoqi@0 54 // f5-f13 Floating point parameters (volatile)
aoqi@0 55 // f14-f31 Floating point values (nonvolatile)
aoqi@0 56 //
aoqi@0 57 // LR Link register for return address (volatile)
aoqi@0 58 // CTR Loop counter (volatile)
aoqi@0 59 // XER Fixed point exception register (volatile)
aoqi@0 60 // FPSCR Floating point status and control register (volatile)
aoqi@0 61 //
aoqi@0 62 // CR0-CR1 Condition code fields (volatile)
aoqi@0 63 // CR2-CR4 Condition code fields (nonvolatile)
aoqi@0 64 // CR5-CR7 Condition code fields (volatile)
aoqi@0 65 //
aoqi@0 66 // ----------------------------------------------
aoqi@0 67 // On processors with the VMX feature:
aoqi@0 68 // v0-v1 Volatile scratch registers
aoqi@0 69 // v2-v13 Volatile vector parameters registers
aoqi@0 70 // v14-v19 Volatile scratch registers
aoqi@0 71 // v20-v31 Non-volatile registers
aoqi@0 72 // vrsave Non-volatile 32-bit register
aoqi@0 73
aoqi@0 74
aoqi@0 75 // Use Register as shortcut
aoqi@0 76 class RegisterImpl;
aoqi@0 77 typedef RegisterImpl* Register;
aoqi@0 78
aoqi@0 79 inline Register as_Register(int encoding) {
aoqi@0 80 assert(encoding >= 0 && encoding < 32, "bad register encoding");
aoqi@0 81 return (Register)(intptr_t)encoding;
aoqi@0 82 }
aoqi@0 83
aoqi@0 84 // The implementation of integer registers for the Power architecture
aoqi@0 85 class RegisterImpl: public AbstractRegisterImpl {
aoqi@0 86 public:
aoqi@0 87 enum {
aoqi@0 88 number_of_registers = 32
aoqi@0 89 };
aoqi@0 90
aoqi@0 91 // general construction
aoqi@0 92 inline friend Register as_Register(int encoding);
aoqi@0 93
aoqi@0 94 // accessors
aoqi@0 95 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
aoqi@0 96 VMReg as_VMReg();
aoqi@0 97 Register successor() const { return as_Register(encoding() + 1); }
aoqi@0 98
aoqi@0 99 // testers
aoqi@0 100 bool is_valid() const { return ( 0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); }
aoqi@0 101 bool is_volatile() const { return ( 0 <= (value()&0x7F) && (value()&0x7F) <= 13 ); }
aoqi@0 102 bool is_nonvolatile() const { return (14 <= (value()&0x7F) && (value()&0x7F) <= 31 ); }
aoqi@0 103
aoqi@0 104 const char* name() const;
aoqi@0 105 };
aoqi@0 106
aoqi@0 107 // The integer registers of the PPC architecture
aoqi@0 108 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
aoqi@0 109
aoqi@0 110 CONSTANT_REGISTER_DECLARATION(Register, R0, (0));
aoqi@0 111 CONSTANT_REGISTER_DECLARATION(Register, R1, (1));
aoqi@0 112 CONSTANT_REGISTER_DECLARATION(Register, R2, (2));
aoqi@0 113 CONSTANT_REGISTER_DECLARATION(Register, R3, (3));
aoqi@0 114 CONSTANT_REGISTER_DECLARATION(Register, R4, (4));
aoqi@0 115 CONSTANT_REGISTER_DECLARATION(Register, R5, (5));
aoqi@0 116 CONSTANT_REGISTER_DECLARATION(Register, R6, (6));
aoqi@0 117 CONSTANT_REGISTER_DECLARATION(Register, R7, (7));
aoqi@0 118 CONSTANT_REGISTER_DECLARATION(Register, R8, (8));
aoqi@0 119 CONSTANT_REGISTER_DECLARATION(Register, R9, (9));
aoqi@0 120 CONSTANT_REGISTER_DECLARATION(Register, R10, (10));
aoqi@0 121 CONSTANT_REGISTER_DECLARATION(Register, R11, (11));
aoqi@0 122 CONSTANT_REGISTER_DECLARATION(Register, R12, (12));
aoqi@0 123 CONSTANT_REGISTER_DECLARATION(Register, R13, (13));
aoqi@0 124 CONSTANT_REGISTER_DECLARATION(Register, R14, (14));
aoqi@0 125 CONSTANT_REGISTER_DECLARATION(Register, R15, (15));
aoqi@0 126 CONSTANT_REGISTER_DECLARATION(Register, R16, (16));
aoqi@0 127 CONSTANT_REGISTER_DECLARATION(Register, R17, (17));
aoqi@0 128 CONSTANT_REGISTER_DECLARATION(Register, R18, (18));
aoqi@0 129 CONSTANT_REGISTER_DECLARATION(Register, R19, (19));
aoqi@0 130 CONSTANT_REGISTER_DECLARATION(Register, R20, (20));
aoqi@0 131 CONSTANT_REGISTER_DECLARATION(Register, R21, (21));
aoqi@0 132 CONSTANT_REGISTER_DECLARATION(Register, R22, (22));
aoqi@0 133 CONSTANT_REGISTER_DECLARATION(Register, R23, (23));
aoqi@0 134 CONSTANT_REGISTER_DECLARATION(Register, R24, (24));
aoqi@0 135 CONSTANT_REGISTER_DECLARATION(Register, R25, (25));
aoqi@0 136 CONSTANT_REGISTER_DECLARATION(Register, R26, (26));
aoqi@0 137 CONSTANT_REGISTER_DECLARATION(Register, R27, (27));
aoqi@0 138 CONSTANT_REGISTER_DECLARATION(Register, R28, (28));
aoqi@0 139 CONSTANT_REGISTER_DECLARATION(Register, R29, (29));
aoqi@0 140 CONSTANT_REGISTER_DECLARATION(Register, R30, (30));
aoqi@0 141 CONSTANT_REGISTER_DECLARATION(Register, R31, (31));
aoqi@0 142
aoqi@0 143
aoqi@0 144 //
aoqi@0 145 // Because Power has many registers, #define'ing values for them is
aoqi@0 146 // beneficial in code size and is worth the cost of some of the
aoqi@0 147 // dangers of defines. If a particular file has a problem with these
aoqi@0 148 // defines then it's possible to turn them off in that file by
aoqi@0 149 // defining DONT_USE_REGISTER_DEFINES. Register_definition_ppc.cpp
aoqi@0 150 // does that so that it's able to provide real definitions of these
aoqi@0 151 // registers for use in debuggers and such.
aoqi@0 152 //
aoqi@0 153
aoqi@0 154 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 155 #define noreg ((Register)(noreg_RegisterEnumValue))
aoqi@0 156
aoqi@0 157 #define R0 ((Register)(R0_RegisterEnumValue))
aoqi@0 158 #define R1 ((Register)(R1_RegisterEnumValue))
aoqi@0 159 #define R2 ((Register)(R2_RegisterEnumValue))
aoqi@0 160 #define R3 ((Register)(R3_RegisterEnumValue))
aoqi@0 161 #define R4 ((Register)(R4_RegisterEnumValue))
aoqi@0 162 #define R5 ((Register)(R5_RegisterEnumValue))
aoqi@0 163 #define R6 ((Register)(R6_RegisterEnumValue))
aoqi@0 164 #define R7 ((Register)(R7_RegisterEnumValue))
aoqi@0 165 #define R8 ((Register)(R8_RegisterEnumValue))
aoqi@0 166 #define R9 ((Register)(R9_RegisterEnumValue))
aoqi@0 167 #define R10 ((Register)(R10_RegisterEnumValue))
aoqi@0 168 #define R11 ((Register)(R11_RegisterEnumValue))
aoqi@0 169 #define R12 ((Register)(R12_RegisterEnumValue))
aoqi@0 170 #define R13 ((Register)(R13_RegisterEnumValue))
aoqi@0 171 #define R14 ((Register)(R14_RegisterEnumValue))
aoqi@0 172 #define R15 ((Register)(R15_RegisterEnumValue))
aoqi@0 173 #define R16 ((Register)(R16_RegisterEnumValue))
aoqi@0 174 #define R17 ((Register)(R17_RegisterEnumValue))
aoqi@0 175 #define R18 ((Register)(R18_RegisterEnumValue))
aoqi@0 176 #define R19 ((Register)(R19_RegisterEnumValue))
aoqi@0 177 #define R20 ((Register)(R20_RegisterEnumValue))
aoqi@0 178 #define R21 ((Register)(R21_RegisterEnumValue))
aoqi@0 179 #define R22 ((Register)(R22_RegisterEnumValue))
aoqi@0 180 #define R23 ((Register)(R23_RegisterEnumValue))
aoqi@0 181 #define R24 ((Register)(R24_RegisterEnumValue))
aoqi@0 182 #define R25 ((Register)(R25_RegisterEnumValue))
aoqi@0 183 #define R26 ((Register)(R26_RegisterEnumValue))
aoqi@0 184 #define R27 ((Register)(R27_RegisterEnumValue))
aoqi@0 185 #define R28 ((Register)(R28_RegisterEnumValue))
aoqi@0 186 #define R29 ((Register)(R29_RegisterEnumValue))
aoqi@0 187 #define R30 ((Register)(R30_RegisterEnumValue))
aoqi@0 188 #define R31 ((Register)(R31_RegisterEnumValue))
aoqi@0 189 #endif
aoqi@0 190
aoqi@0 191 // Use ConditionRegister as shortcut
aoqi@0 192 class ConditionRegisterImpl;
aoqi@0 193 typedef ConditionRegisterImpl* ConditionRegister;
aoqi@0 194
aoqi@0 195 inline ConditionRegister as_ConditionRegister(int encoding) {
aoqi@0 196 assert(encoding >= 0 && encoding < 8, "bad condition register encoding");
aoqi@0 197 return (ConditionRegister)(intptr_t)encoding;
aoqi@0 198 }
aoqi@0 199
aoqi@0 200 // The implementation of condition register(s) for the PPC architecture
aoqi@0 201 class ConditionRegisterImpl: public AbstractRegisterImpl {
aoqi@0 202 public:
aoqi@0 203 enum {
aoqi@0 204 number_of_registers = 8
aoqi@0 205 };
aoqi@0 206
aoqi@0 207 // construction.
aoqi@0 208 inline friend ConditionRegister as_ConditionRegister(int encoding);
aoqi@0 209
aoqi@0 210 // accessors
aoqi@0 211 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
aoqi@0 212 VMReg as_VMReg();
aoqi@0 213
aoqi@0 214 // testers
aoqi@0 215 bool is_valid() const { return (0 <= value() && value() < number_of_registers); }
aoqi@0 216 bool is_nonvolatile() const { return (2 <= (value()&0x7F) && (value()&0x7F) <= 4 ); }
aoqi@0 217
aoqi@0 218 const char* name() const;
aoqi@0 219 };
aoqi@0 220
aoqi@0 221 // The (parts of the) condition register(s) of the PPC architecture
aoqi@0 222 // sys/ioctl.h on AIX defines CR0-CR3, so I name these CCR.
aoqi@0 223 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR0, (0));
aoqi@0 224 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR1, (1));
aoqi@0 225 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR2, (2));
aoqi@0 226 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR3, (3));
aoqi@0 227 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR4, (4));
aoqi@0 228 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR5, (5));
aoqi@0 229 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR6, (6));
aoqi@0 230 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR7, (7));
aoqi@0 231
aoqi@0 232 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 233
aoqi@0 234 #define CCR0 ((ConditionRegister)(CCR0_ConditionRegisterEnumValue))
aoqi@0 235 #define CCR1 ((ConditionRegister)(CCR1_ConditionRegisterEnumValue))
aoqi@0 236 #define CCR2 ((ConditionRegister)(CCR2_ConditionRegisterEnumValue))
aoqi@0 237 #define CCR3 ((ConditionRegister)(CCR3_ConditionRegisterEnumValue))
aoqi@0 238 #define CCR4 ((ConditionRegister)(CCR4_ConditionRegisterEnumValue))
aoqi@0 239 #define CCR5 ((ConditionRegister)(CCR5_ConditionRegisterEnumValue))
aoqi@0 240 #define CCR6 ((ConditionRegister)(CCR6_ConditionRegisterEnumValue))
aoqi@0 241 #define CCR7 ((ConditionRegister)(CCR7_ConditionRegisterEnumValue))
aoqi@0 242
aoqi@0 243 #endif // DONT_USE_REGISTER_DEFINES
aoqi@0 244
aoqi@0 245
aoqi@0 246 // Use FloatRegister as shortcut
aoqi@0 247 class FloatRegisterImpl;
aoqi@0 248 typedef FloatRegisterImpl* FloatRegister;
aoqi@0 249
aoqi@0 250 inline FloatRegister as_FloatRegister(int encoding) {
aoqi@0 251 assert(encoding >= 0 && encoding < 32, "bad float register encoding");
aoqi@0 252 return (FloatRegister)(intptr_t)encoding;
aoqi@0 253 }
aoqi@0 254
aoqi@0 255 // The implementation of float registers for the PPC architecture
aoqi@0 256 class FloatRegisterImpl: public AbstractRegisterImpl {
aoqi@0 257 public:
aoqi@0 258 enum {
aoqi@0 259 number_of_registers = 32
aoqi@0 260 };
aoqi@0 261
aoqi@0 262 // construction
aoqi@0 263 inline friend FloatRegister as_FloatRegister(int encoding);
aoqi@0 264
aoqi@0 265 // accessors
aoqi@0 266 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
aoqi@0 267 VMReg as_VMReg();
aoqi@0 268 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
aoqi@0 269
aoqi@0 270 // testers
aoqi@0 271 bool is_valid() const { return (0 <= value() && value() < number_of_registers); }
aoqi@0 272
aoqi@0 273 const char* name() const;
aoqi@0 274 };
aoqi@0 275
aoqi@0 276 // The float registers of the PPC architecture
aoqi@0 277 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, (-1));
aoqi@0 278
aoqi@0 279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0, ( 0));
aoqi@0 280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1, ( 1));
aoqi@0 281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2, ( 2));
aoqi@0 282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3, ( 3));
aoqi@0 283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4, ( 4));
aoqi@0 284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5, ( 5));
aoqi@0 285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6, ( 6));
aoqi@0 286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7, ( 7));
aoqi@0 287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8, ( 8));
aoqi@0 288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9, ( 9));
aoqi@0 289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10, (10));
aoqi@0 290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11, (11));
aoqi@0 291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12, (12));
aoqi@0 292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13, (13));
aoqi@0 293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14, (14));
aoqi@0 294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15, (15));
aoqi@0 295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16, (16));
aoqi@0 296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17, (17));
aoqi@0 297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18, (18));
aoqi@0 298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19, (19));
aoqi@0 299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20, (20));
aoqi@0 300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21, (21));
aoqi@0 301 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22, (22));
aoqi@0 302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23, (23));
aoqi@0 303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24, (24));
aoqi@0 304 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25, (25));
aoqi@0 305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26, (26));
aoqi@0 306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27, (27));
aoqi@0 307 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28, (28));
aoqi@0 308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29, (29));
aoqi@0 309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30, (30));
aoqi@0 310 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31, (31));
aoqi@0 311
aoqi@0 312 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 313 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue))
aoqi@0 314 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue))
aoqi@0 315 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue))
aoqi@0 316 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue))
aoqi@0 317 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue))
aoqi@0 318 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue))
aoqi@0 319 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue))
aoqi@0 320 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue))
aoqi@0 321 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue))
aoqi@0 322 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue))
aoqi@0 323 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue))
aoqi@0 324 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue))
aoqi@0 325 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue))
aoqi@0 326 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue))
aoqi@0 327 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue))
aoqi@0 328 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue))
aoqi@0 329 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue))
aoqi@0 330 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue))
aoqi@0 331 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue))
aoqi@0 332 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue))
aoqi@0 333 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue))
aoqi@0 334 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue))
aoqi@0 335 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue))
aoqi@0 336 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue))
aoqi@0 337 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue))
aoqi@0 338 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue))
aoqi@0 339 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue))
aoqi@0 340 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue))
aoqi@0 341 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue))
aoqi@0 342 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue))
aoqi@0 343 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue))
aoqi@0 344 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue))
aoqi@0 345 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue))
aoqi@0 346 #endif // DONT_USE_REGISTER_DEFINES
aoqi@0 347
aoqi@0 348 // Use SpecialRegister as shortcut
aoqi@0 349 class SpecialRegisterImpl;
aoqi@0 350 typedef SpecialRegisterImpl* SpecialRegister;
aoqi@0 351
aoqi@0 352 inline SpecialRegister as_SpecialRegister(int encoding) {
aoqi@0 353 return (SpecialRegister)(intptr_t)encoding;
aoqi@0 354 }
aoqi@0 355
aoqi@0 356 // The implementation of special registers for the Power architecture (LR, CTR and friends)
aoqi@0 357 class SpecialRegisterImpl: public AbstractRegisterImpl {
aoqi@0 358 public:
aoqi@0 359 enum {
aoqi@0 360 number_of_registers = 6
aoqi@0 361 };
aoqi@0 362
aoqi@0 363 // construction
aoqi@0 364 inline friend SpecialRegister as_SpecialRegister(int encoding);
aoqi@0 365
aoqi@0 366 // accessors
aoqi@0 367 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
aoqi@0 368 VMReg as_VMReg();
aoqi@0 369
aoqi@0 370 // testers
aoqi@0 371 bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
aoqi@0 372
aoqi@0 373 const char* name() const;
aoqi@0 374 };
aoqi@0 375
aoqi@0 376 // The special registers of the PPC architecture
aoqi@0 377 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_XER, (0));
aoqi@0 378 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_LR, (1));
aoqi@0 379 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_CTR, (2));
aoqi@0 380 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_VRSAVE, (3));
aoqi@0 381 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_SPEFSCR, (4));
aoqi@0 382 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_PPR, (5));
aoqi@0 383
aoqi@0 384 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 385 #define SR_XER ((SpecialRegister)(SR_XER_SpecialRegisterEnumValue))
aoqi@0 386 #define SR_LR ((SpecialRegister)(SR_LR_SpecialRegisterEnumValue))
aoqi@0 387 #define SR_CTR ((SpecialRegister)(SR_CTR_SpecialRegisterEnumValue))
aoqi@0 388 #define SR_VRSAVE ((SpecialRegister)(SR_VRSAVE_SpecialRegisterEnumValue))
aoqi@0 389 #define SR_SPEFSCR ((SpecialRegister)(SR_SPEFSCR_SpecialRegisterEnumValue))
aoqi@0 390 #define SR_PPR ((SpecialRegister)(SR_PPR_SpecialRegisterEnumValue))
aoqi@0 391 #endif // DONT_USE_REGISTER_DEFINES
aoqi@0 392
aoqi@0 393
aoqi@0 394 // Use VectorRegister as shortcut
aoqi@0 395 class VectorRegisterImpl;
aoqi@0 396 typedef VectorRegisterImpl* VectorRegister;
aoqi@0 397
aoqi@0 398 inline VectorRegister as_VectorRegister(int encoding) {
aoqi@0 399 return (VectorRegister)(intptr_t)encoding;
aoqi@0 400 }
aoqi@0 401
aoqi@0 402 // The implementation of vector registers for the Power architecture
aoqi@0 403 class VectorRegisterImpl: public AbstractRegisterImpl {
aoqi@0 404 public:
aoqi@0 405 enum {
aoqi@0 406 number_of_registers = 32
aoqi@0 407 };
aoqi@0 408
aoqi@0 409 // construction
aoqi@0 410 inline friend VectorRegister as_VectorRegister(int encoding);
aoqi@0 411
aoqi@0 412 // accessors
aoqi@0 413 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
aoqi@0 414
aoqi@0 415 // testers
aoqi@0 416 bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
aoqi@0 417
aoqi@0 418 const char* name() const;
aoqi@0 419 };
aoqi@0 420
aoqi@0 421 // The Vector registers of the Power architecture
aoqi@0 422
aoqi@0 423 CONSTANT_REGISTER_DECLARATION(VectorRegister, vnoreg, (-1));
aoqi@0 424
aoqi@0 425 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR0, ( 0));
aoqi@0 426 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR1, ( 1));
aoqi@0 427 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR2, ( 2));
aoqi@0 428 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR3, ( 3));
aoqi@0 429 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR4, ( 4));
aoqi@0 430 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR5, ( 5));
aoqi@0 431 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR6, ( 6));
aoqi@0 432 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR7, ( 7));
aoqi@0 433 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR8, ( 8));
aoqi@0 434 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR9, ( 9));
aoqi@0 435 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR10, (10));
aoqi@0 436 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR11, (11));
aoqi@0 437 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR12, (12));
aoqi@0 438 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR13, (13));
aoqi@0 439 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR14, (14));
aoqi@0 440 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR15, (15));
aoqi@0 441 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR16, (16));
aoqi@0 442 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR17, (17));
aoqi@0 443 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR18, (18));
aoqi@0 444 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR19, (19));
aoqi@0 445 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR20, (20));
aoqi@0 446 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR21, (21));
aoqi@0 447 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR22, (22));
aoqi@0 448 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR23, (23));
aoqi@0 449 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR24, (24));
aoqi@0 450 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR25, (25));
aoqi@0 451 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR26, (26));
aoqi@0 452 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR27, (27));
aoqi@0 453 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR28, (28));
aoqi@0 454 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR29, (29));
aoqi@0 455 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR30, (30));
aoqi@0 456 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR31, (31));
aoqi@0 457
aoqi@0 458 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 459 #define vnoreg ((VectorRegister)(vnoreg_VectorRegisterEnumValue))
aoqi@0 460 #define VR0 ((VectorRegister)( VR0_VectorRegisterEnumValue))
aoqi@0 461 #define VR1 ((VectorRegister)( VR1_VectorRegisterEnumValue))
aoqi@0 462 #define VR2 ((VectorRegister)( VR2_VectorRegisterEnumValue))
aoqi@0 463 #define VR3 ((VectorRegister)( VR3_VectorRegisterEnumValue))
aoqi@0 464 #define VR4 ((VectorRegister)( VR4_VectorRegisterEnumValue))
aoqi@0 465 #define VR5 ((VectorRegister)( VR5_VectorRegisterEnumValue))
aoqi@0 466 #define VR6 ((VectorRegister)( VR6_VectorRegisterEnumValue))
aoqi@0 467 #define VR7 ((VectorRegister)( VR7_VectorRegisterEnumValue))
aoqi@0 468 #define VR8 ((VectorRegister)( VR8_VectorRegisterEnumValue))
aoqi@0 469 #define VR9 ((VectorRegister)( VR9_VectorRegisterEnumValue))
aoqi@0 470 #define VR10 ((VectorRegister)( VR10_VectorRegisterEnumValue))
aoqi@0 471 #define VR11 ((VectorRegister)( VR11_VectorRegisterEnumValue))
aoqi@0 472 #define VR12 ((VectorRegister)( VR12_VectorRegisterEnumValue))
aoqi@0 473 #define VR13 ((VectorRegister)( VR13_VectorRegisterEnumValue))
aoqi@0 474 #define VR14 ((VectorRegister)( VR14_VectorRegisterEnumValue))
aoqi@0 475 #define VR15 ((VectorRegister)( VR15_VectorRegisterEnumValue))
aoqi@0 476 #define VR16 ((VectorRegister)( VR16_VectorRegisterEnumValue))
aoqi@0 477 #define VR17 ((VectorRegister)( VR17_VectorRegisterEnumValue))
aoqi@0 478 #define VR18 ((VectorRegister)( VR18_VectorRegisterEnumValue))
aoqi@0 479 #define VR19 ((VectorRegister)( VR19_VectorRegisterEnumValue))
aoqi@0 480 #define VR20 ((VectorRegister)( VR20_VectorRegisterEnumValue))
aoqi@0 481 #define VR21 ((VectorRegister)( VR21_VectorRegisterEnumValue))
aoqi@0 482 #define VR22 ((VectorRegister)( VR22_VectorRegisterEnumValue))
aoqi@0 483 #define VR23 ((VectorRegister)( VR23_VectorRegisterEnumValue))
aoqi@0 484 #define VR24 ((VectorRegister)( VR24_VectorRegisterEnumValue))
aoqi@0 485 #define VR25 ((VectorRegister)( VR25_VectorRegisterEnumValue))
aoqi@0 486 #define VR26 ((VectorRegister)( VR26_VectorRegisterEnumValue))
aoqi@0 487 #define VR27 ((VectorRegister)( VR27_VectorRegisterEnumValue))
aoqi@0 488 #define VR28 ((VectorRegister)( VR28_VectorRegisterEnumValue))
aoqi@0 489 #define VR29 ((VectorRegister)( VR29_VectorRegisterEnumValue))
aoqi@0 490 #define VR30 ((VectorRegister)( VR30_VectorRegisterEnumValue))
aoqi@0 491 #define VR31 ((VectorRegister)( VR31_VectorRegisterEnumValue))
aoqi@0 492 #endif // DONT_USE_REGISTER_DEFINES
aoqi@0 493
aoqi@0 494
aoqi@0 495 // Maximum number of incoming arguments that can be passed in i registers.
aoqi@0 496 const int PPC_ARGS_IN_REGS_NUM = 8;
aoqi@0 497
aoqi@0 498
aoqi@0 499 // Need to know the total number of registers of all sorts for SharedInfo.
aoqi@0 500 // Define a class that exports it.
aoqi@0 501 class ConcreteRegisterImpl : public AbstractRegisterImpl {
aoqi@0 502 public:
aoqi@0 503 enum {
aoqi@0 504 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
aoqi@0 505 // There is no requirement that any ordering here matches any ordering c2 gives
aoqi@0 506 // it's optoregs.
aoqi@0 507 number_of_registers =
aoqi@0 508 ( RegisterImpl::number_of_registers +
aoqi@0 509 FloatRegisterImpl::number_of_registers )
aoqi@0 510 * 2 // register halves
aoqi@0 511 + ConditionRegisterImpl::number_of_registers // condition code registers
aoqi@0 512 + SpecialRegisterImpl::number_of_registers // special registers
aoqi@0 513 + VectorRegisterImpl::number_of_registers // vector registers
aoqi@0 514 };
aoqi@0 515
aoqi@0 516 static const int max_gpr;
aoqi@0 517 static const int max_fpr;
aoqi@0 518 static const int max_cnd;
aoqi@0 519 };
aoqi@0 520
aoqi@0 521 // Common register declarations used in assembler code.
aoqi@0 522 REGISTER_DECLARATION(Register, R0_SCRATCH, R0); // volatile
aoqi@0 523 REGISTER_DECLARATION(Register, R1_SP, R1); // non-volatile
aoqi@0 524 REGISTER_DECLARATION(Register, R2_TOC, R2); // volatile
aoqi@0 525 REGISTER_DECLARATION(Register, R3_RET, R3); // volatile
aoqi@0 526 REGISTER_DECLARATION(Register, R3_ARG1, R3); // volatile
aoqi@0 527 REGISTER_DECLARATION(Register, R4_ARG2, R4); // volatile
aoqi@0 528 REGISTER_DECLARATION(Register, R5_ARG3, R5); // volatile
aoqi@0 529 REGISTER_DECLARATION(Register, R6_ARG4, R6); // volatile
aoqi@0 530 REGISTER_DECLARATION(Register, R7_ARG5, R7); // volatile
aoqi@0 531 REGISTER_DECLARATION(Register, R8_ARG6, R8); // volatile
aoqi@0 532 REGISTER_DECLARATION(Register, R9_ARG7, R9); // volatile
aoqi@0 533 REGISTER_DECLARATION(Register, R10_ARG8, R10); // volatile
aoqi@0 534 REGISTER_DECLARATION(FloatRegister, F0_SCRATCH, F0); // volatile
aoqi@0 535 REGISTER_DECLARATION(FloatRegister, F1_RET, F1); // volatile
aoqi@0 536 REGISTER_DECLARATION(FloatRegister, F1_ARG1, F1); // volatile
aoqi@0 537 REGISTER_DECLARATION(FloatRegister, F2_ARG2, F2); // volatile
aoqi@0 538 REGISTER_DECLARATION(FloatRegister, F3_ARG3, F3); // volatile
aoqi@0 539 REGISTER_DECLARATION(FloatRegister, F4_ARG4, F4); // volatile
aoqi@0 540 REGISTER_DECLARATION(FloatRegister, F5_ARG5, F5); // volatile
aoqi@0 541 REGISTER_DECLARATION(FloatRegister, F6_ARG6, F6); // volatile
aoqi@0 542 REGISTER_DECLARATION(FloatRegister, F7_ARG7, F7); // volatile
aoqi@0 543 REGISTER_DECLARATION(FloatRegister, F8_ARG8, F8); // volatile
aoqi@0 544 REGISTER_DECLARATION(FloatRegister, F9_ARG9, F9); // volatile
aoqi@0 545 REGISTER_DECLARATION(FloatRegister, F10_ARG10, F10); // volatile
aoqi@0 546 REGISTER_DECLARATION(FloatRegister, F11_ARG11, F11); // volatile
aoqi@0 547 REGISTER_DECLARATION(FloatRegister, F12_ARG12, F12); // volatile
aoqi@0 548 REGISTER_DECLARATION(FloatRegister, F13_ARG13, F13); // volatile
aoqi@0 549
aoqi@0 550 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 551 #define R0_SCRATCH AS_REGISTER(Register, R0)
aoqi@0 552 #define R1_SP AS_REGISTER(Register, R1)
aoqi@0 553 #define R2_TOC AS_REGISTER(Register, R2)
aoqi@0 554 #define R3_RET AS_REGISTER(Register, R3)
aoqi@0 555 #define R3_ARG1 AS_REGISTER(Register, R3)
aoqi@0 556 #define R4_ARG2 AS_REGISTER(Register, R4)
aoqi@0 557 #define R5_ARG3 AS_REGISTER(Register, R5)
aoqi@0 558 #define R6_ARG4 AS_REGISTER(Register, R6)
aoqi@0 559 #define R7_ARG5 AS_REGISTER(Register, R7)
aoqi@0 560 #define R8_ARG6 AS_REGISTER(Register, R8)
aoqi@0 561 #define R9_ARG7 AS_REGISTER(Register, R9)
aoqi@0 562 #define R10_ARG8 AS_REGISTER(Register, R10)
aoqi@0 563 #define F0_SCRATCH AS_REGISTER(FloatRegister, F0)
aoqi@0 564 #define F1_RET AS_REGISTER(FloatRegister, F1)
aoqi@0 565 #define F1_ARG1 AS_REGISTER(FloatRegister, F1)
aoqi@0 566 #define F2_ARG2 AS_REGISTER(FloatRegister, F2)
aoqi@0 567 #define F3_ARG3 AS_REGISTER(FloatRegister, F3)
aoqi@0 568 #define F4_ARG4 AS_REGISTER(FloatRegister, F4)
aoqi@0 569 #define F5_ARG5 AS_REGISTER(FloatRegister, F5)
aoqi@0 570 #define F6_ARG6 AS_REGISTER(FloatRegister, F6)
aoqi@0 571 #define F7_ARG7 AS_REGISTER(FloatRegister, F7)
aoqi@0 572 #define F8_ARG8 AS_REGISTER(FloatRegister, F8)
aoqi@0 573 #define F9_ARG9 AS_REGISTER(FloatRegister, F9)
aoqi@0 574 #define F10_ARG10 AS_REGISTER(FloatRegister, F10)
aoqi@0 575 #define F11_ARG11 AS_REGISTER(FloatRegister, F11)
aoqi@0 576 #define F12_ARG12 AS_REGISTER(FloatRegister, F12)
aoqi@0 577 #define F13_ARG13 AS_REGISTER(FloatRegister, F13)
aoqi@0 578 #endif
aoqi@0 579
aoqi@0 580 // Register declarations to be used in frame manager assembly code.
aoqi@0 581 // Use only non-volatile registers in order to keep values across C-calls.
aoqi@0 582 #ifdef CC_INTERP
aoqi@0 583 REGISTER_DECLARATION(Register, R14_state, R14); // address of new cInterpreter.
aoqi@0 584 REGISTER_DECLARATION(Register, R15_prev_state, R15); // address of old cInterpreter
aoqi@0 585 #else // CC_INTERP
aoqi@0 586 REGISTER_DECLARATION(Register, R14_bcp, R14);
aoqi@0 587 REGISTER_DECLARATION(Register, R15_esp, R15);
aoqi@0 588 REGISTER_DECLARATION(FloatRegister, F15_ftos, F15);
aoqi@0 589 #endif // CC_INTERP
aoqi@0 590 REGISTER_DECLARATION(Register, R16_thread, R16); // address of current thread
aoqi@0 591 REGISTER_DECLARATION(Register, R17_tos, R17); // address of Java tos (prepushed).
aoqi@0 592 REGISTER_DECLARATION(Register, R18_locals, R18); // address of first param slot (receiver).
aoqi@0 593 REGISTER_DECLARATION(Register, R19_method, R19); // address of current method
aoqi@0 594 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 595 #ifdef CC_INTERP
aoqi@0 596 #define R14_state AS_REGISTER(Register, R14)
aoqi@0 597 #define R15_prev_state AS_REGISTER(Register, R15)
aoqi@0 598 #else // CC_INTERP
aoqi@0 599 #define R14_bcp AS_REGISTER(Register, R14)
aoqi@0 600 #define R15_esp AS_REGISTER(Register, R15)
aoqi@0 601 #define F15_ftos AS_REGISTER(FloatRegister, F15)
aoqi@0 602 #endif // CC_INTERP
aoqi@0 603 #define R16_thread AS_REGISTER(Register, R16)
aoqi@0 604 #define R17_tos AS_REGISTER(Register, R17)
aoqi@0 605 #define R18_locals AS_REGISTER(Register, R18)
aoqi@0 606 #define R19_method AS_REGISTER(Register, R19)
aoqi@0 607 #define R21_sender_SP AS_REGISTER(Register, R21)
aoqi@0 608 #define R23_method_handle AS_REGISTER(Register, R23)
aoqi@0 609 #endif
aoqi@0 610
aoqi@0 611 // Temporary registers to be used within frame manager. We can use
aoqi@0 612 // the non-volatiles because the call stub has saved them.
aoqi@0 613 // Use only non-volatile registers in order to keep values across C-calls.
aoqi@0 614 REGISTER_DECLARATION(Register, R21_tmp1, R21);
aoqi@0 615 REGISTER_DECLARATION(Register, R22_tmp2, R22);
aoqi@0 616 REGISTER_DECLARATION(Register, R23_tmp3, R23);
aoqi@0 617 REGISTER_DECLARATION(Register, R24_tmp4, R24);
aoqi@0 618 REGISTER_DECLARATION(Register, R25_tmp5, R25);
aoqi@0 619 REGISTER_DECLARATION(Register, R26_tmp6, R26);
aoqi@0 620 REGISTER_DECLARATION(Register, R27_tmp7, R27);
aoqi@0 621 REGISTER_DECLARATION(Register, R28_tmp8, R28);
aoqi@0 622 REGISTER_DECLARATION(Register, R29_tmp9, R29);
aoqi@0 623 #ifndef CC_INTERP
aoqi@0 624 REGISTER_DECLARATION(Register, R24_dispatch_addr, R24);
aoqi@0 625 REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
aoqi@0 626 REGISTER_DECLARATION(Register, R26_monitor, R26);
aoqi@0 627 REGISTER_DECLARATION(Register, R27_constPoolCache, R27);
aoqi@0 628 REGISTER_DECLARATION(Register, R28_mdx, R28);
aoqi@0 629 #endif // CC_INTERP
aoqi@0 630
aoqi@0 631 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 632 #define R21_tmp1 AS_REGISTER(Register, R21)
aoqi@0 633 #define R22_tmp2 AS_REGISTER(Register, R22)
aoqi@0 634 #define R23_tmp3 AS_REGISTER(Register, R23)
aoqi@0 635 #define R24_tmp4 AS_REGISTER(Register, R24)
aoqi@0 636 #define R25_tmp5 AS_REGISTER(Register, R25)
aoqi@0 637 #define R26_tmp6 AS_REGISTER(Register, R26)
aoqi@0 638 #define R27_tmp7 AS_REGISTER(Register, R27)
aoqi@0 639 #define R28_tmp8 AS_REGISTER(Register, R28)
aoqi@0 640 #define R29_tmp9 AS_REGISTER(Register, R29)
aoqi@0 641 #ifndef CC_INTERP
aoqi@0 642 // Lmonitors : monitor pointer
aoqi@0 643 // LcpoolCache: constant pool cache
aoqi@0 644 // mdx: method data index
aoqi@0 645 #define R24_dispatch_addr AS_REGISTER(Register, R24)
aoqi@0 646 #define R25_templateTableBase AS_REGISTER(Register, R25)
aoqi@0 647 #define R26_monitor AS_REGISTER(Register, R26)
aoqi@0 648 #define R27_constPoolCache AS_REGISTER(Register, R27)
aoqi@0 649 #define R28_mdx AS_REGISTER(Register, R28)
aoqi@0 650 #endif
aoqi@0 651
aoqi@0 652 #define CCR4_is_synced AS_REGISTER(ConditionRegister, CCR4)
aoqi@0 653 #endif
aoqi@0 654
aoqi@0 655 // Scratch registers are volatile.
aoqi@0 656 REGISTER_DECLARATION(Register, R11_scratch1, R11);
aoqi@0 657 REGISTER_DECLARATION(Register, R12_scratch2, R12);
aoqi@0 658 #ifndef DONT_USE_REGISTER_DEFINES
aoqi@0 659 #define R11_scratch1 AS_REGISTER(Register, R11)
aoqi@0 660 #define R12_scratch2 AS_REGISTER(Register, R12)
aoqi@0 661 #endif
aoqi@0 662
aoqi@0 663 #endif // CPU_PPC_VM_REGISTER_PPC_HPP

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